From: Maulik Shah <mkshah@codeaurora.org>
To: Douglas Anderson <dianders@chromium.org>,
Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Neeraj Upadhyay <neeraju@codeaurora.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
Stephen Boyd <swboyd@chromium.org>,
linux-gpio@vger.kernel.org,
Srinivas Ramana <sramana@codeaurora.org>,
linux-arm-msm@vger.kernel.org, Andy Gross <agross@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0
Date: Mon, 11 Jan 2021 21:26:23 +0530 [thread overview]
Message-ID: <3aaf589e-ece1-1b9c-52fd-f7e8274b4938@codeaurora.org> (raw)
In-Reply-To: <20210108093339.v5.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid>
Hi Doug,
Reviewed-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Maulik Shah <mkshah@codeaurora.org>
Thanks,
Maulik
On 1/8/2021 11:05 PM, Douglas Anderson wrote:
> There's currently a comment in the code saying function 0 is GPIO.
> Instead of hardcoding it, let's add a member where an SoC can specify
> it. No known SoCs use a number other than 0, but this just makes the
> code clearer. NOTE: no SoC code needs to be updated since we can rely
> on zero-initialization.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
>
> (no changes since v1)
>
> drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++--
> drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index e051aecf95c4..1d2a78452c2d 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -210,8 +210,8 @@ static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
> if (!g->nfuncs)
> return 0;
>
> - /* For now assume function 0 is GPIO because it always is */
> - return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
> + return msm_pinmux_set_mux(pctldev,
> + g->funcs[pctrl->soc->gpio_func], offset);
> }
>
> static const struct pinmux_ops msm_pinmux_ops = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
> index 333f99243c43..e31a5167c91e 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.h
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.h
> @@ -118,6 +118,7 @@ struct msm_gpio_wakeirq_map {
> * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
> * to be aware that their parent can't handle dual
> * edge interrupts.
> + * @gpio_func: Which function number is GPIO (usually 0).
> */
> struct msm_pinctrl_soc_data {
> const struct pinctrl_pin_desc *pins;
> @@ -134,6 +135,7 @@ struct msm_pinctrl_soc_data {
> const struct msm_gpio_wakeirq_map *wakeirq_map;
> unsigned int nwakeirq_map;
> bool wakeirq_dual_edge_errata;
> + unsigned int gpio_func;
> };
>
> extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2021-01-11 15:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-08 17:35 [PATCH v5 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Douglas Anderson
2021-01-08 17:35 ` [PATCH v5 2/4] pinctrl: qcom: No need to read-modify-write the interrupt status Douglas Anderson
2021-01-11 15:58 ` Maulik Shah
2021-01-14 7:01 ` Stephen Boyd
2021-01-14 16:33 ` Bjorn Andersson
2021-01-08 17:35 ` [PATCH v5 3/4] pinctrl: qcom: Properly clear "intr_ack_high" interrupts when unmasking Douglas Anderson
2021-01-11 15:59 ` Maulik Shah
2021-01-14 7:03 ` Stephen Boyd
2021-01-14 16:34 ` Bjorn Andersson
2021-01-08 17:35 ` [PATCH v5 4/4] pinctrl: qcom: Don't clear pending interrupts when enabling Douglas Anderson
2021-01-09 0:36 ` Linus Walleij
2021-01-16 1:04 ` Doug Anderson
2021-01-11 16:01 ` Maulik Shah
2021-01-14 7:14 ` Stephen Boyd
2021-01-14 17:07 ` Bjorn Andersson
2021-01-14 17:15 ` Bjorn Andersson
2021-01-14 17:58 ` Doug Anderson
2021-01-14 17:58 ` Doug Anderson
2021-01-14 21:04 ` Stephen Boyd
2021-01-11 15:56 ` Maulik Shah [this message]
2021-01-14 16:32 ` [PATCH v5 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3aaf589e-ece1-1b9c-52fd-f7e8274b4938@codeaurora.org \
--to=mkshah@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=dianders@chromium.org \
--cc=jason@lakedaemon.net \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maz@kernel.org \
--cc=neeraju@codeaurora.org \
--cc=rnayak@codeaurora.org \
--cc=sramana@codeaurora.org \
--cc=swboyd@chromium.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).