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[194.187.74.233]) by smtp.googlemail.com with ESMTPSA id x133sm292329lff.290.2021.11.25.04.28.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Nov 2021 04:28:22 -0800 (PST) Message-ID: <3acea66e-c5e1-ff6c-aedb-d9ee61dcf8ab@gmail.com> Date: Thu, 25 Nov 2021 13:28:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:95.0) Gecko/20100101 Thunderbird/95.0 Subject: Re: [PATCH V2 1/6] dt-bindings: pinctrl: support specifying pins, groups & functions To: Tony Lindgren Cc: Linus Walleij , Rob Herring , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= References: <20211124230439.17531-1-zajec5@gmail.com> <20211124230439.17531-2-zajec5@gmail.com> From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 25.11.2021 09:49, Tony Lindgren wrote: > * Rafał Miłecki [211124 23:05]: >> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml >> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml >> @@ -42,4 +42,44 @@ properties: >> This property can be set either globally for the pin controller or in >> child nodes for individual pin group control. >> >> + pins: >> + type: object >> + >> + patternProperties: >> + "^.*$": >> + type: object >> + >> + properties: >> + number: >> + description: Pin number >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + >> + additionalProperties: false > > Please don't introduce Linux kernel internal numbering here. It's > like bringing back the interrupt numbers again. This is a new bit to me and the reason why I got this binding that way. I had no idea pin numbering is system specific thing. I always thought pin numbers are present in every chip datasheets and that is just a part of hardware. Now I'm reading https://www.kernel.org/doc/Documentation/pinctrl.txt again it indeed seems to mention that numbering is handled in a way not related to specs: "I enumerated the pins from 0 in the upper left corner to 63 in the lower right corner.". Sorry for that, I hopefully understand your point correctly now. > Just make this into > a proper hardware offset from the controller base, so a reg property. > Sure in some cases the reg property is just an index depending on > the controller, we don't really care from the binding point of view. > > We already have #pinctrl-cells, so plase do something like the four > ximaginary examples below: > > #pinctrl-cells = <1>; > ... > pin@foo { > reg = <0xf00 MUX_MODE0>; > label = "foo_pin"; > }; > > > #pinctrl-cells = <2>; > ... > pin@foo { > reg = <0xf00 PIN_INPUT_PULLUP MUX_MODE3>; > }; > > > #pinctrl-cells = <2>; > ... > pin@f00 { > reg = <0xf00 DELAY_PS(0) DELAY_PS(0)>; > }; > > > #pinctrl-cells = <3>; > ... > pin@f00 { > reg = <0xf00 MUX_MODE3 PULL_UP_STRENGTH(36) PULL_DOWN_STRENGTH(20)>; > }; > > > Then let's attempt to use just standard numbers and defines for the > values where possible. Then a group of pins is just a list of the pin > phandles in the devicetree. I need to ask for help on understanding that reg = <...> syntax. (Why) do we need to put that extra info in a "reg" property? That seems like either: 1. Pin specific info or 2. Phandle arguments In the first case, instead of: pin@f00 { reg = <0xf00 MUX_MODE3 PULL_UP_STRENGTH(36) PULL_DOWN_STRENGTH(20)>; }; I'd rather use: pin@f00 { reg = <0xf00>; mux_mode3; pull_up_strength = <36>; pull_down_strength = <20>; }; In the second case, shouldn't that be something like: pins { bar: pin@f00 { reg = <0xf00>; #pinctrl-cells = <3>; }; }; groups { qux { pins = <&bar MUX_MODE3 PULL_UP_STRENGTH(36) PULL_DOWN_STRENGTH(20)>; } };