* [PATCH 0/7] Add pin control driver for BCM2712 SoC
@ 2024-07-31 6:28 Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Ivan T. Ivanov
` (7 more replies)
0 siblings, 8 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov
Hi,
The following patches add a pin control driver for the BCM2712 SoC and few
pin/gpio Devicetree nodes for Raspberry Pi 5.
Device driver is follow up version on what Andrea posted in April [1].
It is based on sources from here [2]. I just made few cosmetic changes
and addressed review comments from earlier submission. I don't have
documentation for this controller.
Patch 3 was already posted by Andrea and it is in Broadcom integration tree[3].
Unfortunately it is still not in the Linus tree[4]. So I added it here as base
for my changes and to easy building and testing.
Patch 5 wire up power button on RPi5
Patch 6 adds WiFi Devicetree node for RPi5
Patch 7 adds Bluetooth Devicetree node for RPi5
They are few complaints from checkpatch.pl. Like few lines over 100 columns,
which I keep that way for better readability or usage of EOPNOTSUPP,
but it is according pin control API document.
All this have been tested as kernel was directly booted RPi5 via
kernel= config.txt option and cmdline.txt file with following content
(Note I am using Tumbleweed RPi raw images)
# cat /boot/efi/cmdline.txt
root=/dev/mmcblk0p3 rootwait rw systemd.show_status=1 console=tty ignore_loglevel earlycon console=ttyAMA10,115200
With all these patches Bluetooth and Wifi are working fine (tm) with
firmware files provided by openSUSE Tumbleweed.
All comments and suggestions are welcome!
Happy hacking!
Ivan
[1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
[2] https://github.com/raspberrypi/linux/blob/rpi-6.6.y/drivers/pinctrl/bcm/pinctrl-bcm2712.c
[3] https://lore.kernel.org/lkml/20240605120712.3523290-1-florian.fainelli@broadcom.com/#t
[4] https://lore.kernel.org/all/bfc60a7e-54d2-48a6-a288-4fe76d66507a@gmx.net/
Andrea della Porta (1):
arm64: dts: broadcom: Add support for BCM2712
Ivan T. Ivanov (6):
dt-bindings: pinctrl: Add support for Broadcom STB pin controller
pinctrl: bcm: Add STB family pin controller driver
arm64: dts: broadcom: bcm2712: Add pin controller nodes
arm64: dts: broadcom: bcm2712: Add one more GPIO node
arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
arm64: dts: broadcom: bcm2712: Add UARTA controller node.
.../pinctrl/brcm,brcmstb-pinctrl.yaml | 73 +
arch/arm64/boot/dts/broadcom/Makefile | 1 +
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 203 +++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 357 +++++
drivers/pinctrl/bcm/Kconfig | 13 +
drivers/pinctrl/bcm/Makefile | 1 +
drivers/pinctrl/bcm/pinctrl-brcmstb.c | 1217 +++++++++++++++++
7 files changed, 1865 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi
create mode 100644 drivers/pinctrl/bcm/pinctrl-brcmstb.c
base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9
--
2.43.0
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-08-01 8:17 ` Krzysztof Kozlowski
2024-08-02 18:09 ` Stefan Wahren
2024-07-31 6:28 ` [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver Ivan T. Ivanov
` (6 subsequent siblings)
7 siblings, 2 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov
It looks like they are few revisions of this chip which varies
by number of pins. Perhaps not all of them are available on the
market. Perhaps some of them where early engineering samples,
I don't know. I decided to keep all of them just in case.
Cc: Andrea della Porta <andrea.porta@suse.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
---
.../pinctrl/brcm,brcmstb-pinctrl.yaml | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
new file mode 100644
index 000000000000..c5afdb49d784
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB family pin controller
+
+maintainers:
+ - Ivan T. Ivanov <iivanov@suse.de>
+
+description:
+ Broadcom's STB family memory-mapped pin controller.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2712-pinctrl
+ - brcm,bcm2712-aon-pinctrl
+ - brcm,bcm2712c0-pinctrl
+ - brcm,bcm2712c0-aon-pinctrl
+ - brcm,bcm2712d0-pinctrl
+ - brcm,bcm2712d0-aon-pinctrl
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ anyOf:
+ - type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ function:
+ enum:
+ [
+ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8,
+ aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm,
+ arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2,
+ bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii,
+ ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c,
+ hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out,
+ ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0,
+ sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e,
+ sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0,
+ te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0,
+ vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1,
+ vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3,
+ vc_uart4,
+ ]
+
+ pins:
+ items:
+ pattern: "^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$"
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ additionalProperties: false
+
+ - type: object
+ additionalProperties:
+ $ref: "#/additionalProperties/anyOf/0"
+
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-08-02 10:22 ` Phil Elwell
` (2 more replies)
2024-07-31 6:28 ` [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712 Ivan T. Ivanov
` (5 subsequent siblings)
7 siblings, 3 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov, Jonathan Bell,
Phil Elwell
This driver provide pin muxing and configuration functionality
for BCM2712 SoC used by RPi5. According to [1] this chips is
incarnation of chip used in Broadcom STB product line.
[1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
Cc: Jonathan Bell <jonathan@raspberrypi.com>
Cc: Phil Elwell <phil@raspberrypi.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
---
drivers/pinctrl/bcm/Kconfig | 13 +
drivers/pinctrl/bcm/Makefile | 1 +
drivers/pinctrl/bcm/pinctrl-brcmstb.c | 1217 +++++++++++++++++++++++++
3 files changed, 1231 insertions(+)
create mode 100644 drivers/pinctrl/bcm/pinctrl-brcmstb.c
diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
index 35b51ce4298e..2e1b8d444f58 100644
--- a/drivers/pinctrl/bcm/Kconfig
+++ b/drivers/pinctrl/bcm/Kconfig
@@ -3,6 +3,19 @@
# Broadcom pinctrl drivers
#
+config PINCTRL_BRCMSTB
+ tristate "Broadcom STB product line pin controller driver"
+ depends on OF && (ARCH_BRCMSTB || COMPILE_TEST)
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ help
+ This driver provide pin muxing and configuration functionality
+ for Broadcom STB product line chipsets. BCM2712 SoC is one of these
+ chipsets.
+
+ If M is selected the module will be called pinctrl-brcmstb.
+
config PINCTRL_BCM281XX
bool "Broadcom BCM281xx pinctrl driver"
depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile
index 82b868ec1471..5f790c14cc4c 100644
--- a/drivers/pinctrl/bcm/Makefile
+++ b/drivers/pinctrl/bcm/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o
+obj-$(CONFIG_PINCTRL_BRCMSTB) += pinctrl-brcmstb.o
obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
diff --git a/drivers/pinctrl/bcm/pinctrl-brcmstb.c b/drivers/pinctrl/bcm/pinctrl-brcmstb.c
new file mode 100644
index 000000000000..143c8c2e1d6d
--- /dev/null
+++ b/drivers/pinctrl/bcm/pinctrl-brcmstb.c
@@ -0,0 +1,1217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Broadcom brcmstb GPIO units (pinctrl only)
+ *
+ * Copyright (C) 2021-3 Raspberry Pi Ltd.
+ * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
+ *
+ * Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
+ * pinctrl-nomadik.c, please see original file for copyright information
+ * pinctrl-tegra.c, please see original file for copyright information
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define BRCMSTB_PULL_NONE 0
+#define BRCMSTB_PULL_DOWN 1
+#define BRCMSTB_PULL_UP 2
+#define BRCMSTB_PULL_MASK 0x3
+
+#define BRCMSTB_FSEL_COUNT 9
+#define BRCMSTB_FSEL_MASK 0xf
+
+#define FUNC(f) \
+ [func_##f] = #f
+
+#define PIN(i, f1, f2, f3, f4, f5, f6, f7, f8) \
+ [i] = { \
+ .funcs = { \
+ func_##f1, \
+ func_##f2, \
+ func_##f3, \
+ func_##f4, \
+ func_##f5, \
+ func_##f6, \
+ func_##f7, \
+ func_##f8, \
+ }, \
+ }
+
+#define MUX_BIT_VALID 0x8000
+#define REG_BIT_INVALID 0xffff
+
+#define BIT_TO_REG(b) (((b) >> 5) << 2)
+#define BIT_TO_SHIFT(b) ((b) & 0x1f)
+
+#define MUX_BIT(mr, mb) (MUX_BIT_VALID + ((mr) * 4) * 8 + (mb) * 4)
+#define GPIO_REGS(n, mr, mb, pr, pb) \
+ [n] = { MUX_BIT(mr, mb), ((pr) * 4) * 8 + (pb) * 2 }
+
+#define EMMC_REGS(n, pr, pb) \
+ [n] = { 0, ((pr) * 4) * 8 + (pb) * 2 }
+
+#define AGPIO_REGS(n, mr, mb, pr, pb) \
+ [n] = { MUX_BIT(mr, mb), ((pr) * 4) * 8 + (pb) * 2 }
+
+#define SGPIO_REGS(n, mr, mb) \
+ [(n) + 32] = { MUX_BIT(mr, mb), REG_BIT_INVALID }
+
+#define GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
+#define AGPIO_PIN(a) PINCTRL_PIN(a, "aon_gpio" #a)
+#define SGPIO_PIN(a) PINCTRL_PIN((a) + 32, "aon_sgpio" #a)
+
+struct pin_regs {
+ u16 mux_bit;
+ u16 pad_bit;
+};
+
+struct brcmstb_pin_funcs {
+ u8 funcs[BRCMSTB_FSEL_COUNT - 1];
+};
+
+struct brcmstb_pinctrl {
+ struct device *dev;
+ void __iomem *base;
+ struct pinctrl_dev *pctl_dev;
+ struct pinctrl_desc pctl_desc;
+ const struct pin_regs *pin_regs;
+ const struct brcmstb_pin_funcs *pin_funcs;
+ const char *const *gpio_groups;
+ struct pinctrl_gpio_range gpio_range;
+ /* Protect FSEL registers */
+ spinlock_t lock;
+};
+
+struct brcmstb_pdata {
+ const struct pinctrl_desc *pctl_desc;
+ const struct pinctrl_gpio_range *gpio_range;
+ const struct pin_regs *pin_regs;
+ const struct brcmstb_pin_funcs *pin_funcs;
+};
+
+enum brcmstb_funcs {
+ func_gpio,
+ func_alt1,
+ func_alt2,
+ func_alt3,
+ func_alt4,
+ func_alt5,
+ func_alt6,
+ func_alt7,
+ func_alt8,
+ func_aon_cpu_standbyb,
+ func_aon_fp_4sec_resetb,
+ func_aon_gpclk,
+ func_aon_pwm,
+ func_arm_jtag,
+ func_aud_fs_clk0,
+ func_avs_pmu_bsc,
+ func_bsc_m0,
+ func_bsc_m1,
+ func_bsc_m2,
+ func_bsc_m3,
+ func_clk_observe,
+ func_ctl_hdmi_5v,
+ func_enet0,
+ func_enet0_mii,
+ func_enet0_rgmii,
+ func_ext_sc_clk,
+ func_fl0,
+ func_fl1,
+ func_gpclk0,
+ func_gpclk1,
+ func_gpclk2,
+ func_hdmi_tx0_auto_i2c,
+ func_hdmi_tx0_bsc,
+ func_hdmi_tx1_auto_i2c,
+ func_hdmi_tx1_bsc,
+ func_i2s_in,
+ func_i2s_out,
+ func_ir_in,
+ func_mtsif,
+ func_mtsif_alt,
+ func_mtsif_alt1,
+ func_pdm,
+ func_pkt,
+ func_pm_led_out,
+ func_sc0,
+ func_sd0,
+ func_sd2,
+ func_sd_card_a,
+ func_sd_card_b,
+ func_sd_card_c,
+ func_sd_card_d,
+ func_sd_card_e,
+ func_sd_card_f,
+ func_sd_card_g,
+ func_spdif_out,
+ func_spi_m,
+ func_spi_s,
+ func_sr_edm_sense,
+ func_te0,
+ func_te1,
+ func_tsio,
+ func_uart0,
+ func_uart1,
+ func_uart2,
+ func_usb_pwr,
+ func_usb_vbus,
+ func_uui,
+ func_vc_i2c0,
+ func_vc_i2c3,
+ func_vc_i2c4,
+ func_vc_i2c5,
+ func_vc_i2csl,
+ func_vc_pcm,
+ func_vc_pwm0,
+ func_vc_pwm1,
+ func_vc_spi0,
+ func_vc_spi3,
+ func_vc_spi4,
+ func_vc_spi5,
+ func_vc_uart0,
+ func_vc_uart2,
+ func_vc_uart3,
+ func_vc_uart4,
+ func__,
+ func_count = func__
+};
+
+static const struct pin_regs bcm2712_c0_gpio_pin_regs[] = {
+ GPIO_REGS(0, 0, 0, 7, 7),
+ GPIO_REGS(1, 0, 1, 7, 8),
+ GPIO_REGS(2, 0, 2, 7, 9),
+ GPIO_REGS(3, 0, 3, 7, 10),
+ GPIO_REGS(4, 0, 4, 7, 11),
+ GPIO_REGS(5, 0, 5, 7, 12),
+ GPIO_REGS(6, 0, 6, 7, 13),
+ GPIO_REGS(7, 0, 7, 7, 14),
+ GPIO_REGS(8, 1, 0, 8, 0),
+ GPIO_REGS(9, 1, 1, 8, 1),
+ GPIO_REGS(10, 1, 2, 8, 2),
+ GPIO_REGS(11, 1, 3, 8, 3),
+ GPIO_REGS(12, 1, 4, 8, 4),
+ GPIO_REGS(13, 1, 5, 8, 5),
+ GPIO_REGS(14, 1, 6, 8, 6),
+ GPIO_REGS(15, 1, 7, 8, 7),
+ GPIO_REGS(16, 2, 0, 8, 8),
+ GPIO_REGS(17, 2, 1, 8, 9),
+ GPIO_REGS(18, 2, 2, 8, 10),
+ GPIO_REGS(19, 2, 3, 8, 11),
+ GPIO_REGS(20, 2, 4, 8, 12),
+ GPIO_REGS(21, 2, 5, 8, 13),
+ GPIO_REGS(22, 2, 6, 8, 14),
+ GPIO_REGS(23, 2, 7, 9, 0),
+ GPIO_REGS(24, 3, 0, 9, 1),
+ GPIO_REGS(25, 3, 1, 9, 2),
+ GPIO_REGS(26, 3, 2, 9, 3),
+ GPIO_REGS(27, 3, 3, 9, 4),
+ GPIO_REGS(28, 3, 4, 9, 5),
+ GPIO_REGS(29, 3, 5, 9, 6),
+ GPIO_REGS(30, 3, 6, 9, 7),
+ GPIO_REGS(31, 3, 7, 9, 8),
+ GPIO_REGS(32, 4, 0, 9, 9),
+ GPIO_REGS(33, 4, 1, 9, 10),
+ GPIO_REGS(34, 4, 2, 9, 11),
+ GPIO_REGS(35, 4, 3, 9, 12),
+ GPIO_REGS(36, 4, 4, 9, 13),
+ GPIO_REGS(37, 4, 5, 9, 14),
+ GPIO_REGS(38, 4, 6, 10, 0),
+ GPIO_REGS(39, 4, 7, 10, 1),
+ GPIO_REGS(40, 5, 0, 10, 2),
+ GPIO_REGS(41, 5, 1, 10, 3),
+ GPIO_REGS(42, 5, 2, 10, 4),
+ GPIO_REGS(43, 5, 3, 10, 5),
+ GPIO_REGS(44, 5, 4, 10, 6),
+ GPIO_REGS(45, 5, 5, 10, 7),
+ GPIO_REGS(46, 5, 6, 10, 8),
+ GPIO_REGS(47, 5, 7, 10, 9),
+ GPIO_REGS(48, 6, 0, 10, 10),
+ GPIO_REGS(49, 6, 1, 10, 11),
+ GPIO_REGS(50, 6, 2, 10, 12),
+ GPIO_REGS(51, 6, 3, 10, 13),
+ GPIO_REGS(52, 6, 4, 10, 14),
+ GPIO_REGS(53, 6, 5, 11, 0),
+ EMMC_REGS(54, 11, 1), /* EMMC_CMD */
+ EMMC_REGS(55, 11, 2), /* EMMC_DS */
+ EMMC_REGS(56, 11, 3), /* EMMC_CLK */
+ EMMC_REGS(57, 11, 4), /* EMMC_DAT0 */
+ EMMC_REGS(58, 11, 5), /* EMMC_DAT1 */
+ EMMC_REGS(59, 11, 6), /* EMMC_DAT2 */
+ EMMC_REGS(60, 11, 7), /* EMMC_DAT3 */
+ EMMC_REGS(61, 11, 8), /* EMMC_DAT4 */
+ EMMC_REGS(62, 11, 9), /* EMMC_DAT5 */
+ EMMC_REGS(63, 11, 10), /* EMMC_DAT6 */
+ EMMC_REGS(64, 11, 11), /* EMMC_DAT7 */
+};
+
+static struct pin_regs bcm2712_c0_aon_gpio_pin_regs[] = {
+ AGPIO_REGS(0, 3, 0, 6, 10),
+ AGPIO_REGS(1, 3, 1, 6, 11),
+ AGPIO_REGS(2, 3, 2, 6, 12),
+ AGPIO_REGS(3, 3, 3, 6, 13),
+ AGPIO_REGS(4, 3, 4, 6, 14),
+ AGPIO_REGS(5, 3, 5, 7, 0),
+ AGPIO_REGS(6, 3, 6, 7, 1),
+ AGPIO_REGS(7, 3, 7, 7, 2),
+ AGPIO_REGS(8, 4, 0, 7, 3),
+ AGPIO_REGS(9, 4, 1, 7, 4),
+ AGPIO_REGS(10, 4, 2, 7, 5),
+ AGPIO_REGS(11, 4, 3, 7, 6),
+ AGPIO_REGS(12, 4, 4, 7, 7),
+ AGPIO_REGS(13, 4, 5, 7, 8),
+ AGPIO_REGS(14, 4, 6, 7, 9),
+ AGPIO_REGS(15, 4, 7, 7, 10),
+ AGPIO_REGS(16, 5, 0, 7, 11),
+ SGPIO_REGS(0, 0, 0),
+ SGPIO_REGS(1, 0, 1),
+ SGPIO_REGS(2, 0, 2),
+ SGPIO_REGS(3, 0, 3),
+ SGPIO_REGS(4, 1, 0),
+ SGPIO_REGS(5, 2, 0),
+};
+
+static const struct pinctrl_pin_desc bcm2712_c0_gpio_pins[] = {
+ GPIO_PIN(0),
+ GPIO_PIN(1),
+ GPIO_PIN(2),
+ GPIO_PIN(3),
+ GPIO_PIN(4),
+ GPIO_PIN(5),
+ GPIO_PIN(6),
+ GPIO_PIN(7),
+ GPIO_PIN(8),
+ GPIO_PIN(9),
+ GPIO_PIN(10),
+ GPIO_PIN(11),
+ GPIO_PIN(12),
+ GPIO_PIN(13),
+ GPIO_PIN(14),
+ GPIO_PIN(15),
+ GPIO_PIN(16),
+ GPIO_PIN(17),
+ GPIO_PIN(18),
+ GPIO_PIN(19),
+ GPIO_PIN(20),
+ GPIO_PIN(21),
+ GPIO_PIN(22),
+ GPIO_PIN(23),
+ GPIO_PIN(24),
+ GPIO_PIN(25),
+ GPIO_PIN(26),
+ GPIO_PIN(27),
+ GPIO_PIN(28),
+ GPIO_PIN(29),
+ GPIO_PIN(30),
+ GPIO_PIN(31),
+ GPIO_PIN(32),
+ GPIO_PIN(33),
+ GPIO_PIN(34),
+ GPIO_PIN(35),
+ GPIO_PIN(36),
+ GPIO_PIN(37),
+ GPIO_PIN(38),
+ GPIO_PIN(39),
+ GPIO_PIN(40),
+ GPIO_PIN(41),
+ GPIO_PIN(42),
+ GPIO_PIN(43),
+ GPIO_PIN(44),
+ GPIO_PIN(45),
+ GPIO_PIN(46),
+ GPIO_PIN(47),
+ GPIO_PIN(48),
+ GPIO_PIN(49),
+ GPIO_PIN(50),
+ GPIO_PIN(51),
+ GPIO_PIN(52),
+ GPIO_PIN(53),
+ PINCTRL_PIN(54, "emmc_cmd"),
+ PINCTRL_PIN(55, "emmc_ds"),
+ PINCTRL_PIN(56, "emmc_clk"),
+ PINCTRL_PIN(57, "emmc_dat0"),
+ PINCTRL_PIN(58, "emmc_dat1"),
+ PINCTRL_PIN(59, "emmc_dat2"),
+ PINCTRL_PIN(60, "emmc_dat3"),
+ PINCTRL_PIN(61, "emmc_dat4"),
+ PINCTRL_PIN(62, "emmc_dat5"),
+ PINCTRL_PIN(63, "emmc_dat6"),
+ PINCTRL_PIN(64, "emmc_dat7"),
+};
+
+static struct pinctrl_pin_desc bcm2712_c0_aon_gpio_pins[] = {
+ AGPIO_PIN(0), AGPIO_PIN(1), AGPIO_PIN(2), AGPIO_PIN(3),
+ AGPIO_PIN(4), AGPIO_PIN(5), AGPIO_PIN(6), AGPIO_PIN(7),
+ AGPIO_PIN(8), AGPIO_PIN(9), AGPIO_PIN(10), AGPIO_PIN(11),
+ AGPIO_PIN(12), AGPIO_PIN(13), AGPIO_PIN(14), AGPIO_PIN(15),
+ AGPIO_PIN(16), SGPIO_PIN(0), SGPIO_PIN(1), SGPIO_PIN(2),
+ SGPIO_PIN(3), SGPIO_PIN(4), SGPIO_PIN(5),
+};
+
+static const struct pin_regs bcm2712_d0_gpio_pin_regs[] = {
+ GPIO_REGS(1, 0, 0, 4, 5),
+ GPIO_REGS(2, 0, 1, 4, 6),
+ GPIO_REGS(3, 0, 2, 4, 7),
+ GPIO_REGS(4, 0, 3, 4, 8),
+ GPIO_REGS(10, 0, 4, 4, 9),
+ GPIO_REGS(11, 0, 5, 4, 10),
+ GPIO_REGS(12, 0, 6, 4, 11),
+ GPIO_REGS(13, 0, 7, 4, 12),
+ GPIO_REGS(14, 1, 0, 4, 13),
+ GPIO_REGS(15, 1, 1, 4, 14),
+ GPIO_REGS(18, 1, 2, 5, 0),
+ GPIO_REGS(19, 1, 3, 5, 1),
+ GPIO_REGS(20, 1, 4, 5, 2),
+ GPIO_REGS(21, 1, 5, 5, 3),
+ GPIO_REGS(22, 1, 6, 5, 4),
+ GPIO_REGS(23, 1, 7, 5, 5),
+ GPIO_REGS(24, 2, 0, 5, 6),
+ GPIO_REGS(25, 2, 1, 5, 7),
+ GPIO_REGS(26, 2, 2, 5, 8),
+ GPIO_REGS(27, 2, 3, 5, 9),
+ GPIO_REGS(28, 2, 4, 5, 10),
+ GPIO_REGS(29, 2, 5, 5, 11),
+ GPIO_REGS(30, 2, 6, 5, 12),
+ GPIO_REGS(31, 2, 7, 5, 13),
+ GPIO_REGS(32, 3, 0, 5, 14),
+ GPIO_REGS(33, 3, 1, 6, 0),
+ GPIO_REGS(34, 3, 2, 6, 1),
+ GPIO_REGS(35, 3, 3, 6, 2),
+ EMMC_REGS(36, 6, 3), /* EMMC_CMD */
+ EMMC_REGS(37, 6, 4), /* EMMC_DS */
+ EMMC_REGS(38, 6, 5), /* EMMC_CLK */
+ EMMC_REGS(39, 6, 6), /* EMMC_DAT0 */
+ EMMC_REGS(40, 6, 7), /* EMMC_DAT1 */
+ EMMC_REGS(41, 6, 8), /* EMMC_DAT2 */
+ EMMC_REGS(42, 6, 9), /* EMMC_DAT3 */
+ EMMC_REGS(43, 6, 10), /* EMMC_DAT4 */
+ EMMC_REGS(44, 6, 11), /* EMMC_DAT5 */
+ EMMC_REGS(45, 6, 12), /* EMMC_DAT6 */
+ EMMC_REGS(46, 6, 13), /* EMMC_DAT7 */
+};
+
+static struct pin_regs bcm2712_d0_aon_gpio_pin_regs[] = {
+ AGPIO_REGS(0, 3, 0, 5, 9),
+ AGPIO_REGS(1, 3, 1, 5, 10),
+ AGPIO_REGS(2, 3, 2, 5, 11),
+ AGPIO_REGS(3, 3, 3, 5, 12),
+ AGPIO_REGS(4, 3, 4, 5, 13),
+ AGPIO_REGS(5, 3, 5, 5, 14),
+ AGPIO_REGS(6, 3, 6, 6, 0),
+ AGPIO_REGS(8, 3, 7, 6, 1),
+ AGPIO_REGS(9, 4, 0, 6, 2),
+ AGPIO_REGS(12, 4, 1, 6, 3),
+ AGPIO_REGS(13, 4, 2, 6, 4),
+ AGPIO_REGS(14, 4, 3, 6, 5),
+ SGPIO_REGS(0, 0, 0),
+ SGPIO_REGS(1, 0, 1),
+ SGPIO_REGS(2, 0, 2),
+ SGPIO_REGS(3, 0, 3),
+ SGPIO_REGS(4, 1, 0),
+ SGPIO_REGS(5, 2, 0),
+};
+
+static const struct pinctrl_pin_desc bcm2712_d0_gpio_pins[] = {
+ GPIO_PIN(1),
+ GPIO_PIN(2),
+ GPIO_PIN(3),
+ GPIO_PIN(4),
+ GPIO_PIN(10),
+ GPIO_PIN(11),
+ GPIO_PIN(12),
+ GPIO_PIN(13),
+ GPIO_PIN(14),
+ GPIO_PIN(15),
+ GPIO_PIN(18),
+ GPIO_PIN(19),
+ GPIO_PIN(20),
+ GPIO_PIN(21),
+ GPIO_PIN(22),
+ GPIO_PIN(23),
+ GPIO_PIN(24),
+ GPIO_PIN(25),
+ GPIO_PIN(26),
+ GPIO_PIN(27),
+ GPIO_PIN(28),
+ GPIO_PIN(29),
+ GPIO_PIN(30),
+ GPIO_PIN(31),
+ GPIO_PIN(32),
+ GPIO_PIN(33),
+ GPIO_PIN(34),
+ GPIO_PIN(35),
+ PINCTRL_PIN(36, "emmc_cmd"),
+ PINCTRL_PIN(37, "emmc_ds"),
+ PINCTRL_PIN(38, "emmc_clk"),
+ PINCTRL_PIN(39, "emmc_dat0"),
+ PINCTRL_PIN(40, "emmc_dat1"),
+ PINCTRL_PIN(41, "emmc_dat2"),
+ PINCTRL_PIN(42, "emmc_dat3"),
+ PINCTRL_PIN(43, "emmc_dat4"),
+ PINCTRL_PIN(44, "emmc_dat5"),
+ PINCTRL_PIN(45, "emmc_dat6"),
+ PINCTRL_PIN(46, "emmc_dat7"),
+};
+
+static struct pinctrl_pin_desc bcm2712_d0_aon_gpio_pins[] = {
+ AGPIO_PIN(0), AGPIO_PIN(1), AGPIO_PIN(2), AGPIO_PIN(3), AGPIO_PIN(4),
+ AGPIO_PIN(5), AGPIO_PIN(6), AGPIO_PIN(8), AGPIO_PIN(9), AGPIO_PIN(12),
+ AGPIO_PIN(13), AGPIO_PIN(14), SGPIO_PIN(0), SGPIO_PIN(1), SGPIO_PIN(2),
+ SGPIO_PIN(3), SGPIO_PIN(4), SGPIO_PIN(5),
+};
+
+static const char * const brcmstb_func_names[] = {
+ FUNC(gpio),
+ FUNC(alt1),
+ FUNC(alt2),
+ FUNC(alt3),
+ FUNC(alt4),
+ FUNC(alt5),
+ FUNC(alt6),
+ FUNC(alt7),
+ FUNC(alt8),
+ FUNC(aon_cpu_standbyb),
+ FUNC(aon_fp_4sec_resetb),
+ FUNC(aon_gpclk),
+ FUNC(aon_pwm),
+ FUNC(arm_jtag),
+ FUNC(aud_fs_clk0),
+ FUNC(avs_pmu_bsc),
+ FUNC(bsc_m0),
+ FUNC(bsc_m1),
+ FUNC(bsc_m2),
+ FUNC(bsc_m3),
+ FUNC(clk_observe),
+ FUNC(ctl_hdmi_5v),
+ FUNC(enet0),
+ FUNC(enet0_mii),
+ FUNC(enet0_rgmii),
+ FUNC(ext_sc_clk),
+ FUNC(fl0),
+ FUNC(fl1),
+ FUNC(gpclk0),
+ FUNC(gpclk1),
+ FUNC(gpclk2),
+ FUNC(hdmi_tx0_auto_i2c),
+ FUNC(hdmi_tx0_bsc),
+ FUNC(hdmi_tx1_auto_i2c),
+ FUNC(hdmi_tx1_bsc),
+ FUNC(i2s_in),
+ FUNC(i2s_out),
+ FUNC(ir_in),
+ FUNC(mtsif),
+ FUNC(mtsif_alt),
+ FUNC(mtsif_alt1),
+ FUNC(pdm),
+ FUNC(pkt),
+ FUNC(pm_led_out),
+ FUNC(sc0),
+ FUNC(sd0),
+ FUNC(sd2),
+ FUNC(sd_card_a),
+ FUNC(sd_card_b),
+ FUNC(sd_card_c),
+ FUNC(sd_card_d),
+ FUNC(sd_card_e),
+ FUNC(sd_card_f),
+ FUNC(sd_card_g),
+ FUNC(spdif_out),
+ FUNC(spi_m),
+ FUNC(spi_s),
+ FUNC(sr_edm_sense),
+ FUNC(te0),
+ FUNC(te1),
+ FUNC(tsio),
+ FUNC(uart0),
+ FUNC(uart1),
+ FUNC(uart2),
+ FUNC(usb_pwr),
+ FUNC(usb_vbus),
+ FUNC(uui),
+ FUNC(vc_i2c0),
+ FUNC(vc_i2c3),
+ FUNC(vc_i2c4),
+ FUNC(vc_i2c5),
+ FUNC(vc_i2csl),
+ FUNC(vc_pcm),
+ FUNC(vc_pwm0),
+ FUNC(vc_pwm1),
+ FUNC(vc_spi0),
+ FUNC(vc_spi3),
+ FUNC(vc_spi4),
+ FUNC(vc_spi5),
+ FUNC(vc_uart0),
+ FUNC(vc_uart2),
+ FUNC(vc_uart3),
+ FUNC(vc_uart4),
+};
+
+static const struct brcmstb_pin_funcs bcm2712_c0_aon_gpio_pin_funcs[] = {
+ PIN(0, ir_in, vc_spi0, vc_uart3, vc_i2c3, te0, vc_i2c0, _, _),
+ PIN(1, vc_pwm0, vc_spi0, vc_uart3, vc_i2c3, te1, aon_pwm, vc_i2c0, vc_pwm1),
+ PIN(2, vc_pwm0, vc_spi0, vc_uart3, ctl_hdmi_5v, fl0, aon_pwm, ir_in, vc_pwm1),
+ PIN(3, ir_in, vc_spi0, vc_uart3, aon_fp_4sec_resetb, fl1, sd_card_g, aon_gpclk, _),
+ PIN(4, gpclk0, vc_spi0, vc_i2csl, aon_gpclk, pm_led_out, aon_pwm, sd_card_g, vc_pwm0),
+ PIN(5, gpclk1, ir_in, vc_i2csl, clk_observe, aon_pwm, sd_card_g, vc_pwm0, _),
+ PIN(6, uart1, vc_uart4, gpclk2, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
+ PIN(7, uart1, vc_uart4, gpclk0, aon_pwm, vc_uart0, vc_spi3, _, _),
+ PIN(8, uart1, vc_uart4, vc_i2csl, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
+ PIN(9, uart1, vc_uart4, vc_i2csl, aon_pwm, vc_uart0, vc_spi3, _, _),
+ PIN(10, tsio, ctl_hdmi_5v, sc0, spdif_out, vc_spi5, usb_pwr, aon_gpclk, sd_card_f),
+ PIN(11, tsio, uart0, sc0, aud_fs_clk0, vc_spi5, usb_vbus, vc_uart2, sd_card_f),
+ PIN(12, tsio, uart0, vc_uart0, tsio, vc_spi5, usb_pwr, vc_uart2, sd_card_f),
+ PIN(13, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
+ PIN(14, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
+ PIN(15, ir_in, aon_fp_4sec_resetb, vc_uart0, pm_led_out, ctl_hdmi_5v, aon_pwm, aon_gpclk, _),
+ PIN(16, aon_cpu_standbyb, gpclk0, pm_led_out, ctl_hdmi_5v, vc_pwm0, usb_pwr, aud_fs_clk0, _),
+};
+
+static const struct brcmstb_pin_funcs bcm2712_c0_aon_sgpio_pin_funcs[] = {
+ PIN(0, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
+ PIN(1, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
+ PIN(2, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c4, ctl_hdmi_5v, _, _, _),
+ PIN(3, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c4, _, _, _, _),
+ PIN(4, avs_pmu_bsc, bsc_m2, vc_i2c5, ctl_hdmi_5v, _, _, _, _),
+ PIN(5, avs_pmu_bsc, bsc_m2, vc_i2c5, _, _, _, _, _),
+};
+
+static const struct brcmstb_pin_funcs bcm2712_c0_gpio_pin_funcs[] = {
+ PIN(0, bsc_m3, vc_i2c0, gpclk0, enet0, vc_pwm1, vc_spi0, ir_in, _),
+ PIN(1, bsc_m3, vc_i2c0, gpclk1, enet0, vc_pwm1, sr_edm_sense, vc_spi0, vc_uart3),
+ PIN(2, pdm, i2s_in, gpclk2, vc_spi4, pkt, vc_spi0, vc_uart3, _),
+ PIN(3, pdm, i2s_in, vc_spi4, pkt, vc_spi0, vc_uart3, _, _),
+ PIN(4, pdm, i2s_in, arm_jtag, vc_spi4, pkt, vc_spi0, vc_uart3, _),
+ PIN(5, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
+ PIN(6, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
+ PIN(7, i2s_out, spdif_out, arm_jtag, sd_card_e, vc_i2c3, enet0_rgmii, vc_pcm, vc_spi4),
+ PIN(8, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, vc_i2c3, enet0_mii, vc_pcm, vc_spi4),
+ PIN(9, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, enet0_mii, sd_card_c, vc_spi4, _),
+ PIN(10, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
+ PIN(11, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
+ PIN(12, spi_s, mtsif_alt1, i2s_in, i2s_out, vc_spi5, vc_i2csl, sd0, sd_card_d),
+ PIN(13, spi_s, mtsif_alt1, i2s_out, usb_vbus, vc_spi5, vc_i2csl, sd0, sd_card_d),
+ PIN(14, spi_s, vc_i2csl, enet0_rgmii, arm_jtag, vc_spi5, vc_pwm0, vc_i2c4, sd_card_d),
+ PIN(15, spi_s, vc_i2csl, vc_spi3, arm_jtag, vc_pwm0, vc_i2c4, gpclk0, _),
+ PIN(16, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, gpclk1, _),
+ PIN(17, sd_card_b, i2s_out, vc_spi3, i2s_in, ext_sc_clk, sd0, enet0_rgmii, gpclk2),
+ PIN(18, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, vc_pwm1, _),
+ PIN(19, sd_card_b, usb_pwr, vc_spi3, pkt, spdif_out, sd0, ir_in, vc_pwm1),
+ PIN(20, sd_card_b, uui, vc_uart0, arm_jtag, uart2, usb_pwr, vc_pcm, vc_uart4),
+ PIN(21, usb_pwr, uui, vc_uart0, arm_jtag, uart2, sd_card_b, vc_pcm, vc_uart4),
+ PIN(22, usb_pwr, enet0, vc_uart0, mtsif, uart2, usb_vbus, vc_pcm, vc_i2c5),
+ PIN(23, usb_vbus, enet0, vc_uart0, mtsif, uart2, i2s_out, vc_pcm, vc_i2c5),
+ PIN(24, mtsif, pkt, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3, _),
+ PIN(25, mtsif, pkt, sc0, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3),
+ PIN(26, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
+ PIN(27, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
+ PIN(28, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
+ PIN(29, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
+ PIN(30, mtsif, pkt, sc0, sd2, enet0_rgmii, gpclk0, vc_pwm0, _),
+ PIN(31, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_pwm0, _),
+ PIN(32, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_uart3, _),
+ PIN(33, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_uart3, _, _),
+ PIN(34, mtsif, pkt, ext_sc_clk, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _),
+ PIN(35, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _, _),
+ PIN(36, sd0, mtsif, sc0, i2s_in, vc_uart3, vc_uart2, _, _),
+ PIN(37, sd0, mtsif, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
+ PIN(38, sd0, mtsif_alt, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
+ PIN(39, sd0, mtsif_alt, sc0, vc_spi0, vc_uart3, vc_uart2, _, _),
+ PIN(40, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
+ PIN(41, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
+ PIN(42, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
+ PIN(43, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
+ PIN(44, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
+ PIN(45, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
+ PIN(46, vc_spi0, mtsif_alt, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m, _),
+ PIN(47, enet0, mtsif_alt, i2s_out, mtsif_alt1, arm_jtag, _, _, _),
+ PIN(48, sc0, usb_pwr, spdif_out, mtsif, _, _, _, _),
+ PIN(49, sc0, usb_pwr, aud_fs_clk0, mtsif, _, _, _, _),
+ PIN(50, sc0, usb_vbus, sc0, _, _, _, _, _),
+ PIN(51, sc0, enet0, sc0, sr_edm_sense, _, _, _, _),
+ PIN(52, sc0, enet0, vc_pwm1, _, _, _, _, _),
+ PIN(53, sc0, enet0_rgmii, ext_sc_clk, _, _, _, _, _),
+};
+
+static const struct brcmstb_pin_funcs bcm2712_d0_aon_gpio_pin_funcs[] = {
+ PIN(0, ir_in, vc_spi0, vc_uart0, vc_i2c3, uart0, vc_i2c0, _, _),
+ PIN(1, vc_pwm0, vc_spi0, vc_uart0, vc_i2c3, uart0, aon_pwm, vc_i2c0, vc_pwm1),
+ PIN(2, vc_pwm0, vc_spi0, vc_uart0, ctl_hdmi_5v, uart0, aon_pwm, ir_in, vc_pwm1),
+ PIN(3, ir_in, vc_spi0, vc_uart0, uart0, sd_card_g, aon_gpclk, _, _),
+ PIN(4, gpclk0, vc_spi0, pm_led_out, aon_pwm, sd_card_g, vc_pwm0, _, _),
+ PIN(5, gpclk1, ir_in, aon_pwm, sd_card_g, vc_pwm0, _, _, _),
+ PIN(6, uart1, vc_uart2, ctl_hdmi_5v, gpclk2, vc_spi3, _, _, _),
+ PIN(7, _, _, _, _, _, _, _, _),
+ PIN(8, uart1, vc_uart2, ctl_hdmi_5v, vc_spi0, vc_spi3, _, _, _),
+ PIN(9, uart1, vc_uart2, vc_uart0, aon_pwm, vc_spi0, vc_uart2, vc_spi3, _),
+ PIN(10, _, _, _, _, _, _, _, _),
+ PIN(11, _, _, _, _, _, _, _, _),
+ PIN(12, uart1, vc_uart2, vc_uart0, vc_spi0, usb_pwr, vc_uart2, vc_spi3, _),
+ PIN(13, bsc_m1, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3, _),
+ PIN(14, bsc_m1, aon_gpclk, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3),
+};
+
+static const struct brcmstb_pin_funcs bcm2712_d0_aon_sgpio_pin_funcs[] = {
+ PIN(0, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
+ PIN(1, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
+ PIN(2, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c0, ctl_hdmi_5v, _, _, _),
+ PIN(3, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c0, _, _, _, _),
+ PIN(4, avs_pmu_bsc, bsc_m2, vc_i2c3, ctl_hdmi_5v, _, _, _, _),
+ PIN(5, avs_pmu_bsc, bsc_m2, vc_i2c3, _, _, _, _, _),
+};
+
+static const struct brcmstb_pin_funcs bcm2712_d0_gpio_pin_funcs[] = {
+ PIN(1, vc_i2c0, usb_pwr, gpclk0, sd_card_e, vc_spi3, sr_edm_sense, vc_spi0, vc_uart0),
+ PIN(2, vc_i2c0, usb_pwr, gpclk1, sd_card_e, vc_spi3, clk_observe, vc_spi0, vc_uart0),
+ PIN(3, vc_i2c3, usb_vbus, gpclk2, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
+ PIN(4, vc_i2c3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
+ PIN(10, bsc_m3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, gpclk0, _, _),
+ PIN(11, bsc_m3, vc_spi3, clk_observe, sd_card_c, gpclk1, _, _, _),
+ PIN(12, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
+ PIN(13, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
+ PIN(14, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, sd_card_d, _, _),
+ PIN(15, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, gpclk0, _, _),
+ PIN(18, sd_card_f, vc_pwm1, _, _, _, _, _, _),
+ PIN(19, sd_card_f, usb_pwr, vc_pwm1, _, _, _, _, _),
+ PIN(20, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
+ PIN(21, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
+ PIN(22, sd_card_f, vc_uart0, vc_i2c3, _, _, _, _, _),
+ PIN(23, vc_uart0, vc_i2c3, _, _, _, _, _, _),
+ PIN(24, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
+ PIN(25, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
+ PIN(26, sd_card_b, vc_spi0, arm_jtag, uart0, usb_vbus, vc_uart2, vc_spi0, _),
+ PIN(27, sd_card_b, vc_spi0, arm_jtag, uart0, vc_uart2, vc_spi0, _, _),
+ PIN(28, sd_card_b, vc_spi0, arm_jtag, vc_i2c0, vc_spi0, _, _, _),
+ PIN(29, arm_jtag, vc_i2c0, vc_spi0, _, _, _, _, _),
+ PIN(30, sd2, gpclk0, vc_pwm0, _, _, _, _, _),
+ PIN(31, sd2, vc_spi3, vc_pwm0, _, _, _, _, _),
+ PIN(32, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
+ PIN(33, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
+ PIN(34, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
+ PIN(35, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
+};
+
+static inline u32 brcmstb_reg_rd(struct brcmstb_pinctrl *pc, unsigned int reg)
+{
+ return readl(pc->base + reg);
+}
+
+static inline void brcmstb_reg_wr(struct brcmstb_pinctrl *pc, unsigned int reg,
+ u32 val)
+{
+ writel(val, pc->base + reg);
+}
+
+static enum brcmstb_funcs brcmstb_pinctrl_fsel_get(struct brcmstb_pinctrl *pc,
+ unsigned int pin)
+{
+ u32 bit = pc->pin_regs[pin].mux_bit;
+ enum brcmstb_funcs func;
+ int fsel;
+ u32 val;
+
+ if (!bit)
+ return func_gpio;
+
+ bit &= ~MUX_BIT_VALID;
+
+ val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
+ fsel = (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_FSEL_MASK;
+ func = pc->pin_funcs[pin].funcs[fsel];
+
+ if (func >= func_count)
+ func = (enum brcmstb_funcs)fsel;
+
+ dev_dbg(pc->dev, "get %04x: %08x (%u => %s)\n",
+ BIT_TO_REG(bit), val, pin,
+ brcmstb_func_names[func]);
+
+ return func;
+}
+
+static void brcmstb_pinctrl_fsel_set(struct brcmstb_pinctrl *pc,
+ unsigned int pin, enum brcmstb_funcs func)
+{
+ u32 bit = pc->pin_regs[pin].mux_bit, val;
+ const u8 *pin_funcs;
+ unsigned long flags;
+ int fsel;
+ int cur;
+ int i;
+
+ if (!bit || func >= func_count)
+ return;
+
+ bit &= ~MUX_BIT_VALID;
+
+ fsel = BRCMSTB_FSEL_COUNT;
+
+ if (func >= BRCMSTB_FSEL_COUNT) {
+ /* Convert to an fsel number */
+ pin_funcs = pc->pin_funcs[pin].funcs;
+ for (i = 1; i < BRCMSTB_FSEL_COUNT; i++) {
+ if (pin_funcs[i - 1] == func) {
+ fsel = i;
+ break;
+ }
+ }
+ } else {
+ fsel = (enum brcmstb_funcs)func;
+ }
+
+ if (fsel >= BRCMSTB_FSEL_COUNT)
+ return;
+
+ spin_lock_irqsave(&pc->lock, flags);
+
+ val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
+ cur = (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_FSEL_MASK;
+
+ dev_dbg(pc->dev, "read %04x: %08x (%u => %s)\n",
+ BIT_TO_REG(bit), val, pin,
+ brcmstb_func_names[cur]);
+
+ if (cur != fsel) {
+ val &= ~(BRCMSTB_FSEL_MASK << BIT_TO_SHIFT(bit));
+ val |= fsel << BIT_TO_SHIFT(bit);
+
+ dev_dbg(pc->dev, "write %04x: %08x (%u <= %s)\n",
+ BIT_TO_REG(bit), val, pin,
+ brcmstb_func_names[fsel]);
+ brcmstb_reg_wr(pc, BIT_TO_REG(bit), val);
+ }
+
+ spin_unlock_irqrestore(&pc->lock, flags);
+}
+
+static int brcmstb_pctl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ return pc->pctl_desc.npins;
+}
+
+static const char *brcmstb_pctl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ return pc->gpio_groups[selector];
+}
+
+static int brcmstb_pctl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &pc->pctl_desc.pins[selector].number;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static void brcmstb_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int offset)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+ enum brcmstb_funcs fsel = brcmstb_pinctrl_fsel_get(pc, offset);
+ const char *fname = brcmstb_func_names[fsel];
+
+ seq_printf(s, "function %s", fname);
+}
+
+static void brcmstb_pctl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *maps,
+ unsigned int num_maps)
+{
+ int i;
+
+ for (i = 0; i < num_maps; i++)
+ if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
+ kfree(maps[i].data.configs.configs);
+
+ kfree(maps);
+}
+
+static const struct pinctrl_ops brcmstb_pctl_ops = {
+ .get_groups_count = brcmstb_pctl_get_groups_count,
+ .get_group_name = brcmstb_pctl_get_group_name,
+ .get_group_pins = brcmstb_pctl_get_group_pins,
+ .pin_dbg_show = brcmstb_pctl_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = brcmstb_pctl_dt_free_map,
+};
+
+static int brcmstb_pmx_free(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ /* disable by setting to GPIO */
+ brcmstb_pinctrl_fsel_set(pc, offset, func_gpio);
+ return 0;
+}
+
+static int brcmstb_pmx_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ return func_count;
+}
+
+static const char *brcmstb_pmx_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return (selector < func_count) ? brcmstb_func_names[selector] : NULL;
+}
+
+static int brcmstb_pmx_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const char *const **groups,
+ unsigned *const num_groups)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pc->gpio_groups;
+ *num_groups = pc->pctl_desc.npins;
+
+ return 0;
+}
+
+static int brcmstb_pmx_set(struct pinctrl_dev *pctldev,
+ unsigned int func_selector,
+ unsigned int group_selector)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+ const struct pinctrl_desc *pctldesc = &pc->pctl_desc;
+ const struct pinctrl_pin_desc *pindesc;
+
+ if (group_selector >= pctldesc->npins)
+ return -EINVAL;
+
+ pindesc = &pctldesc->pins[group_selector];
+ brcmstb_pinctrl_fsel_set(pc, pindesc->number, func_selector);
+
+ return 0;
+}
+
+static int brcmstb_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ brcmstb_pinctrl_fsel_set(pc, pin, func_gpio);
+
+ return 0;
+}
+
+static void brcmstb_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+
+ /* disable by setting to GPIO */
+ brcmstb_pinctrl_fsel_set(pc, offset, func_gpio);
+}
+
+static const struct pinmux_ops brcmstb_pmx_ops = {
+ .free = brcmstb_pmx_free,
+ .get_functions_count = brcmstb_pmx_get_functions_count,
+ .get_function_name = brcmstb_pmx_get_function_name,
+ .get_function_groups = brcmstb_pmx_get_function_groups,
+ .set_mux = brcmstb_pmx_set,
+ .gpio_request_enable = brcmstb_pmx_gpio_request_enable,
+ .gpio_disable_free = brcmstb_pmx_gpio_disable_free,
+};
+
+static unsigned int brcmstb_pull_config_get(struct brcmstb_pinctrl *pc,
+ unsigned int pin)
+{
+ u32 bit = pc->pin_regs[pin].pad_bit, val;
+
+ if (bit == REG_BIT_INVALID)
+ return BRCMSTB_PULL_NONE;
+
+ val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
+ return (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_PULL_MASK;
+}
+
+static void brcmstb_pull_config_set(struct brcmstb_pinctrl *pc,
+ unsigned int pin, unsigned int arg)
+{
+ u32 bit = pc->pin_regs[pin].pad_bit, val;
+ unsigned long flags;
+
+ if (bit == REG_BIT_INVALID) {
+ dev_warn(pc->dev, "Can't set pulls for %s\n",
+ pc->gpio_groups[pin]);
+ return;
+ }
+
+ spin_lock_irqsave(&pc->lock, flags);
+
+ val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
+ val &= ~(BRCMSTB_PULL_MASK << BIT_TO_SHIFT(bit));
+ val |= (arg << BIT_TO_SHIFT(bit));
+ brcmstb_reg_wr(pc, BIT_TO_REG(bit), val);
+
+ spin_unlock_irqrestore(&pc->lock, flags);
+}
+
+static int brcmstb_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 arg;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_NONE);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_DOWN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_UP);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int brcmstb_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
+ u32 param, arg;
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_NONE);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_DOWN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_UP);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops brcmstb_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = brcmstb_pinconf_get,
+ .pin_config_set = brcmstb_pinconf_set,
+};
+
+static const struct pinctrl_desc bcm2712_c0_pinctrl_desc = {
+ .name = "pinctrl-bcm2712",
+ .pins = bcm2712_c0_gpio_pins,
+ .npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
+ .pctlops = &brcmstb_pctl_ops,
+ .pmxops = &brcmstb_pmx_ops,
+ .confops = &brcmstb_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static const struct pinctrl_desc bcm2712_c0_aon_pinctrl_desc = {
+ .name = "aon-pinctrl-bcm2712",
+ .pins = bcm2712_c0_aon_gpio_pins,
+ .npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
+ .pctlops = &brcmstb_pctl_ops,
+ .pmxops = &brcmstb_pmx_ops,
+ .confops = &brcmstb_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static const struct pinctrl_desc bcm2712_d0_pinctrl_desc = {
+ .name = "pinctrl-bcm2712",
+ .pins = bcm2712_d0_gpio_pins,
+ .npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
+ .pctlops = &brcmstb_pctl_ops,
+ .pmxops = &brcmstb_pmx_ops,
+ .confops = &brcmstb_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static const struct pinctrl_desc bcm2712_d0_aon_pinctrl_desc = {
+ .name = "aon-pinctrl-bcm2712",
+ .pins = bcm2712_d0_aon_gpio_pins,
+ .npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
+ .pctlops = &brcmstb_pctl_ops,
+ .pmxops = &brcmstb_pmx_ops,
+ .confops = &brcmstb_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static const struct pinctrl_gpio_range bcm2712_c0_pinctrl_gpio_range = {
+ .name = "pinctrl-bcm2712",
+ .npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
+};
+
+static const struct pinctrl_gpio_range bcm2712_c0_aon_pinctrl_gpio_range = {
+ .name = "aon-pinctrl-bcm2712",
+ .npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
+};
+
+static const struct pinctrl_gpio_range bcm2712_d0_pinctrl_gpio_range = {
+ .name = "pinctrl-bcm2712",
+ .npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
+};
+
+static const struct pinctrl_gpio_range bcm2712_d0_aon_pinctrl_gpio_range = {
+ .name = "aon-pinctrl-bcm2712",
+ .npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
+};
+
+static const struct brcmstb_pdata bcm2712_c0_pdata = {
+ .pctl_desc = &bcm2712_c0_pinctrl_desc,
+ .gpio_range = &bcm2712_c0_pinctrl_gpio_range,
+ .pin_regs = bcm2712_c0_gpio_pin_regs,
+ .pin_funcs = bcm2712_c0_gpio_pin_funcs,
+};
+
+static const struct brcmstb_pdata bcm2712_c0_aon_pdata = {
+ .pctl_desc = &bcm2712_c0_aon_pinctrl_desc,
+ .gpio_range = &bcm2712_c0_aon_pinctrl_gpio_range,
+ .pin_regs = bcm2712_c0_aon_gpio_pin_regs,
+ .pin_funcs = bcm2712_c0_aon_gpio_pin_funcs,
+};
+
+static const struct brcmstb_pdata bcm2712_d0_pdata = {
+ .pctl_desc = &bcm2712_d0_pinctrl_desc,
+ .gpio_range = &bcm2712_d0_pinctrl_gpio_range,
+ .pin_regs = bcm2712_d0_gpio_pin_regs,
+ .pin_funcs = bcm2712_d0_gpio_pin_funcs,
+};
+
+static const struct brcmstb_pdata bcm2712_d0_aon_pdata = {
+ .pctl_desc = &bcm2712_d0_aon_pinctrl_desc,
+ .gpio_range = &bcm2712_d0_aon_pinctrl_gpio_range,
+ .pin_regs = bcm2712_d0_aon_gpio_pin_regs,
+ .pin_funcs = bcm2712_d0_aon_gpio_pin_funcs,
+};
+
+static const struct of_device_id brcmstb_pinctrl_match[] = {
+ {
+ .compatible = "brcm,bcm2712-pinctrl",
+ .data = &bcm2712_c0_pdata
+ },
+ {
+ .compatible = "brcm,bcm2712-aon-pinctrl",
+ .data = &bcm2712_c0_aon_pdata
+ },
+
+ {
+ .compatible = "brcm,bcm2712c0-pinctrl",
+ .data = &bcm2712_c0_pdata
+ },
+ {
+ .compatible = "brcm,bcm2712c0-aon-pinctrl",
+ .data = &bcm2712_c0_aon_pdata
+ },
+
+ {
+ .compatible = "brcm,bcm2712d0-pinctrl",
+ .data = &bcm2712_d0_pdata
+ },
+ {
+ .compatible = "brcm,bcm2712d0-aon-pinctrl",
+ .data = &bcm2712_d0_aon_pdata
+ },
+ { /* sentinel */ }
+};
+
+static int brcmstb_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct brcmstb_pdata *pdata;
+ const struct of_device_id *match;
+ struct brcmstb_pinctrl *pc;
+ const char **names;
+ int num_pins, i;
+
+ match = of_match_node(brcmstb_pinctrl_match, np);
+ pdata = match->data;
+
+ pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+ if (!pc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pc);
+ pc->dev = dev;
+ spin_lock_init(&pc->lock);
+
+ pc->base = devm_of_iomap(dev, np, 0, NULL);
+ if (IS_ERR(pc->base))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->base),
+ "Could not get IO memory\n");
+
+ pc->pctl_desc = *pdata->pctl_desc;
+ num_pins = pc->pctl_desc.npins;
+ names = devm_kmalloc_array(dev, num_pins, sizeof(const char *),
+ GFP_KERNEL);
+ if (!names)
+ return -ENOMEM;
+
+ for (i = 0; i < num_pins; i++)
+ names[i] = pc->pctl_desc.pins[i].name;
+
+ pc->gpio_groups = names;
+ pc->pin_regs = pdata->pin_regs;
+ pc->pin_funcs = pdata->pin_funcs;
+ pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
+ if (IS_ERR(pc->pctl_dev))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->pctl_dev),
+ "Failed to register pinctrl device\n");
+
+ pc->gpio_range = *pdata->gpio_range;
+ pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
+
+ return 0;
+}
+
+static struct platform_driver brcmstb_pinctrl_driver = {
+ .probe = brcmstb_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-brcmstb",
+ .of_match_table = brcmstb_pinctrl_match,
+ .suppress_bind_attrs = true,
+ },
+};
+module_platform_driver(brcmstb_pinctrl_driver);
+
+MODULE_AUTHOR("Phil Elwell");
+MODULE_AUTHOR("Jonathan Bell");
+MODULE_AUTHOR("Ivan T. Ivanov");
+MODULE_DESCRIPTION("Broadcom brcmstb pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-07-31 21:57 ` Florian Fainelli
2024-07-31 6:28 ` [PATCH 4/7] arm64: dts: broadcom: bcm2712: Add pin controller nodes Ivan T. Ivanov
` (4 subsequent siblings)
7 siblings, 1 reply; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel
From: Andrea della Porta <andrea.porta@suse.com>
The BCM2712 SoC family can be found on Raspberry Pi 5.
Add minimal SoC and board (Rpi5 specific) dts file to be able to
boot from SD card and use console on debug UART.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
---
arch/arm64/boot/dts/broadcom/Makefile | 1 +
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 62 ++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 302 ++++++++++++++++++
3 files changed, 365 insertions(+)
create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index 8b4591ddd27c..92565e9781ad 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -6,6 +6,7 @@ DTC_FLAGS := -@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \
+ bcm2712-rpi-5-b.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
new file mode 100644
index 000000000000..b5921437e09f
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "bcm2712.dtsi"
+
+/ {
+ compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
+ model = "Raspberry Pi 5";
+
+ aliases {
+ serial10 = &uart0;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial10:115200n8";
+ };
+
+ /* Will be filled by the bootloader */
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0x28000000>;
+ };
+
+ sd_io_1v8_reg: sd-io-1v8-reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-sd-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-settling-time-us = <5000>;
+ gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ };
+
+ sd_vcc_reg: sd-vcc-reg {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* The system UART */
+&uart0 {
+ status = "okay";
+};
+
+/* SDIO1 is used to drive the SD card */
+&sdio1 {
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ vmmc-supply = <&sd_vcc_reg>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
new file mode 100644
index 000000000000..398df13148bd
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,bcm2712";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gicv2>;
+
+ axi: axi {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ sdio1: mmc@1000fff000 {
+ compatible = "brcm,bcm2712-sdhci",
+ "brcm,sdhci-brcmstb";
+ reg = <0x10 0x00fff000 0x260>,
+ <0x10 0x00fff400 0x200>;
+ reg-names = "host", "cfg";
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_emmc2>;
+ clock-names = "sw_sdio";
+ mmc-ddr-3_3v;
+ };
+
+ gicv2: interrupt-controller@107fff9000 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "arm,gic-400";
+ reg = <0x10 0x7fff9000 0x1000>,
+ <0x10 0x7fffa000 0x2000>,
+ <0x10 0x7fffc000 0x2000>,
+ <0x10 0x7fffe000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ clocks {
+ /* The oscillator is the root of the clock tree. */
+ clk_osc: clk-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <54000000>;
+ };
+
+ clk_vpu: clk-vpu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <750000000>;
+ clock-output-names = "vpu-clock";
+ };
+
+ clk_uart: clk-uart {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <9216000>;
+ clock-output-names = "uart-clock";
+ };
+
+ clk_emmc2: clk-emmc2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ clock-output-names = "emmc2-clock";
+ };
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Source for d/i cache-line-size, cache-sets, cache-size
+ * https://developer.arm.com/documentation/100798/0401
+ * /L1-memory-system/About-the-L1-memory-system?lang=en
+ */
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x000>;
+ enable-method = "psci";
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x100>;
+ enable-method = "psci";
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x200>;
+ enable-method = "psci";
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ next-level-cache = <&l2_cache_l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x300>;
+ enable-method = "psci";
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
+ next-level-cache = <&l2_cache_l3>;
+ };
+
+ /* Source for cache-line-size and cache-sets:
+ * https://developer.arm.com/documentation/100798/0401
+ * /L2-memory-system/About-the-L2-memory-system?lang=en
+ * and for cache-size:
+ * https://www.raspberrypi.com/documentation/computers
+ * /processors.html#bcm2712
+ */
+ l2_cache_l0: l2-cache-l0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <128>;
+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l1: l2-cache-l1 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <128>;
+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l2: l2-cache-l2 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <128>;
+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l3: l2-cache-l3 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <128>;
+ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ /* Source for cache-line-size and cache-sets:
+ * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
+ * Source for cache-size:
+ * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
+ */
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
+ cache-level = <3>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ method = "smc";
+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ cpu_on = <0xc4000003>;
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ };
+
+ rmem: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ atf@0 {
+ reg = <0x0 0x0 0x80000>;
+ no-map;
+ };
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x4000000>; /* 64MB */
+ reusable;
+ linux,cma-default;
+ alloc-ranges = <0x0 0x00000000 0x40000000>;
+ };
+ };
+
+ soc: soc@107c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x7c000000 0x10 0x7c000000 0x04000000>;
+ /* Emulate a contiguous 30-bit address range for DMA */
+ dma-ranges = <0xc0000000 0x00 0x00000000 0x40000000>,
+ <0x7c000000 0x10 0x7c000000 0x04000000>;
+
+ system_timer: timer@7c003000 {
+ compatible = "brcm,bcm2835-system-timer";
+ reg = <0x7c003000 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <1000000>;
+ };
+
+ mailbox: mailbox@7c013880 {
+ compatible = "brcm,bcm2835-mbox";
+ reg = <0x7c013880 0x40>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <0>;
+ };
+
+ local_intc: local-intc@7cd00000 {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x7cd00000 0x100>;
+ };
+
+ uart0: serial@7d001000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7d001000 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_uart>, <&clk_vpu>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ interrupt-controller@7d517000 {
+ compatible = "brcm,bcm7271-l2-intc";
+ reg = <0x7d517000 0x10>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ status = "disabled";
+ };
+
+ gio_aon: gpio@7d517c00 {
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ reg = <0x7d517c00 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ // Don't use GIO_AON as an interrupt controller because it will
+ // clash with the firmware monitoring the PMIC interrupt via the VPU.
+ brcm,gpio-bank-widths = <17 6>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ /* This only applies to the ARMv7 stub */
+ arm,cpu-registers-not-fw-configured;
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 4/7] arm64: dts: broadcom: bcm2712: Add pin controller nodes
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
` (2 preceding siblings ...)
2024-07-31 6:28 ` [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712 Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-08-02 19:16 ` Stefan Wahren
2024-07-31 6:28 ` [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node Ivan T. Ivanov
` (3 subsequent siblings)
7 siblings, 1 reply; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov
Add pin-control devicetree nodes and used them to
explicitly define uSD card interface pin configuration.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
---
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 20 +++++++++++++++++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 10 ++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index b5921437e09f..8a0d20afebfe 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -53,10 +53,30 @@ &uart0 {
/* SDIO1 is used to drive the SD card */
&sdio1 {
+ pinctrl-0 = <&emmc_sd_pulls>, <&emmc_aon_cd_pins>;
+ pinctrl-names = "default";
vqmmc-supply = <&sd_io_1v8_reg>;
vmmc-supply = <&sd_vcc_reg>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
+ cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
+};
+
+&pinctrl_aon {
+ emmc_aon_cd_pins: emmc-aon-cd-pins {
+ function = "sd_card_g";
+ pins = "aon_gpio5";
+ bias-pull-up;
+ };
+};
+
+&pinctrl {
+
+ emmc_sd_pulls: emmc-sd-pulls {
+ pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
+ bias-pull-up;
+ };
+
};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 398df13148bd..1099171cd435 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -266,6 +266,16 @@ uart0: serial@7d001000 {
status = "disabled";
};
+ pinctrl: pinctrl@7d504100 {
+ compatible = "brcm,bcm2712-pinctrl";
+ reg = <0x7d504100 0x30>;
+ };
+
+ pinctrl_aon: pinctrl@7d510700 {
+ compatible = "brcm,bcm2712-aon-pinctrl";
+ reg = <0x7d510700 0x20>;
+ };
+
interrupt-controller@7d517000 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d517000 0x10>;
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
` (3 preceding siblings ...)
2024-07-31 6:28 ` [PATCH 4/7] arm64: dts: broadcom: bcm2712: Add pin controller nodes Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-07-31 22:11 ` Florian Fainelli
` (2 more replies)
2024-07-31 6:28 ` [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node Ivan T. Ivanov
` (2 subsequent siblings)
7 siblings, 3 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov
Add GPIO and related interrupt controller nodes and wire one
of the lines to power button.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
---
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 21 +++++++++++++++++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 21 +++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index 8a0d20afebfe..06e926af16b7 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include "bcm2712.dtsi"
/ {
@@ -44,6 +45,21 @@ sd_vcc_reg: sd-vcc-reg {
enable-active-high;
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
};
+
+ pwr-button {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_button_pins>;
+ status = "okay";
+
+ pwr_key: pwr {
+ label = "pwr_button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gio 20 GPIO_ACTIVE_LOW>;
+ debounce-interval = <50>;
+ };
+ };
};
/* The system UART */
@@ -73,6 +89,11 @@ emmc_aon_cd_pins: emmc-aon-cd-pins {
};
&pinctrl {
+ pwr_button_pins: pwr-button-pins {
+ function = "gpio";
+ pins = "gpio20";
+ bias-pull-up;
+ };
emmc_sd_pulls: emmc-sd-pulls {
pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 1099171cd435..39d2419ffce2 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -271,6 +271,27 @@ pinctrl: pinctrl@7d504100 {
reg = <0x7d504100 0x30>;
};
+ main_irq: intc@7d508400 {
+ compatible = "brcm,bcm7271-l2-intc";
+ reg = <0x7d508400 0x10>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gio: gpio@7d508500 {
+ compatible = "brcm,brcmstb-gpio";
+ reg = <0x7d508500 0x40>;
+ interrupt-parent = <&main_irq>;
+ interrupts = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ brcm,gpio-bank-widths = <32 22>;
+ brcm,gpio-direct;
+ };
+
pinctrl_aon: pinctrl@7d510700 {
compatible = "brcm,bcm2712-aon-pinctrl";
reg = <0x7d510700 0x20>;
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
` (4 preceding siblings ...)
2024-07-31 6:28 ` [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-08-02 19:01 ` Stefan Wahren
2024-07-31 6:28 ` [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA " Ivan T. Ivanov
2024-07-31 14:25 ` [PATCH 0/7] Add pin control driver for BCM2712 SoC Rob Herring (Arm)
7 siblings, 1 reply; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov
Add SDIO2 node. On RPi5 it is connected to WiFi chip.
Add related pin, gpio and regulator definitions and
add WiFi node. With this and firmware already provided by
distributions, at least on openSUSE Tumbleweed, this is
sufficient to make WiFi operational on RPi5 \o/.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
---
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 55 +++++++++++++++++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 13 +++++
2 files changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index 06e926af16b7..b6bfe0abb774 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -46,6 +46,20 @@ sd_vcc_reg: sd-vcc-reg {
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
};
+ wl_on_reg: wl-on-reg {
+ compatible = "regulator-fixed";
+ regulator-name = "wl-on-regulator";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-0 = <&wl_on_pins>;
+ pinctrl-names = "default";
+
+ gpio = <&gio 28 GPIO_ACTIVE_HIGH>;
+
+ startup-delay-us = <150000>;
+ enable-active-high;
+ };
+
pwr-button {
compatible = "gpio-keys";
@@ -80,6 +94,25 @@ &sdio1 {
cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
};
+/* SDIO2 drives the WLAN interface */
+&sdio2 {
+ pinctrl-0 = <&sdio2_30_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ vmmc-supply = <&wl_on_reg>;
+ sd-uhs-ddr50;
+ non-removable;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wifi: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
+
&pinctrl_aon {
emmc_aon_cd_pins: emmc-aon-cd-pins {
function = "sd_card_g";
@@ -95,9 +128,31 @@ pwr_button_pins: pwr-button-pins {
bias-pull-up;
};
+ wl_on_pins: wl-on-pins {
+ function = "gpio";
+ pins = "gpio28";
+ };
+
emmc_sd_pulls: emmc-sd-pulls {
pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
bias-pull-up;
};
+ sdio2_30_pins: sdio2-30-pins {
+ pin-clk {
+ function = "sd2";
+ pins = "gpio30";
+ bias-disable;
+ };
+ pin-cmd {
+ function = "sd2";
+ pins = "gpio31";
+ bias-pull-up;
+ };
+ pins-dat {
+ function = "sd2";
+ pins = "gpio32", "gpio33", "gpio34", "gpio35";
+ bias-pull-up;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 39d2419ffce2..3c0663dc6712 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -27,6 +27,19 @@ sdio1: mmc@1000fff000 {
mmc-ddr-3_3v;
};
+ sdio2: mmc@1001100000 {
+ compatible = "brcm,bcm2712-sdhci";
+ reg = <0x10 0x01100000 0x260>,
+ <0x10 0x01100400 0x200>;
+ reg-names = "host", "cfg";
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_emmc2>;
+ sdhci-caps-mask = <0x0000C000 0x0>;
+ sdhci-caps = <0x0 0x0>;
+ mmc-ddr-3_3v;
+ status = "disabled";
+ };
+
gicv2: interrupt-controller@107fff9000 {
interrupt-controller;
#interrupt-cells = <3>;
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA controller node.
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
` (5 preceding siblings ...)
2024-07-31 6:28 ` [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node Ivan T. Ivanov
@ 2024-07-31 6:28 ` Ivan T. Ivanov
2024-07-31 22:13 ` Florian Fainelli
2024-08-02 19:12 ` Stefan Wahren
2024-07-31 14:25 ` [PATCH 0/7] Add pin control driver for BCM2712 SoC Rob Herring (Arm)
7 siblings, 2 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-07-31 6:28 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel, Ivan T. Ivanov
On RPi5 device Bluetooth chips is connected to UARTA
port. Add Bluetooth chips and related pin definitions.
With this and firmware already provided by distributions,
at least on openSUSE Tumbleweed, this is sufficient to make
Bluetooth operational on RPi5 \o/.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
---
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 45 +++++++++++++++++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 11 +++++
2 files changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index b6bfe0abb774..a557cbd8ba17 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -133,11 +133,39 @@ wl_on_pins: wl-on-pins {
pins = "gpio28";
};
+ bt_shutdown_pins: bt-shutdown-pins {
+ function = "gpio";
+ pins = "gpio29";
+ };
+
emmc_sd_pulls: emmc-sd-pulls {
pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
bias-pull-up;
};
+ uarta_24_pins: uarta-24-pins {
+ pin-rts {
+ function = "uart0";
+ pins = "gpio24";
+ bias-disable;
+ };
+ pin-cts {
+ function = "uart0";
+ pins = "gpio25";
+ bias-pull-up;
+ };
+ pin-txd {
+ function = "uart0";
+ pins = "gpio26";
+ bias-disable;
+ };
+ pin-rxd {
+ function = "uart0";
+ pins = "gpio27";
+ bias-pull-up;
+ };
+ };
+
sdio2_30_pins: sdio2-30-pins {
pin-clk {
function = "sd2";
@@ -156,3 +184,20 @@ pins-dat {
};
};
};
+
+/* uarta communicates with the BT module */
+&uarta {
+ uart-has-rtscts;
+ auto-flow-control;
+ status = "okay";
+ clock-frequency = <96000000>;
+ pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>;
+ pinctrl-names = "default";
+
+ bluetooth: bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>;
+ local-bd-address = [ 00 00 00 00 00 00 ];
+ };
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 3c0663dc6712..e972f94d6828 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -305,6 +305,17 @@ gio: gpio@7d508500 {
brcm,gpio-direct;
};
+ uarta: serial@7d50c000 {
+ compatible = "brcm,bcm7271-uart";
+ reg = <0x7d50c000 0x20>;
+ reg-names = "uart";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ skip-init;
+ status = "disabled";
+ };
+
pinctrl_aon: pinctrl@7d510700 {
compatible = "brcm,bcm2712-aon-pinctrl";
reg = <0x7d510700 0x20>;
--
2.43.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 0/7] Add pin control driver for BCM2712 SoC
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
` (6 preceding siblings ...)
2024-07-31 6:28 ` [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA " Ivan T. Ivanov
@ 2024-07-31 14:25 ` Rob Herring (Arm)
7 siblings, 0 replies; 34+ messages in thread
From: Rob Herring (Arm) @ 2024-07-31 14:25 UTC (permalink / raw)
To: Ivan T. Ivanov
Cc: conor+dt, devicetree, andrea.porta, florian.fainelli, linux-gpio,
krzk+dt, wahrenst, linux-arm-kernel, linus.walleij
On Wed, 31 Jul 2024 09:28:07 +0300, Ivan T. Ivanov wrote:
> Hi,
>
> The following patches add a pin control driver for the BCM2712 SoC and few
> pin/gpio Devicetree nodes for Raspberry Pi 5.
>
> Device driver is follow up version on what Andrea posted in April [1].
>
> It is based on sources from here [2]. I just made few cosmetic changes
> and addressed review comments from earlier submission. I don't have
> documentation for this controller.
>
> Patch 3 was already posted by Andrea and it is in Broadcom integration tree[3].
> Unfortunately it is still not in the Linus tree[4]. So I added it here as base
> for my changes and to easy building and testing.
>
> Patch 5 wire up power button on RPi5
>
> Patch 6 adds WiFi Devicetree node for RPi5
>
> Patch 7 adds Bluetooth Devicetree node for RPi5
>
> They are few complaints from checkpatch.pl. Like few lines over 100 columns,
> which I keep that way for better readability or usage of EOPNOTSUPP,
> but it is according pin control API document.
>
> All this have been tested as kernel was directly booted RPi5 via
> kernel= config.txt option and cmdline.txt file with following content
> (Note I am using Tumbleweed RPi raw images)
>
> # cat /boot/efi/cmdline.txt
> root=/dev/mmcblk0p3 rootwait rw systemd.show_status=1 console=tty ignore_loglevel earlycon console=ttyAMA10,115200
>
> With all these patches Bluetooth and Wifi are working fine (tm) with
> firmware files provided by openSUSE Tumbleweed.
>
> All comments and suggestions are welcome!
>
> Happy hacking!
> Ivan
>
> [1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
> [2] https://github.com/raspberrypi/linux/blob/rpi-6.6.y/drivers/pinctrl/bcm/pinctrl-bcm2712.c
> [3] https://lore.kernel.org/lkml/20240605120712.3523290-1-florian.fainelli@broadcom.com/#t
> [4] https://lore.kernel.org/all/bfc60a7e-54d2-48a6-a288-4fe76d66507a@gmx.net/
>
>
> Andrea della Porta (1):
> arm64: dts: broadcom: Add support for BCM2712
>
> Ivan T. Ivanov (6):
> dt-bindings: pinctrl: Add support for Broadcom STB pin controller
> pinctrl: bcm: Add STB family pin controller driver
> arm64: dts: broadcom: bcm2712: Add pin controller nodes
> arm64: dts: broadcom: bcm2712: Add one more GPIO node
> arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
> arm64: dts: broadcom: bcm2712: Add UARTA controller node.
>
> .../pinctrl/brcm,brcmstb-pinctrl.yaml | 73 +
> arch/arm64/boot/dts/broadcom/Makefile | 1 +
> .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 203 +++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 357 +++++
> drivers/pinctrl/bcm/Kconfig | 13 +
> drivers/pinctrl/bcm/Makefile | 1 +
> drivers/pinctrl/bcm/pinctrl-brcmstb.c | 1217 +++++++++++++++++
> 7 files changed, 1865 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> create mode 100644 drivers/pinctrl/bcm/pinctrl-brcmstb.c
>
>
> base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9
> --
> 2.43.0
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y broadcom/bcm2712-rpi-5-b.dtb' for 20240731062814.215833-1-iivanov@suse.de:
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: mmc@1001100000: compatible: 'oneOf' conditional failed, one must be fixed:
['brcm,bcm2712-sdhci'] is too short
'brcm,bcm2712-sdhci' is not one of ['brcm,bcm7216-sdhci']
from schema $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: mmc@1001100000: 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: mmc@1001100000: 'clock-names' is a required property
from schema $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: mmc@1001100000: Unevaluated properties are not allowed ('compatible', 'sdhci-caps', 'sdhci-caps-mask' were unexpected)
from schema $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: wifi@1: Unevaluated properties are not allowed ('local-mac-address' was unexpected)
from schema $id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: /soc@107c000000/timer@7c003000: failed to match any schema with compatible: ['brcm,bcm2835-system-timer']
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: /soc@107c000000/local-intc@7cd00000: failed to match any schema with compatible: ['brcm,bcm2836-l1-intc']
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: intc@7d508400: $nodename:0: 'intc@7d508400' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
from schema $id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: gpio@7d508500: compatible:0: 'brcm,brcmstb-gpio' is not one of ['brcm,bcm7445-gpio']
from schema $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: gpio@7d508500: compatible: ['brcm,brcmstb-gpio'] is too short
from schema $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: gpio@7d508500: 'brcm,gpio-direct' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: serial@7d50c000: 'clocks' is a required property
from schema $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: serial@7d50c000: 'clock-names' is a required property
from schema $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: serial@7d50c000: 'interrupt-names' is a required property
from schema $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: serial@7d50c000: Unevaluated properties are not allowed ('auto-flow-control', 'clock-frequency', 'reg-io-width', 'reg-shift', 'skip-init' were unexpected)
from schema $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: bluetooth: 'local-bd-address' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/broadcom-bluetooth.yaml#
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dtb: pwr-button: 'pwr' does not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/input/gpio-keys.yaml#
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712
2024-07-31 6:28 ` [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712 Ivan T. Ivanov
@ 2024-07-31 21:57 ` Florian Fainelli
2024-08-01 6:45 ` Ivan T. Ivanov
0 siblings, 1 reply; 34+ messages in thread
From: Florian Fainelli @ 2024-07-31 21:57 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, wahrenst, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel
On 7/30/24 23:28, Ivan T. Ivanov wrote:
> From: Andrea della Porta <andrea.porta@suse.com>
>
> The BCM2712 SoC family can be found on Raspberry Pi 5.
> Add minimal SoC and board (Rpi5 specific) dts file to be able to
> boot from SD card and use console on debug UART.
>
> Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
I have already applied this one:
https://github.com/Broadcom/stblinux/commit/faa3381267d01a389b13038504079c85c0bc4392
should I drop it and take this patch instead?
--
Florian
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node
2024-07-31 6:28 ` [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node Ivan T. Ivanov
@ 2024-07-31 22:11 ` Florian Fainelli
2024-08-01 7:19 ` Ivan T. Ivanov
2024-08-02 18:49 ` Stefan Wahren
2024-08-02 19:08 ` Stefan Wahren
2 siblings, 1 reply; 34+ messages in thread
From: Florian Fainelli @ 2024-07-31 22:11 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel
On 7/30/24 23:28, Ivan T. Ivanov wrote:
> Add GPIO and related interrupt controller nodes and wire one
> of the lines to power button.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 21 +++++++++++++++++++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 21 +++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> index 8a0d20afebfe..06e926af16b7 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> @@ -2,6 +2,7 @@
> /dts-v1/;
>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> #include "bcm2712.dtsi"
>
> / {
> @@ -44,6 +45,21 @@ sd_vcc_reg: sd-vcc-reg {
> enable-active-high;
> gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
> };
> +
> + pwr-button {
> + compatible = "gpio-keys";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwr_button_pins>;
> + status = "okay";
> +
> + pwr_key: pwr {
> + label = "pwr_button";
> + linux,code = <KEY_POWER>;
> + gpios = <&gio 20 GPIO_ACTIVE_LOW>;
> + debounce-interval = <50>;
> + };
> + };
> };
>
> /* The system UART */
> @@ -73,6 +89,11 @@ emmc_aon_cd_pins: emmc-aon-cd-pins {
> };
>
> &pinctrl {
> + pwr_button_pins: pwr-button-pins {
> + function = "gpio";
> + pins = "gpio20";
> + bias-pull-up;
> + };
>
> emmc_sd_pulls: emmc-sd-pulls {
> pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 1099171cd435..39d2419ffce2 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -271,6 +271,27 @@ pinctrl: pinctrl@7d504100 {
> reg = <0x7d504100 0x30>;
> };
>
> + main_irq: intc@7d508400 {
> + compatible = "brcm,bcm7271-l2-intc";
> + reg = <0x7d508400 0x10>;
> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gio: gpio@7d508500 {
> + compatible = "brcm,brcmstb-gpio";
> + reg = <0x7d508500 0x40>;
> + interrupt-parent = <&main_irq>;
> + interrupts = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + brcm,gpio-bank-widths = <32 22>;
> + brcm,gpio-direct;
Undocumented and unsupported property upstream, what does it do? Other
than that, LGTM.
--
Florian
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA controller node.
2024-07-31 6:28 ` [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA " Ivan T. Ivanov
@ 2024-07-31 22:13 ` Florian Fainelli
2024-08-01 7:50 ` Ivan T. Ivanov
2024-08-02 19:12 ` Stefan Wahren
1 sibling, 1 reply; 34+ messages in thread
From: Florian Fainelli @ 2024-07-31 22:13 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel
On 7/30/24 23:28, Ivan T. Ivanov wrote:
> On RPi5 device Bluetooth chips is connected to UARTA
> port. Add Bluetooth chips and related pin definitions.
> With this and firmware already provided by distributions,
> at least on openSUSE Tumbleweed, this is sufficient to make
> Bluetooth operational on RPi5 \o/.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
[snip]
> sdio2_30_pins: sdio2-30-pins {
> pin-clk {
> function = "sd2";
> @@ -156,3 +184,20 @@ pins-dat {
> };
> };
> };
> +
> +/* uarta communicates with the BT module */
> +&uarta {
> + uart-has-rtscts;
> + auto-flow-control;
> + status = "okay";
> + clock-frequency = <96000000>;
Would not the "clock-frequency" belong to the .dtsi node instead?
> + pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>;
> + pinctrl-names = "default";
> +
> + bluetooth: bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + max-speed = <3000000>;
> + shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>;
> + local-bd-address = [ 00 00 00 00 00 00 ];
> + };
> +};
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 3c0663dc6712..e972f94d6828 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -305,6 +305,17 @@ gio: gpio@7d508500 {
> brcm,gpio-direct;
> };
>
> + uarta: serial@7d50c000 {
> + compatible = "brcm,bcm7271-uart";
> + reg = <0x7d50c000 0x20>;
> + reg-names = "uart";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
> + skip-init;
Also an undocumented property upstream, what does it do? Is this to set
UPF_SKIP_TEST?
--
Florian
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712
2024-07-31 21:57 ` Florian Fainelli
@ 2024-08-01 6:45 ` Ivan T. Ivanov
0 siblings, 0 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-08-01 6:45 UTC (permalink / raw)
To: Florian Fainelli
Cc: linus.walleij, robh, krzk+dt, conor+dt, wahrenst, andrea.porta,
linux-gpio, devicetree, linux-arm-kernel
Hi,
On 07-31 14:57, Florian Fainelli wrote:
>
> On 7/30/24 23:28, Ivan T. Ivanov wrote:
> > From: Andrea della Porta <andrea.porta@suse.com>
> >
> > The BCM2712 SoC family can be found on Raspberry Pi 5.
> > Add minimal SoC and board (Rpi5 specific) dts file to be able to
> > boot from SD card and use console on debug UART.
> >
> > Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
>
> I have already applied this one:
>
> https://github.com/Broadcom/stblinux/commit/faa3381267d01a389b13038504079c85c0bc4392
>
> should I drop it and take this patch instead?
No. I added this patch here just for completeness.
It is written in cover letter.
Regards,
Ivan
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node
2024-07-31 22:11 ` Florian Fainelli
@ 2024-08-01 7:19 ` Ivan T. Ivanov
0 siblings, 0 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-08-01 7:19 UTC (permalink / raw)
To: Florian Fainelli
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
wahrenst, andrea.porta, linux-gpio, devicetree, linux-arm-kernel
On 07-31 15:11, Florian Fainelli wrote:
> > +
> > + gio: gpio@7d508500 {
> > + compatible = "brcm,brcmstb-gpio";
> > + reg = <0x7d508500 0x40>;
> > + interrupt-parent = <&main_irq>;
> > + interrupts = <0>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + brcm,gpio-bank-widths = <32 22>;
> > + brcm,gpio-direct;
>
> Undocumented and unsupported property upstream, what does it do? Other than
> that, LGTM.
Doh. Something used for banging GPIO's from user-space via "/dev/gpiomem".
I will remove it in next patch version.
Thanks,
Ivan
[1]
"...
gpio: mmio: Add DIRECT mode for shared access
The generic MMIO GPIO library uses shadow registers for efficiency,
but this breaks attempts by raspi-gpio to change other GPIOs in the
same bank. Add a DIRECT mode that makes fewer assumptions about the
existing register contents, but note that genuinely simultaneous
accesses are likely to lose updates.
... "
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA controller node.
2024-07-31 22:13 ` Florian Fainelli
@ 2024-08-01 7:50 ` Ivan T. Ivanov
0 siblings, 0 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-08-01 7:50 UTC (permalink / raw)
To: Florian Fainelli
Cc: linus.walleij, robh, krzk+dt, conor+dt, wahrenst, andrea.porta,
linux-gpio, devicetree, linux-arm-kernel
Hi,
On 07-31 15:13, Florian Fainelli wrote:
> > +
> > +/* uarta communicates with the BT module */
> > +&uarta {
> > + uart-has-rtscts;
> > + auto-flow-control;
> > + status = "okay";
> > + clock-frequency = <96000000>;
>
> Would not the "clock-frequency" belong to the .dtsi node instead?
>
Perhaps.
> > + pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>;
> > + pinctrl-names = "default";
> > +
> > + bluetooth: bluetooth {
> > + compatible = "brcm,bcm43438-bt";
> > + max-speed = <3000000>;
> > + shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>;
> > + local-bd-address = [ 00 00 00 00 00 00 ];
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> > index 3c0663dc6712..e972f94d6828 100644
> > --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> > +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> > @@ -305,6 +305,17 @@ gio: gpio@7d508500 {
> > brcm,gpio-direct;
> > };
> > + uarta: serial@7d50c000 {
> > + compatible = "brcm,bcm7271-uart";
> > + reg = <0x7d50c000 0x20>;
> > + reg-names = "uart";
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
> > + skip-init;
>
> Also an undocumented property upstream, what does it do? Is this to set
> UPF_SKIP_TEST?
It is U-Boot thing [1]. I suppose I can drop it.
Thanks,
Ivan
[1] ... "
serial: pl01x: Add support for devices with the rate pre-configured.
For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt. Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.
..."
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-07-31 6:28 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Ivan T. Ivanov
@ 2024-08-01 8:17 ` Krzysztof Kozlowski
2024-08-01 8:38 ` Ivan T. Ivanov
2024-08-02 18:09 ` Stefan Wahren
1 sibling, 1 reply; 34+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-01 8:17 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, andrea.porta, linux-gpio,
devicetree, linux-arm-kernel
On 31/07/2024 08:28, Ivan T. Ivanov wrote:
> It looks like they are few revisions of this chip which varies
> by number of pins. Perhaps not all of them are available on the
> market. Perhaps some of them where early engineering samples,
> I don't know. I decided to keep all of them just in case.
>
> Cc: Andrea della Porta <andrea.porta@suse.com>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../pinctrl/brcm,brcmstb-pinctrl.yaml | 73 +++++++++++++++++++
> 1 file changed, 73 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> new file mode 100644
> index 000000000000..c5afdb49d784
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
bcm2712 is Rpi, so not really STB. The name is confusing. Please use
compatible as filename, so:
brcm,bcm2712-pinctrl.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom STB family pin controller
> +
> +maintainers:
> + - Ivan T. Ivanov <iivanov@suse.de>
> +
> +description:
> + Broadcom's STB family memory-mapped pin controller.
> +
> +properties:
> + compatible:
> + enum:
> + - brcm,bcm2712-pinctrl
> + - brcm,bcm2712-aon-pinctrl
> + - brcm,bcm2712c0-pinctrl
> + - brcm,bcm2712c0-aon-pinctrl
> + - brcm,bcm2712d0-pinctrl
> + - brcm,bcm2712d0-aon-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - $ref: pinctrl.yaml#
"allOf:" block goes after "required:".
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties:
> + anyOf:
> + - type: object
> + allOf:
> + - $ref: pincfg-node.yaml#
> + - $ref: pinmux-node.yaml#
> +
> + properties:
> + function:
> + enum:
> + [
Unnecessary new line
> + gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8,
> + aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm,
> + arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2,
> + bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii,
> + ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c,
> + hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out,
> + ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0,
> + sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e,
> + sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0,
> + te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0,
> + vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1,
> + vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3,
> + vc_uart4,
> + ]
> +
> + pins:
> + items:
> + pattern: "^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$"
> +
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + additionalProperties: false
> +
> + - type: object
> + additionalProperties:
> + $ref: "#/additionalProperties/anyOf/0"
I suggest going with patternProperties, fixed suffix for node names and
$defs. See for example:
Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml
Missing example. I don't see this being part of other complete device,
so example is a requirement.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-08-01 8:17 ` Krzysztof Kozlowski
@ 2024-08-01 8:38 ` Ivan T. Ivanov
2024-08-01 14:19 ` Krzysztof Kozlowski
0 siblings, 1 reply; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-08-01 8:38 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
wahrenst, andrea.porta, linux-gpio, devicetree, linux-arm-kernel
Hi,
On 08-01 10:17, Krzysztof Kozlowski wrote:
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
>
> bcm2712 is Rpi, so not really STB. The name is confusing. Please use
> compatible as filename, so:
> brcm,bcm2712-pinctrl.yaml
According Florian it is:
https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
>
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Broadcom STB family pin controller
> > +
> > +maintainers:
> > + - Ivan T. Ivanov <iivanov@suse.de>
> > +
> > +description:
> > + Broadcom's STB family memory-mapped pin controller.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - brcm,bcm2712-pinctrl
> > + - brcm,bcm2712-aon-pinctrl
> > + - brcm,bcm2712c0-pinctrl
> > + - brcm,bcm2712c0-aon-pinctrl
> > + - brcm,bcm2712d0-pinctrl
> > + - brcm,bcm2712d0-aon-pinctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +allOf:
> > + - $ref: pinctrl.yaml#
>
> "allOf:" block goes after "required:".
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties:
> > + anyOf:
> > + - type: object
> > + allOf:
> > + - $ref: pincfg-node.yaml#
> > + - $ref: pinmux-node.yaml#
> > +
> > + properties:
> > + function:
> > + enum:
> > + [
>
> Unnecessary new line
>
> > + gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8,
> > + aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm,
> > + arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2,
> > + bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii,
> > + ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c,
> > + hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out,
> > + ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0,
> > + sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e,
> > + sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0,
> > + te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0,
> > + vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1,
> > + vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3,
> > + vc_uart4,
> > + ]
> > +
> > + pins:
> > + items:
> > + pattern: "^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$"
> > +
> > + bias-disable: true
> > + bias-pull-down: true
> > + bias-pull-up: true
> > + additionalProperties: false
> > +
> > + - type: object
> > + additionalProperties:
> > + $ref: "#/additionalProperties/anyOf/0"
>
> I suggest going with patternProperties, fixed suffix for node names and
> $defs. See for example:
> Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml
>
> Missing example. I don't see this being part of other complete device,
> so example is a requirement.
>
Thanks, I will update and resend.
Regards,
Ivan
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-08-01 8:38 ` Ivan T. Ivanov
@ 2024-08-01 14:19 ` Krzysztof Kozlowski
2024-08-05 9:27 ` Ivan T. Ivanov
0 siblings, 1 reply; 34+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-01 14:19 UTC (permalink / raw)
To: Ivan T. Ivanov
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
wahrenst, andrea.porta, linux-gpio, devicetree, linux-arm-kernel
On 01/08/2024 10:38, Ivan T. Ivanov wrote:
> Hi,
>
> On 08-01 10:17, Krzysztof Kozlowski wrote:
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
>>
>> bcm2712 is Rpi, so not really STB. The name is confusing. Please use
>> compatible as filename, so:
>> brcm,bcm2712-pinctrl.yaml
>
> According Florian it is:
>
> https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
OK, title can be like this, no problem, although then please expand what
"STB" means.
Bindings still are supposed to use compatible as filename.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver
2024-07-31 6:28 ` [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver Ivan T. Ivanov
@ 2024-08-02 10:22 ` Phil Elwell
2024-08-02 18:36 ` Stefan Wahren
2024-08-05 9:13 ` Stefan Wahren
2 siblings, 0 replies; 34+ messages in thread
From: Phil Elwell @ 2024-08-02 10:22 UTC (permalink / raw)
To: Ivan T. Ivanov
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
wahrenst, andrea.porta, linux-gpio, devicetree, linux-arm-kernel,
Jonathan Bell
On Wed, 31 Jul 2024 at 07:26, Ivan T. Ivanov <iivanov@suse.de> wrote:
>
> This driver provide pin muxing and configuration functionality
> for BCM2712 SoC used by RPi5. According to [1] this chips is
> incarnation of chip used in Broadcom STB product line.
>
> [1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
>
> Cc: Jonathan Bell <jonathan@raspberrypi.com>
> Cc: Phil Elwell <phil@raspberrypi.com>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> drivers/pinctrl/bcm/Kconfig | 13 +
> drivers/pinctrl/bcm/Makefile | 1 +
> drivers/pinctrl/bcm/pinctrl-brcmstb.c | 1217 +++++++++++++++++++++++++
> 3 files changed, 1231 insertions(+)
> create mode 100644 drivers/pinctrl/bcm/pinctrl-brcmstb.c
>
> diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
> index 35b51ce4298e..2e1b8d444f58 100644
> --- a/drivers/pinctrl/bcm/Kconfig
> +++ b/drivers/pinctrl/bcm/Kconfig
> @@ -3,6 +3,19 @@
> # Broadcom pinctrl drivers
> #
>
> +config PINCTRL_BRCMSTB
> + tristate "Broadcom STB product line pin controller driver"
> + depends on OF && (ARCH_BRCMSTB || COMPILE_TEST)
> + select PINMUX
> + select PINCONF
> + select GENERIC_PINCONF
> + help
> + This driver provide pin muxing and configuration functionality
> + for Broadcom STB product line chipsets. BCM2712 SoC is one of these
> + chipsets.
> +
> + If M is selected the module will be called pinctrl-brcmstb.
> +
> config PINCTRL_BCM281XX
> bool "Broadcom BCM281xx pinctrl driver"
> depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
> diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile
> index 82b868ec1471..5f790c14cc4c 100644
> --- a/drivers/pinctrl/bcm/Makefile
> +++ b/drivers/pinctrl/bcm/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
> obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
> obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
> obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o
> +obj-$(CONFIG_PINCTRL_BRCMSTB) += pinctrl-brcmstb.o
> obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
> obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
> obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
> diff --git a/drivers/pinctrl/bcm/pinctrl-brcmstb.c b/drivers/pinctrl/bcm/pinctrl-brcmstb.c
> new file mode 100644
> index 000000000000..143c8c2e1d6d
> --- /dev/null
> +++ b/drivers/pinctrl/bcm/pinctrl-brcmstb.c
> @@ -0,0 +1,1217 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Driver for Broadcom brcmstb GPIO units (pinctrl only)
> + *
> + * Copyright (C) 2021-3 Raspberry Pi Ltd.
> + * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
> + *
> + * Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
> + * pinctrl-nomadik.c, please see original file for copyright information
> + * pinctrl-tegra.c, please see original file for copyright information
> + */
> +
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/pinctrl/pinconf-generic.h>
> +#include <linux/platform_device.h>
> +#include <linux/seq_file.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define BRCMSTB_PULL_NONE 0
> +#define BRCMSTB_PULL_DOWN 1
> +#define BRCMSTB_PULL_UP 2
> +#define BRCMSTB_PULL_MASK 0x3
> +
> +#define BRCMSTB_FSEL_COUNT 9
> +#define BRCMSTB_FSEL_MASK 0xf
> +
> +#define FUNC(f) \
> + [func_##f] = #f
> +
> +#define PIN(i, f1, f2, f3, f4, f5, f6, f7, f8) \
> + [i] = { \
> + .funcs = { \
> + func_##f1, \
> + func_##f2, \
> + func_##f3, \
> + func_##f4, \
> + func_##f5, \
> + func_##f6, \
> + func_##f7, \
> + func_##f8, \
> + }, \
> + }
> +
> +#define MUX_BIT_VALID 0x8000
> +#define REG_BIT_INVALID 0xffff
> +
> +#define BIT_TO_REG(b) (((b) >> 5) << 2)
> +#define BIT_TO_SHIFT(b) ((b) & 0x1f)
> +
> +#define MUX_BIT(mr, mb) (MUX_BIT_VALID + ((mr) * 4) * 8 + (mb) * 4)
> +#define GPIO_REGS(n, mr, mb, pr, pb) \
> + [n] = { MUX_BIT(mr, mb), ((pr) * 4) * 8 + (pb) * 2 }
> +
> +#define EMMC_REGS(n, pr, pb) \
> + [n] = { 0, ((pr) * 4) * 8 + (pb) * 2 }
> +
> +#define AGPIO_REGS(n, mr, mb, pr, pb) \
> + [n] = { MUX_BIT(mr, mb), ((pr) * 4) * 8 + (pb) * 2 }
> +
> +#define SGPIO_REGS(n, mr, mb) \
> + [(n) + 32] = { MUX_BIT(mr, mb), REG_BIT_INVALID }
> +
> +#define GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
> +#define AGPIO_PIN(a) PINCTRL_PIN(a, "aon_gpio" #a)
> +#define SGPIO_PIN(a) PINCTRL_PIN((a) + 32, "aon_sgpio" #a)
> +
> +struct pin_regs {
> + u16 mux_bit;
> + u16 pad_bit;
> +};
> +
> +struct brcmstb_pin_funcs {
> + u8 funcs[BRCMSTB_FSEL_COUNT - 1];
> +};
> +
> +struct brcmstb_pinctrl {
> + struct device *dev;
> + void __iomem *base;
> + struct pinctrl_dev *pctl_dev;
> + struct pinctrl_desc pctl_desc;
> + const struct pin_regs *pin_regs;
> + const struct brcmstb_pin_funcs *pin_funcs;
> + const char *const *gpio_groups;
> + struct pinctrl_gpio_range gpio_range;
> + /* Protect FSEL registers */
> + spinlock_t lock;
> +};
> +
> +struct brcmstb_pdata {
> + const struct pinctrl_desc *pctl_desc;
> + const struct pinctrl_gpio_range *gpio_range;
> + const struct pin_regs *pin_regs;
> + const struct brcmstb_pin_funcs *pin_funcs;
> +};
> +
> +enum brcmstb_funcs {
> + func_gpio,
> + func_alt1,
> + func_alt2,
> + func_alt3,
> + func_alt4,
> + func_alt5,
> + func_alt6,
> + func_alt7,
> + func_alt8,
> + func_aon_cpu_standbyb,
> + func_aon_fp_4sec_resetb,
> + func_aon_gpclk,
> + func_aon_pwm,
> + func_arm_jtag,
> + func_aud_fs_clk0,
> + func_avs_pmu_bsc,
> + func_bsc_m0,
> + func_bsc_m1,
> + func_bsc_m2,
> + func_bsc_m3,
> + func_clk_observe,
> + func_ctl_hdmi_5v,
> + func_enet0,
> + func_enet0_mii,
> + func_enet0_rgmii,
> + func_ext_sc_clk,
> + func_fl0,
> + func_fl1,
> + func_gpclk0,
> + func_gpclk1,
> + func_gpclk2,
> + func_hdmi_tx0_auto_i2c,
> + func_hdmi_tx0_bsc,
> + func_hdmi_tx1_auto_i2c,
> + func_hdmi_tx1_bsc,
> + func_i2s_in,
> + func_i2s_out,
> + func_ir_in,
> + func_mtsif,
> + func_mtsif_alt,
> + func_mtsif_alt1,
> + func_pdm,
> + func_pkt,
> + func_pm_led_out,
> + func_sc0,
> + func_sd0,
> + func_sd2,
> + func_sd_card_a,
> + func_sd_card_b,
> + func_sd_card_c,
> + func_sd_card_d,
> + func_sd_card_e,
> + func_sd_card_f,
> + func_sd_card_g,
> + func_spdif_out,
> + func_spi_m,
> + func_spi_s,
> + func_sr_edm_sense,
> + func_te0,
> + func_te1,
> + func_tsio,
> + func_uart0,
> + func_uart1,
> + func_uart2,
> + func_usb_pwr,
> + func_usb_vbus,
> + func_uui,
> + func_vc_i2c0,
> + func_vc_i2c3,
> + func_vc_i2c4,
> + func_vc_i2c5,
> + func_vc_i2csl,
> + func_vc_pcm,
> + func_vc_pwm0,
> + func_vc_pwm1,
> + func_vc_spi0,
> + func_vc_spi3,
> + func_vc_spi4,
> + func_vc_spi5,
> + func_vc_uart0,
> + func_vc_uart2,
> + func_vc_uart3,
> + func_vc_uart4,
> + func__,
> + func_count = func__
> +};
> +
> +static const struct pin_regs bcm2712_c0_gpio_pin_regs[] = {
> + GPIO_REGS(0, 0, 0, 7, 7),
> + GPIO_REGS(1, 0, 1, 7, 8),
> + GPIO_REGS(2, 0, 2, 7, 9),
> + GPIO_REGS(3, 0, 3, 7, 10),
> + GPIO_REGS(4, 0, 4, 7, 11),
> + GPIO_REGS(5, 0, 5, 7, 12),
> + GPIO_REGS(6, 0, 6, 7, 13),
> + GPIO_REGS(7, 0, 7, 7, 14),
> + GPIO_REGS(8, 1, 0, 8, 0),
> + GPIO_REGS(9, 1, 1, 8, 1),
> + GPIO_REGS(10, 1, 2, 8, 2),
> + GPIO_REGS(11, 1, 3, 8, 3),
> + GPIO_REGS(12, 1, 4, 8, 4),
> + GPIO_REGS(13, 1, 5, 8, 5),
> + GPIO_REGS(14, 1, 6, 8, 6),
> + GPIO_REGS(15, 1, 7, 8, 7),
> + GPIO_REGS(16, 2, 0, 8, 8),
> + GPIO_REGS(17, 2, 1, 8, 9),
> + GPIO_REGS(18, 2, 2, 8, 10),
> + GPIO_REGS(19, 2, 3, 8, 11),
> + GPIO_REGS(20, 2, 4, 8, 12),
> + GPIO_REGS(21, 2, 5, 8, 13),
> + GPIO_REGS(22, 2, 6, 8, 14),
> + GPIO_REGS(23, 2, 7, 9, 0),
> + GPIO_REGS(24, 3, 0, 9, 1),
> + GPIO_REGS(25, 3, 1, 9, 2),
> + GPIO_REGS(26, 3, 2, 9, 3),
> + GPIO_REGS(27, 3, 3, 9, 4),
> + GPIO_REGS(28, 3, 4, 9, 5),
> + GPIO_REGS(29, 3, 5, 9, 6),
> + GPIO_REGS(30, 3, 6, 9, 7),
> + GPIO_REGS(31, 3, 7, 9, 8),
> + GPIO_REGS(32, 4, 0, 9, 9),
> + GPIO_REGS(33, 4, 1, 9, 10),
> + GPIO_REGS(34, 4, 2, 9, 11),
> + GPIO_REGS(35, 4, 3, 9, 12),
> + GPIO_REGS(36, 4, 4, 9, 13),
> + GPIO_REGS(37, 4, 5, 9, 14),
> + GPIO_REGS(38, 4, 6, 10, 0),
> + GPIO_REGS(39, 4, 7, 10, 1),
> + GPIO_REGS(40, 5, 0, 10, 2),
> + GPIO_REGS(41, 5, 1, 10, 3),
> + GPIO_REGS(42, 5, 2, 10, 4),
> + GPIO_REGS(43, 5, 3, 10, 5),
> + GPIO_REGS(44, 5, 4, 10, 6),
> + GPIO_REGS(45, 5, 5, 10, 7),
> + GPIO_REGS(46, 5, 6, 10, 8),
> + GPIO_REGS(47, 5, 7, 10, 9),
> + GPIO_REGS(48, 6, 0, 10, 10),
> + GPIO_REGS(49, 6, 1, 10, 11),
> + GPIO_REGS(50, 6, 2, 10, 12),
> + GPIO_REGS(51, 6, 3, 10, 13),
> + GPIO_REGS(52, 6, 4, 10, 14),
> + GPIO_REGS(53, 6, 5, 11, 0),
> + EMMC_REGS(54, 11, 1), /* EMMC_CMD */
> + EMMC_REGS(55, 11, 2), /* EMMC_DS */
> + EMMC_REGS(56, 11, 3), /* EMMC_CLK */
> + EMMC_REGS(57, 11, 4), /* EMMC_DAT0 */
> + EMMC_REGS(58, 11, 5), /* EMMC_DAT1 */
> + EMMC_REGS(59, 11, 6), /* EMMC_DAT2 */
> + EMMC_REGS(60, 11, 7), /* EMMC_DAT3 */
> + EMMC_REGS(61, 11, 8), /* EMMC_DAT4 */
> + EMMC_REGS(62, 11, 9), /* EMMC_DAT5 */
> + EMMC_REGS(63, 11, 10), /* EMMC_DAT6 */
> + EMMC_REGS(64, 11, 11), /* EMMC_DAT7 */
> +};
> +
> +static struct pin_regs bcm2712_c0_aon_gpio_pin_regs[] = {
> + AGPIO_REGS(0, 3, 0, 6, 10),
> + AGPIO_REGS(1, 3, 1, 6, 11),
> + AGPIO_REGS(2, 3, 2, 6, 12),
> + AGPIO_REGS(3, 3, 3, 6, 13),
> + AGPIO_REGS(4, 3, 4, 6, 14),
> + AGPIO_REGS(5, 3, 5, 7, 0),
> + AGPIO_REGS(6, 3, 6, 7, 1),
> + AGPIO_REGS(7, 3, 7, 7, 2),
> + AGPIO_REGS(8, 4, 0, 7, 3),
> + AGPIO_REGS(9, 4, 1, 7, 4),
> + AGPIO_REGS(10, 4, 2, 7, 5),
> + AGPIO_REGS(11, 4, 3, 7, 6),
> + AGPIO_REGS(12, 4, 4, 7, 7),
> + AGPIO_REGS(13, 4, 5, 7, 8),
> + AGPIO_REGS(14, 4, 6, 7, 9),
> + AGPIO_REGS(15, 4, 7, 7, 10),
> + AGPIO_REGS(16, 5, 0, 7, 11),
> + SGPIO_REGS(0, 0, 0),
> + SGPIO_REGS(1, 0, 1),
> + SGPIO_REGS(2, 0, 2),
> + SGPIO_REGS(3, 0, 3),
> + SGPIO_REGS(4, 1, 0),
> + SGPIO_REGS(5, 2, 0),
> +};
> +
> +static const struct pinctrl_pin_desc bcm2712_c0_gpio_pins[] = {
> + GPIO_PIN(0),
> + GPIO_PIN(1),
> + GPIO_PIN(2),
> + GPIO_PIN(3),
> + GPIO_PIN(4),
> + GPIO_PIN(5),
> + GPIO_PIN(6),
> + GPIO_PIN(7),
> + GPIO_PIN(8),
> + GPIO_PIN(9),
> + GPIO_PIN(10),
> + GPIO_PIN(11),
> + GPIO_PIN(12),
> + GPIO_PIN(13),
> + GPIO_PIN(14),
> + GPIO_PIN(15),
> + GPIO_PIN(16),
> + GPIO_PIN(17),
> + GPIO_PIN(18),
> + GPIO_PIN(19),
> + GPIO_PIN(20),
> + GPIO_PIN(21),
> + GPIO_PIN(22),
> + GPIO_PIN(23),
> + GPIO_PIN(24),
> + GPIO_PIN(25),
> + GPIO_PIN(26),
> + GPIO_PIN(27),
> + GPIO_PIN(28),
> + GPIO_PIN(29),
> + GPIO_PIN(30),
> + GPIO_PIN(31),
> + GPIO_PIN(32),
> + GPIO_PIN(33),
> + GPIO_PIN(34),
> + GPIO_PIN(35),
> + GPIO_PIN(36),
> + GPIO_PIN(37),
> + GPIO_PIN(38),
> + GPIO_PIN(39),
> + GPIO_PIN(40),
> + GPIO_PIN(41),
> + GPIO_PIN(42),
> + GPIO_PIN(43),
> + GPIO_PIN(44),
> + GPIO_PIN(45),
> + GPIO_PIN(46),
> + GPIO_PIN(47),
> + GPIO_PIN(48),
> + GPIO_PIN(49),
> + GPIO_PIN(50),
> + GPIO_PIN(51),
> + GPIO_PIN(52),
> + GPIO_PIN(53),
> + PINCTRL_PIN(54, "emmc_cmd"),
> + PINCTRL_PIN(55, "emmc_ds"),
> + PINCTRL_PIN(56, "emmc_clk"),
> + PINCTRL_PIN(57, "emmc_dat0"),
> + PINCTRL_PIN(58, "emmc_dat1"),
> + PINCTRL_PIN(59, "emmc_dat2"),
> + PINCTRL_PIN(60, "emmc_dat3"),
> + PINCTRL_PIN(61, "emmc_dat4"),
> + PINCTRL_PIN(62, "emmc_dat5"),
> + PINCTRL_PIN(63, "emmc_dat6"),
> + PINCTRL_PIN(64, "emmc_dat7"),
> +};
> +
> +static struct pinctrl_pin_desc bcm2712_c0_aon_gpio_pins[] = {
> + AGPIO_PIN(0), AGPIO_PIN(1), AGPIO_PIN(2), AGPIO_PIN(3),
> + AGPIO_PIN(4), AGPIO_PIN(5), AGPIO_PIN(6), AGPIO_PIN(7),
> + AGPIO_PIN(8), AGPIO_PIN(9), AGPIO_PIN(10), AGPIO_PIN(11),
> + AGPIO_PIN(12), AGPIO_PIN(13), AGPIO_PIN(14), AGPIO_PIN(15),
> + AGPIO_PIN(16), SGPIO_PIN(0), SGPIO_PIN(1), SGPIO_PIN(2),
> + SGPIO_PIN(3), SGPIO_PIN(4), SGPIO_PIN(5),
> +};
> +
> +static const struct pin_regs bcm2712_d0_gpio_pin_regs[] = {
> + GPIO_REGS(1, 0, 0, 4, 5),
> + GPIO_REGS(2, 0, 1, 4, 6),
> + GPIO_REGS(3, 0, 2, 4, 7),
> + GPIO_REGS(4, 0, 3, 4, 8),
> + GPIO_REGS(10, 0, 4, 4, 9),
> + GPIO_REGS(11, 0, 5, 4, 10),
> + GPIO_REGS(12, 0, 6, 4, 11),
> + GPIO_REGS(13, 0, 7, 4, 12),
> + GPIO_REGS(14, 1, 0, 4, 13),
> + GPIO_REGS(15, 1, 1, 4, 14),
> + GPIO_REGS(18, 1, 2, 5, 0),
> + GPIO_REGS(19, 1, 3, 5, 1),
> + GPIO_REGS(20, 1, 4, 5, 2),
> + GPIO_REGS(21, 1, 5, 5, 3),
> + GPIO_REGS(22, 1, 6, 5, 4),
> + GPIO_REGS(23, 1, 7, 5, 5),
> + GPIO_REGS(24, 2, 0, 5, 6),
> + GPIO_REGS(25, 2, 1, 5, 7),
> + GPIO_REGS(26, 2, 2, 5, 8),
> + GPIO_REGS(27, 2, 3, 5, 9),
> + GPIO_REGS(28, 2, 4, 5, 10),
> + GPIO_REGS(29, 2, 5, 5, 11),
> + GPIO_REGS(30, 2, 6, 5, 12),
> + GPIO_REGS(31, 2, 7, 5, 13),
> + GPIO_REGS(32, 3, 0, 5, 14),
> + GPIO_REGS(33, 3, 1, 6, 0),
> + GPIO_REGS(34, 3, 2, 6, 1),
> + GPIO_REGS(35, 3, 3, 6, 2),
> + EMMC_REGS(36, 6, 3), /* EMMC_CMD */
> + EMMC_REGS(37, 6, 4), /* EMMC_DS */
> + EMMC_REGS(38, 6, 5), /* EMMC_CLK */
> + EMMC_REGS(39, 6, 6), /* EMMC_DAT0 */
> + EMMC_REGS(40, 6, 7), /* EMMC_DAT1 */
> + EMMC_REGS(41, 6, 8), /* EMMC_DAT2 */
> + EMMC_REGS(42, 6, 9), /* EMMC_DAT3 */
> + EMMC_REGS(43, 6, 10), /* EMMC_DAT4 */
> + EMMC_REGS(44, 6, 11), /* EMMC_DAT5 */
> + EMMC_REGS(45, 6, 12), /* EMMC_DAT6 */
> + EMMC_REGS(46, 6, 13), /* EMMC_DAT7 */
> +};
> +
> +static struct pin_regs bcm2712_d0_aon_gpio_pin_regs[] = {
> + AGPIO_REGS(0, 3, 0, 5, 9),
> + AGPIO_REGS(1, 3, 1, 5, 10),
> + AGPIO_REGS(2, 3, 2, 5, 11),
> + AGPIO_REGS(3, 3, 3, 5, 12),
> + AGPIO_REGS(4, 3, 4, 5, 13),
> + AGPIO_REGS(5, 3, 5, 5, 14),
> + AGPIO_REGS(6, 3, 6, 6, 0),
> + AGPIO_REGS(8, 3, 7, 6, 1),
> + AGPIO_REGS(9, 4, 0, 6, 2),
> + AGPIO_REGS(12, 4, 1, 6, 3),
> + AGPIO_REGS(13, 4, 2, 6, 4),
> + AGPIO_REGS(14, 4, 3, 6, 5),
> + SGPIO_REGS(0, 0, 0),
> + SGPIO_REGS(1, 0, 1),
> + SGPIO_REGS(2, 0, 2),
> + SGPIO_REGS(3, 0, 3),
> + SGPIO_REGS(4, 1, 0),
> + SGPIO_REGS(5, 2, 0),
> +};
> +
> +static const struct pinctrl_pin_desc bcm2712_d0_gpio_pins[] = {
> + GPIO_PIN(1),
> + GPIO_PIN(2),
> + GPIO_PIN(3),
> + GPIO_PIN(4),
> + GPIO_PIN(10),
> + GPIO_PIN(11),
> + GPIO_PIN(12),
> + GPIO_PIN(13),
> + GPIO_PIN(14),
> + GPIO_PIN(15),
> + GPIO_PIN(18),
> + GPIO_PIN(19),
> + GPIO_PIN(20),
> + GPIO_PIN(21),
> + GPIO_PIN(22),
> + GPIO_PIN(23),
> + GPIO_PIN(24),
> + GPIO_PIN(25),
> + GPIO_PIN(26),
> + GPIO_PIN(27),
> + GPIO_PIN(28),
> + GPIO_PIN(29),
> + GPIO_PIN(30),
> + GPIO_PIN(31),
> + GPIO_PIN(32),
> + GPIO_PIN(33),
> + GPIO_PIN(34),
> + GPIO_PIN(35),
> + PINCTRL_PIN(36, "emmc_cmd"),
> + PINCTRL_PIN(37, "emmc_ds"),
> + PINCTRL_PIN(38, "emmc_clk"),
> + PINCTRL_PIN(39, "emmc_dat0"),
> + PINCTRL_PIN(40, "emmc_dat1"),
> + PINCTRL_PIN(41, "emmc_dat2"),
> + PINCTRL_PIN(42, "emmc_dat3"),
> + PINCTRL_PIN(43, "emmc_dat4"),
> + PINCTRL_PIN(44, "emmc_dat5"),
> + PINCTRL_PIN(45, "emmc_dat6"),
> + PINCTRL_PIN(46, "emmc_dat7"),
> +};
> +
> +static struct pinctrl_pin_desc bcm2712_d0_aon_gpio_pins[] = {
> + AGPIO_PIN(0), AGPIO_PIN(1), AGPIO_PIN(2), AGPIO_PIN(3), AGPIO_PIN(4),
> + AGPIO_PIN(5), AGPIO_PIN(6), AGPIO_PIN(8), AGPIO_PIN(9), AGPIO_PIN(12),
> + AGPIO_PIN(13), AGPIO_PIN(14), SGPIO_PIN(0), SGPIO_PIN(1), SGPIO_PIN(2),
> + SGPIO_PIN(3), SGPIO_PIN(4), SGPIO_PIN(5),
> +};
> +
> +static const char * const brcmstb_func_names[] = {
> + FUNC(gpio),
> + FUNC(alt1),
> + FUNC(alt2),
> + FUNC(alt3),
> + FUNC(alt4),
> + FUNC(alt5),
> + FUNC(alt6),
> + FUNC(alt7),
> + FUNC(alt8),
> + FUNC(aon_cpu_standbyb),
> + FUNC(aon_fp_4sec_resetb),
> + FUNC(aon_gpclk),
> + FUNC(aon_pwm),
> + FUNC(arm_jtag),
> + FUNC(aud_fs_clk0),
> + FUNC(avs_pmu_bsc),
> + FUNC(bsc_m0),
> + FUNC(bsc_m1),
> + FUNC(bsc_m2),
> + FUNC(bsc_m3),
> + FUNC(clk_observe),
> + FUNC(ctl_hdmi_5v),
> + FUNC(enet0),
> + FUNC(enet0_mii),
> + FUNC(enet0_rgmii),
> + FUNC(ext_sc_clk),
> + FUNC(fl0),
> + FUNC(fl1),
> + FUNC(gpclk0),
> + FUNC(gpclk1),
> + FUNC(gpclk2),
> + FUNC(hdmi_tx0_auto_i2c),
> + FUNC(hdmi_tx0_bsc),
> + FUNC(hdmi_tx1_auto_i2c),
> + FUNC(hdmi_tx1_bsc),
> + FUNC(i2s_in),
> + FUNC(i2s_out),
> + FUNC(ir_in),
> + FUNC(mtsif),
> + FUNC(mtsif_alt),
> + FUNC(mtsif_alt1),
> + FUNC(pdm),
> + FUNC(pkt),
> + FUNC(pm_led_out),
> + FUNC(sc0),
> + FUNC(sd0),
> + FUNC(sd2),
> + FUNC(sd_card_a),
> + FUNC(sd_card_b),
> + FUNC(sd_card_c),
> + FUNC(sd_card_d),
> + FUNC(sd_card_e),
> + FUNC(sd_card_f),
> + FUNC(sd_card_g),
> + FUNC(spdif_out),
> + FUNC(spi_m),
> + FUNC(spi_s),
> + FUNC(sr_edm_sense),
> + FUNC(te0),
> + FUNC(te1),
> + FUNC(tsio),
> + FUNC(uart0),
> + FUNC(uart1),
> + FUNC(uart2),
> + FUNC(usb_pwr),
> + FUNC(usb_vbus),
> + FUNC(uui),
> + FUNC(vc_i2c0),
> + FUNC(vc_i2c3),
> + FUNC(vc_i2c4),
> + FUNC(vc_i2c5),
> + FUNC(vc_i2csl),
> + FUNC(vc_pcm),
> + FUNC(vc_pwm0),
> + FUNC(vc_pwm1),
> + FUNC(vc_spi0),
> + FUNC(vc_spi3),
> + FUNC(vc_spi4),
> + FUNC(vc_spi5),
> + FUNC(vc_uart0),
> + FUNC(vc_uart2),
> + FUNC(vc_uart3),
> + FUNC(vc_uart4),
> +};
> +
> +static const struct brcmstb_pin_funcs bcm2712_c0_aon_gpio_pin_funcs[] = {
> + PIN(0, ir_in, vc_spi0, vc_uart3, vc_i2c3, te0, vc_i2c0, _, _),
> + PIN(1, vc_pwm0, vc_spi0, vc_uart3, vc_i2c3, te1, aon_pwm, vc_i2c0, vc_pwm1),
> + PIN(2, vc_pwm0, vc_spi0, vc_uart3, ctl_hdmi_5v, fl0, aon_pwm, ir_in, vc_pwm1),
> + PIN(3, ir_in, vc_spi0, vc_uart3, aon_fp_4sec_resetb, fl1, sd_card_g, aon_gpclk, _),
> + PIN(4, gpclk0, vc_spi0, vc_i2csl, aon_gpclk, pm_led_out, aon_pwm, sd_card_g, vc_pwm0),
> + PIN(5, gpclk1, ir_in, vc_i2csl, clk_observe, aon_pwm, sd_card_g, vc_pwm0, _),
> + PIN(6, uart1, vc_uart4, gpclk2, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
> + PIN(7, uart1, vc_uart4, gpclk0, aon_pwm, vc_uart0, vc_spi3, _, _),
> + PIN(8, uart1, vc_uart4, vc_i2csl, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
> + PIN(9, uart1, vc_uart4, vc_i2csl, aon_pwm, vc_uart0, vc_spi3, _, _),
> + PIN(10, tsio, ctl_hdmi_5v, sc0, spdif_out, vc_spi5, usb_pwr, aon_gpclk, sd_card_f),
> + PIN(11, tsio, uart0, sc0, aud_fs_clk0, vc_spi5, usb_vbus, vc_uart2, sd_card_f),
> + PIN(12, tsio, uart0, vc_uart0, tsio, vc_spi5, usb_pwr, vc_uart2, sd_card_f),
> + PIN(13, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
> + PIN(14, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
> + PIN(15, ir_in, aon_fp_4sec_resetb, vc_uart0, pm_led_out, ctl_hdmi_5v, aon_pwm, aon_gpclk, _),
> + PIN(16, aon_cpu_standbyb, gpclk0, pm_led_out, ctl_hdmi_5v, vc_pwm0, usb_pwr, aud_fs_clk0, _),
> +};
> +
> +static const struct brcmstb_pin_funcs bcm2712_c0_aon_sgpio_pin_funcs[] = {
> + PIN(0, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
> + PIN(1, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
> + PIN(2, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c4, ctl_hdmi_5v, _, _, _),
> + PIN(3, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c4, _, _, _, _),
> + PIN(4, avs_pmu_bsc, bsc_m2, vc_i2c5, ctl_hdmi_5v, _, _, _, _),
> + PIN(5, avs_pmu_bsc, bsc_m2, vc_i2c5, _, _, _, _, _),
> +};
> +
> +static const struct brcmstb_pin_funcs bcm2712_c0_gpio_pin_funcs[] = {
> + PIN(0, bsc_m3, vc_i2c0, gpclk0, enet0, vc_pwm1, vc_spi0, ir_in, _),
> + PIN(1, bsc_m3, vc_i2c0, gpclk1, enet0, vc_pwm1, sr_edm_sense, vc_spi0, vc_uart3),
> + PIN(2, pdm, i2s_in, gpclk2, vc_spi4, pkt, vc_spi0, vc_uart3, _),
> + PIN(3, pdm, i2s_in, vc_spi4, pkt, vc_spi0, vc_uart3, _, _),
> + PIN(4, pdm, i2s_in, arm_jtag, vc_spi4, pkt, vc_spi0, vc_uart3, _),
> + PIN(5, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
> + PIN(6, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
> + PIN(7, i2s_out, spdif_out, arm_jtag, sd_card_e, vc_i2c3, enet0_rgmii, vc_pcm, vc_spi4),
> + PIN(8, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, vc_i2c3, enet0_mii, vc_pcm, vc_spi4),
> + PIN(9, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, enet0_mii, sd_card_c, vc_spi4, _),
> + PIN(10, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
> + PIN(11, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
> + PIN(12, spi_s, mtsif_alt1, i2s_in, i2s_out, vc_spi5, vc_i2csl, sd0, sd_card_d),
> + PIN(13, spi_s, mtsif_alt1, i2s_out, usb_vbus, vc_spi5, vc_i2csl, sd0, sd_card_d),
> + PIN(14, spi_s, vc_i2csl, enet0_rgmii, arm_jtag, vc_spi5, vc_pwm0, vc_i2c4, sd_card_d),
> + PIN(15, spi_s, vc_i2csl, vc_spi3, arm_jtag, vc_pwm0, vc_i2c4, gpclk0, _),
> + PIN(16, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, gpclk1, _),
> + PIN(17, sd_card_b, i2s_out, vc_spi3, i2s_in, ext_sc_clk, sd0, enet0_rgmii, gpclk2),
> + PIN(18, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, vc_pwm1, _),
> + PIN(19, sd_card_b, usb_pwr, vc_spi3, pkt, spdif_out, sd0, ir_in, vc_pwm1),
> + PIN(20, sd_card_b, uui, vc_uart0, arm_jtag, uart2, usb_pwr, vc_pcm, vc_uart4),
> + PIN(21, usb_pwr, uui, vc_uart0, arm_jtag, uart2, sd_card_b, vc_pcm, vc_uart4),
> + PIN(22, usb_pwr, enet0, vc_uart0, mtsif, uart2, usb_vbus, vc_pcm, vc_i2c5),
> + PIN(23, usb_vbus, enet0, vc_uart0, mtsif, uart2, i2s_out, vc_pcm, vc_i2c5),
> + PIN(24, mtsif, pkt, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3, _),
> + PIN(25, mtsif, pkt, sc0, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3),
> + PIN(26, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
> + PIN(27, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
> + PIN(28, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
> + PIN(29, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
> + PIN(30, mtsif, pkt, sc0, sd2, enet0_rgmii, gpclk0, vc_pwm0, _),
> + PIN(31, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_pwm0, _),
> + PIN(32, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_uart3, _),
> + PIN(33, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_uart3, _, _),
> + PIN(34, mtsif, pkt, ext_sc_clk, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _),
> + PIN(35, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _, _),
> + PIN(36, sd0, mtsif, sc0, i2s_in, vc_uart3, vc_uart2, _, _),
> + PIN(37, sd0, mtsif, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
> + PIN(38, sd0, mtsif_alt, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
> + PIN(39, sd0, mtsif_alt, sc0, vc_spi0, vc_uart3, vc_uart2, _, _),
> + PIN(40, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
> + PIN(41, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
> + PIN(42, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
> + PIN(43, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
> + PIN(44, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
> + PIN(45, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
> + PIN(46, vc_spi0, mtsif_alt, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m, _),
> + PIN(47, enet0, mtsif_alt, i2s_out, mtsif_alt1, arm_jtag, _, _, _),
> + PIN(48, sc0, usb_pwr, spdif_out, mtsif, _, _, _, _),
> + PIN(49, sc0, usb_pwr, aud_fs_clk0, mtsif, _, _, _, _),
> + PIN(50, sc0, usb_vbus, sc0, _, _, _, _, _),
> + PIN(51, sc0, enet0, sc0, sr_edm_sense, _, _, _, _),
> + PIN(52, sc0, enet0, vc_pwm1, _, _, _, _, _),
> + PIN(53, sc0, enet0_rgmii, ext_sc_clk, _, _, _, _, _),
> +};
> +
> +static const struct brcmstb_pin_funcs bcm2712_d0_aon_gpio_pin_funcs[] = {
> + PIN(0, ir_in, vc_spi0, vc_uart0, vc_i2c3, uart0, vc_i2c0, _, _),
> + PIN(1, vc_pwm0, vc_spi0, vc_uart0, vc_i2c3, uart0, aon_pwm, vc_i2c0, vc_pwm1),
> + PIN(2, vc_pwm0, vc_spi0, vc_uart0, ctl_hdmi_5v, uart0, aon_pwm, ir_in, vc_pwm1),
> + PIN(3, ir_in, vc_spi0, vc_uart0, uart0, sd_card_g, aon_gpclk, _, _),
> + PIN(4, gpclk0, vc_spi0, pm_led_out, aon_pwm, sd_card_g, vc_pwm0, _, _),
> + PIN(5, gpclk1, ir_in, aon_pwm, sd_card_g, vc_pwm0, _, _, _),
> + PIN(6, uart1, vc_uart2, ctl_hdmi_5v, gpclk2, vc_spi3, _, _, _),
> + PIN(7, _, _, _, _, _, _, _, _),
> + PIN(8, uart1, vc_uart2, ctl_hdmi_5v, vc_spi0, vc_spi3, _, _, _),
> + PIN(9, uart1, vc_uart2, vc_uart0, aon_pwm, vc_spi0, vc_uart2, vc_spi3, _),
> + PIN(10, _, _, _, _, _, _, _, _),
> + PIN(11, _, _, _, _, _, _, _, _),
> + PIN(12, uart1, vc_uart2, vc_uart0, vc_spi0, usb_pwr, vc_uart2, vc_spi3, _),
> + PIN(13, bsc_m1, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3, _),
> + PIN(14, bsc_m1, aon_gpclk, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3),
> +};
> +
> +static const struct brcmstb_pin_funcs bcm2712_d0_aon_sgpio_pin_funcs[] = {
> + PIN(0, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
> + PIN(1, hdmi_tx0_bsc, hdmi_tx0_auto_i2c, bsc_m0, vc_i2c0, _, _, _, _),
> + PIN(2, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c0, ctl_hdmi_5v, _, _, _),
> + PIN(3, hdmi_tx1_bsc, hdmi_tx1_auto_i2c, bsc_m1, vc_i2c0, _, _, _, _),
> + PIN(4, avs_pmu_bsc, bsc_m2, vc_i2c3, ctl_hdmi_5v, _, _, _, _),
> + PIN(5, avs_pmu_bsc, bsc_m2, vc_i2c3, _, _, _, _, _),
> +};
> +
> +static const struct brcmstb_pin_funcs bcm2712_d0_gpio_pin_funcs[] = {
> + PIN(1, vc_i2c0, usb_pwr, gpclk0, sd_card_e, vc_spi3, sr_edm_sense, vc_spi0, vc_uart0),
> + PIN(2, vc_i2c0, usb_pwr, gpclk1, sd_card_e, vc_spi3, clk_observe, vc_spi0, vc_uart0),
> + PIN(3, vc_i2c3, usb_vbus, gpclk2, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
> + PIN(4, vc_i2c3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
> + PIN(10, bsc_m3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, gpclk0, _, _),
> + PIN(11, bsc_m3, vc_spi3, clk_observe, sd_card_c, gpclk1, _, _, _),
> + PIN(12, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
> + PIN(13, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
> + PIN(14, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, sd_card_d, _, _),
> + PIN(15, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, gpclk0, _, _),
> + PIN(18, sd_card_f, vc_pwm1, _, _, _, _, _, _),
> + PIN(19, sd_card_f, usb_pwr, vc_pwm1, _, _, _, _, _),
> + PIN(20, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
> + PIN(21, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
> + PIN(22, sd_card_f, vc_uart0, vc_i2c3, _, _, _, _, _),
> + PIN(23, vc_uart0, vc_i2c3, _, _, _, _, _, _),
> + PIN(24, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
> + PIN(25, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
> + PIN(26, sd_card_b, vc_spi0, arm_jtag, uart0, usb_vbus, vc_uart2, vc_spi0, _),
> + PIN(27, sd_card_b, vc_spi0, arm_jtag, uart0, vc_uart2, vc_spi0, _, _),
> + PIN(28, sd_card_b, vc_spi0, arm_jtag, vc_i2c0, vc_spi0, _, _, _),
> + PIN(29, arm_jtag, vc_i2c0, vc_spi0, _, _, _, _, _),
> + PIN(30, sd2, gpclk0, vc_pwm0, _, _, _, _, _),
> + PIN(31, sd2, vc_spi3, vc_pwm0, _, _, _, _, _),
> + PIN(32, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
> + PIN(33, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
> + PIN(34, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
> + PIN(35, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
> +};
> +
> +static inline u32 brcmstb_reg_rd(struct brcmstb_pinctrl *pc, unsigned int reg)
> +{
> + return readl(pc->base + reg);
> +}
> +
> +static inline void brcmstb_reg_wr(struct brcmstb_pinctrl *pc, unsigned int reg,
> + u32 val)
> +{
> + writel(val, pc->base + reg);
> +}
> +
> +static enum brcmstb_funcs brcmstb_pinctrl_fsel_get(struct brcmstb_pinctrl *pc,
> + unsigned int pin)
> +{
> + u32 bit = pc->pin_regs[pin].mux_bit;
> + enum brcmstb_funcs func;
> + int fsel;
> + u32 val;
> +
> + if (!bit)
> + return func_gpio;
> +
> + bit &= ~MUX_BIT_VALID;
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + fsel = (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_FSEL_MASK;
> + func = pc->pin_funcs[pin].funcs[fsel];
> +
> + if (func >= func_count)
> + func = (enum brcmstb_funcs)fsel;
> +
> + dev_dbg(pc->dev, "get %04x: %08x (%u => %s)\n",
> + BIT_TO_REG(bit), val, pin,
> + brcmstb_func_names[func]);
> +
> + return func;
> +}
> +
> +static void brcmstb_pinctrl_fsel_set(struct brcmstb_pinctrl *pc,
> + unsigned int pin, enum brcmstb_funcs func)
> +{
> + u32 bit = pc->pin_regs[pin].mux_bit, val;
> + const u8 *pin_funcs;
> + unsigned long flags;
> + int fsel;
> + int cur;
> + int i;
> +
> + if (!bit || func >= func_count)
> + return;
> +
> + bit &= ~MUX_BIT_VALID;
> +
> + fsel = BRCMSTB_FSEL_COUNT;
> +
> + if (func >= BRCMSTB_FSEL_COUNT) {
> + /* Convert to an fsel number */
> + pin_funcs = pc->pin_funcs[pin].funcs;
> + for (i = 1; i < BRCMSTB_FSEL_COUNT; i++) {
> + if (pin_funcs[i - 1] == func) {
> + fsel = i;
> + break;
> + }
> + }
> + } else {
> + fsel = (enum brcmstb_funcs)func;
> + }
> +
> + if (fsel >= BRCMSTB_FSEL_COUNT)
> + return;
> +
> + spin_lock_irqsave(&pc->lock, flags);
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + cur = (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_FSEL_MASK;
> +
> + dev_dbg(pc->dev, "read %04x: %08x (%u => %s)\n",
> + BIT_TO_REG(bit), val, pin,
> + brcmstb_func_names[cur]);
> +
> + if (cur != fsel) {
> + val &= ~(BRCMSTB_FSEL_MASK << BIT_TO_SHIFT(bit));
> + val |= fsel << BIT_TO_SHIFT(bit);
> +
> + dev_dbg(pc->dev, "write %04x: %08x (%u <= %s)\n",
> + BIT_TO_REG(bit), val, pin,
> + brcmstb_func_names[fsel]);
> + brcmstb_reg_wr(pc, BIT_TO_REG(bit), val);
> + }
> +
> + spin_unlock_irqrestore(&pc->lock, flags);
> +}
> +
> +static int brcmstb_pctl_get_groups_count(struct pinctrl_dev *pctldev)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pc->pctl_desc.npins;
> +}
> +
> +static const char *brcmstb_pctl_get_group_name(struct pinctrl_dev *pctldev,
> + unsigned int selector)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pc->gpio_groups[selector];
> +}
> +
> +static int brcmstb_pctl_get_group_pins(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const unsigned int **pins,
> + unsigned int *num_pins)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + *pins = &pc->pctl_desc.pins[selector].number;
> + *num_pins = 1;
> +
> + return 0;
> +}
> +
> +static void brcmstb_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
> + struct seq_file *s, unsigned int offset)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + enum brcmstb_funcs fsel = brcmstb_pinctrl_fsel_get(pc, offset);
> + const char *fname = brcmstb_func_names[fsel];
> +
> + seq_printf(s, "function %s", fname);
> +}
> +
> +static void brcmstb_pctl_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *maps,
> + unsigned int num_maps)
> +{
> + int i;
> +
> + for (i = 0; i < num_maps; i++)
> + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
> + kfree(maps[i].data.configs.configs);
> +
> + kfree(maps);
> +}
> +
> +static const struct pinctrl_ops brcmstb_pctl_ops = {
> + .get_groups_count = brcmstb_pctl_get_groups_count,
> + .get_group_name = brcmstb_pctl_get_group_name,
> + .get_group_pins = brcmstb_pctl_get_group_pins,
> + .pin_dbg_show = brcmstb_pctl_pin_dbg_show,
> + .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
> + .dt_free_map = brcmstb_pctl_dt_free_map,
> +};
> +
> +static int brcmstb_pmx_free(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + /* disable by setting to GPIO */
> + brcmstb_pinctrl_fsel_set(pc, offset, func_gpio);
> + return 0;
> +}
> +
> +static int brcmstb_pmx_get_functions_count(struct pinctrl_dev *pctldev)
> +{
> + return func_count;
> +}
> +
> +static const char *brcmstb_pmx_get_function_name(struct pinctrl_dev *pctldev,
> + unsigned int selector)
> +{
> + return (selector < func_count) ? brcmstb_func_names[selector] : NULL;
> +}
> +
> +static int brcmstb_pmx_get_function_groups(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const char *const **groups,
> + unsigned *const num_groups)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + *groups = pc->gpio_groups;
> + *num_groups = pc->pctl_desc.npins;
> +
> + return 0;
> +}
> +
> +static int brcmstb_pmx_set(struct pinctrl_dev *pctldev,
> + unsigned int func_selector,
> + unsigned int group_selector)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + const struct pinctrl_desc *pctldesc = &pc->pctl_desc;
> + const struct pinctrl_pin_desc *pindesc;
> +
> + if (group_selector >= pctldesc->npins)
> + return -EINVAL;
> +
> + pindesc = &pctldesc->pins[group_selector];
> + brcmstb_pinctrl_fsel_set(pc, pindesc->number, func_selector);
> +
> + return 0;
> +}
> +
> +static int brcmstb_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned int pin)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + brcmstb_pinctrl_fsel_set(pc, pin, func_gpio);
> +
> + return 0;
> +}
> +
> +static void brcmstb_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned int offset)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + /* disable by setting to GPIO */
> + brcmstb_pinctrl_fsel_set(pc, offset, func_gpio);
> +}
> +
> +static const struct pinmux_ops brcmstb_pmx_ops = {
> + .free = brcmstb_pmx_free,
> + .get_functions_count = brcmstb_pmx_get_functions_count,
> + .get_function_name = brcmstb_pmx_get_function_name,
> + .get_function_groups = brcmstb_pmx_get_function_groups,
> + .set_mux = brcmstb_pmx_set,
> + .gpio_request_enable = brcmstb_pmx_gpio_request_enable,
> + .gpio_disable_free = brcmstb_pmx_gpio_disable_free,
> +};
> +
> +static unsigned int brcmstb_pull_config_get(struct brcmstb_pinctrl *pc,
> + unsigned int pin)
> +{
> + u32 bit = pc->pin_regs[pin].pad_bit, val;
> +
> + if (bit == REG_BIT_INVALID)
> + return BRCMSTB_PULL_NONE;
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + return (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_PULL_MASK;
> +}
> +
> +static void brcmstb_pull_config_set(struct brcmstb_pinctrl *pc,
> + unsigned int pin, unsigned int arg)
> +{
> + u32 bit = pc->pin_regs[pin].pad_bit, val;
> + unsigned long flags;
> +
> + if (bit == REG_BIT_INVALID) {
> + dev_warn(pc->dev, "Can't set pulls for %s\n",
> + pc->gpio_groups[pin]);
> + return;
> + }
> +
> + spin_lock_irqsave(&pc->lock, flags);
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + val &= ~(BRCMSTB_PULL_MASK << BIT_TO_SHIFT(bit));
> + val |= (arg << BIT_TO_SHIFT(bit));
> + brcmstb_reg_wr(pc, BIT_TO_REG(bit), val);
> +
> + spin_unlock_irqrestore(&pc->lock, flags);
> +}
> +
> +static int brcmstb_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
> + unsigned long *config)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + enum pin_config_param param = pinconf_to_config_param(*config);
> + u32 arg;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_NONE);
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_DOWN);
> + break;
> + case PIN_CONFIG_BIAS_PULL_UP:
> + arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_UP);
> + break;
> + default:
> + return -ENOTSUPP;
> + }
> +
> + *config = pinconf_to_config_packed(param, arg);
> +
> + return 0;
> +}
> +
> +static int brcmstb_pinconf_set(struct pinctrl_dev *pctldev,
> + unsigned int pin, unsigned long *configs,
> + unsigned int num_configs)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + u32 param, arg;
> + int i;
> +
> + for (i = 0; i < num_configs; i++) {
> + param = pinconf_to_config_param(configs[i]);
> + arg = pinconf_to_config_argument(configs[i]);
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_NONE);
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_DOWN);
> + break;
> + case PIN_CONFIG_BIAS_PULL_UP:
> + brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_UP);
> + break;
> + default:
> + return -ENOTSUPP;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct pinconf_ops brcmstb_pinconf_ops = {
> + .is_generic = true,
> + .pin_config_get = brcmstb_pinconf_get,
> + .pin_config_set = brcmstb_pinconf_set,
> +};
> +
> +static const struct pinctrl_desc bcm2712_c0_pinctrl_desc = {
> + .name = "pinctrl-bcm2712",
> + .pins = bcm2712_c0_gpio_pins,
> + .npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
> + .pctlops = &brcmstb_pctl_ops,
> + .pmxops = &brcmstb_pmx_ops,
> + .confops = &brcmstb_pinconf_ops,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct pinctrl_desc bcm2712_c0_aon_pinctrl_desc = {
> + .name = "aon-pinctrl-bcm2712",
> + .pins = bcm2712_c0_aon_gpio_pins,
> + .npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
> + .pctlops = &brcmstb_pctl_ops,
> + .pmxops = &brcmstb_pmx_ops,
> + .confops = &brcmstb_pinconf_ops,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct pinctrl_desc bcm2712_d0_pinctrl_desc = {
> + .name = "pinctrl-bcm2712",
> + .pins = bcm2712_d0_gpio_pins,
> + .npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
> + .pctlops = &brcmstb_pctl_ops,
> + .pmxops = &brcmstb_pmx_ops,
> + .confops = &brcmstb_pinconf_ops,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct pinctrl_desc bcm2712_d0_aon_pinctrl_desc = {
> + .name = "aon-pinctrl-bcm2712",
> + .pins = bcm2712_d0_aon_gpio_pins,
> + .npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
> + .pctlops = &brcmstb_pctl_ops,
> + .pmxops = &brcmstb_pmx_ops,
> + .confops = &brcmstb_pinconf_ops,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct pinctrl_gpio_range bcm2712_c0_pinctrl_gpio_range = {
> + .name = "pinctrl-bcm2712",
> + .npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
> +};
> +
> +static const struct pinctrl_gpio_range bcm2712_c0_aon_pinctrl_gpio_range = {
> + .name = "aon-pinctrl-bcm2712",
> + .npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
> +};
> +
> +static const struct pinctrl_gpio_range bcm2712_d0_pinctrl_gpio_range = {
> + .name = "pinctrl-bcm2712",
> + .npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
> +};
> +
> +static const struct pinctrl_gpio_range bcm2712_d0_aon_pinctrl_gpio_range = {
> + .name = "aon-pinctrl-bcm2712",
> + .npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
> +};
> +
> +static const struct brcmstb_pdata bcm2712_c0_pdata = {
> + .pctl_desc = &bcm2712_c0_pinctrl_desc,
> + .gpio_range = &bcm2712_c0_pinctrl_gpio_range,
> + .pin_regs = bcm2712_c0_gpio_pin_regs,
> + .pin_funcs = bcm2712_c0_gpio_pin_funcs,
> +};
> +
> +static const struct brcmstb_pdata bcm2712_c0_aon_pdata = {
> + .pctl_desc = &bcm2712_c0_aon_pinctrl_desc,
> + .gpio_range = &bcm2712_c0_aon_pinctrl_gpio_range,
> + .pin_regs = bcm2712_c0_aon_gpio_pin_regs,
> + .pin_funcs = bcm2712_c0_aon_gpio_pin_funcs,
> +};
> +
> +static const struct brcmstb_pdata bcm2712_d0_pdata = {
> + .pctl_desc = &bcm2712_d0_pinctrl_desc,
> + .gpio_range = &bcm2712_d0_pinctrl_gpio_range,
> + .pin_regs = bcm2712_d0_gpio_pin_regs,
> + .pin_funcs = bcm2712_d0_gpio_pin_funcs,
> +};
> +
> +static const struct brcmstb_pdata bcm2712_d0_aon_pdata = {
> + .pctl_desc = &bcm2712_d0_aon_pinctrl_desc,
> + .gpio_range = &bcm2712_d0_aon_pinctrl_gpio_range,
> + .pin_regs = bcm2712_d0_aon_gpio_pin_regs,
> + .pin_funcs = bcm2712_d0_aon_gpio_pin_funcs,
> +};
> +
> +static const struct of_device_id brcmstb_pinctrl_match[] = {
> + {
> + .compatible = "brcm,bcm2712-pinctrl",
> + .data = &bcm2712_c0_pdata
> + },
> + {
> + .compatible = "brcm,bcm2712-aon-pinctrl",
> + .data = &bcm2712_c0_aon_pdata
> + },
> +
> + {
> + .compatible = "brcm,bcm2712c0-pinctrl",
> + .data = &bcm2712_c0_pdata
> + },
> + {
> + .compatible = "brcm,bcm2712c0-aon-pinctrl",
> + .data = &bcm2712_c0_aon_pdata
> + },
> +
> + {
> + .compatible = "brcm,bcm2712d0-pinctrl",
> + .data = &bcm2712_d0_pdata
> + },
> + {
> + .compatible = "brcm,bcm2712d0-aon-pinctrl",
> + .data = &bcm2712_d0_aon_pdata
> + },
> + { /* sentinel */ }
> +};
> +
> +static int brcmstb_pinctrl_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + const struct brcmstb_pdata *pdata;
> + const struct of_device_id *match;
> + struct brcmstb_pinctrl *pc;
> + const char **names;
> + int num_pins, i;
> +
> + match = of_match_node(brcmstb_pinctrl_match, np);
> + pdata = match->data;
> +
> + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
> + if (!pc)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, pc);
> + pc->dev = dev;
> + spin_lock_init(&pc->lock);
> +
> + pc->base = devm_of_iomap(dev, np, 0, NULL);
> + if (IS_ERR(pc->base))
> + return dev_err_probe(&pdev->dev, PTR_ERR(pc->base),
> + "Could not get IO memory\n");
> +
> + pc->pctl_desc = *pdata->pctl_desc;
> + num_pins = pc->pctl_desc.npins;
> + names = devm_kmalloc_array(dev, num_pins, sizeof(const char *),
> + GFP_KERNEL);
> + if (!names)
> + return -ENOMEM;
> +
> + for (i = 0; i < num_pins; i++)
> + names[i] = pc->pctl_desc.pins[i].name;
> +
> + pc->gpio_groups = names;
> + pc->pin_regs = pdata->pin_regs;
> + pc->pin_funcs = pdata->pin_funcs;
> + pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
> + if (IS_ERR(pc->pctl_dev))
> + return dev_err_probe(&pdev->dev, PTR_ERR(pc->pctl_dev),
> + "Failed to register pinctrl device\n");
> +
> + pc->gpio_range = *pdata->gpio_range;
> + pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
> +
> + return 0;
> +}
> +
> +static struct platform_driver brcmstb_pinctrl_driver = {
> + .probe = brcmstb_pinctrl_probe,
> + .driver = {
> + .name = "pinctrl-brcmstb",
> + .of_match_table = brcmstb_pinctrl_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +module_platform_driver(brcmstb_pinctrl_driver);
> +
> +MODULE_AUTHOR("Phil Elwell");
> +MODULE_AUTHOR("Jonathan Bell");
> +MODULE_AUTHOR("Ivan T. Ivanov");
> +MODULE_DESCRIPTION("Broadcom brcmstb pinctrl driver");
> +MODULE_LICENSE("GPL");
> --
> 2.43.0
>
Reviewed-by: Phil Elwell <phil@raspberrypi.com>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-07-31 6:28 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Ivan T. Ivanov
2024-08-01 8:17 ` Krzysztof Kozlowski
@ 2024-08-02 18:09 ` Stefan Wahren
2024-08-12 16:28 ` Dave Stevenson
1 sibling, 1 reply; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 18:09 UTC (permalink / raw)
To: Ivan T. Ivanov, kernel-list, florian.fainelli, andrea.porta
Cc: conor+dt, krzk+dt, linux-gpio, devicetree, linux-arm-kernel, robh,
linus.walleij
Hi,
[add official Raspberry Pi kernel developer list]
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> It looks like they are few revisions of this chip which varies
> by number of pins. Perhaps not all of them are available on the
> market. Perhaps some of them where early engineering samples,
> I don't know. I decided to keep all of them just in case.
The BCM2711 had also some revisions and we avoided successfully multiple
versions of the RPi 4B DTS. So it would be nice if someone can explain
if C0 & D0 are available in the market? Otherwise we may end up with
multiple versions of the RPi 5 DTS.
I'm missing an explanation in the commit message, what's the difference
between brcm,bcm2712-pinctrl and brcm,bcm2712-aon-pinctrl?
According to the driver brcm,bcm2712-pinctrl is the same as
brcm,bcm2712c0-pinctrl. So the former is more a fallback?
Thanks
>
> Cc: Andrea della Porta <andrea.porta@suse.com>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../pinctrl/brcm,brcmstb-pinctrl.yaml | 73 +++++++++++++++++++
> 1 file changed, 73 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> new file mode 100644
> index 000000000000..c5afdb49d784
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom STB family pin controller
> +
> +maintainers:
> + - Ivan T. Ivanov <iivanov@suse.de>
> +
> +description:
> + Broadcom's STB family memory-mapped pin controller.
> +
> +properties:
> + compatible:
> + enum:
> + - brcm,bcm2712-pinctrl
> + - brcm,bcm2712-aon-pinctrl
> + - brcm,bcm2712c0-pinctrl
> + - brcm,bcm2712c0-aon-pinctrl
> + - brcm,bcm2712d0-pinctrl
> + - brcm,bcm2712d0-aon-pinctrl
> +
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver
2024-07-31 6:28 ` [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver Ivan T. Ivanov
2024-08-02 10:22 ` Phil Elwell
@ 2024-08-02 18:36 ` Stefan Wahren
2024-08-05 9:13 ` Stefan Wahren
2 siblings, 0 replies; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 18:36 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel, Jonathan Bell, Phil Elwell, kernel-list
Hi,
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> This driver provide pin muxing and configuration functionality
> for BCM2712 SoC used by RPi5. According to [1] this chips is
> incarnation of chip used in Broadcom STB product line.
>
> [1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
>
> Cc: Jonathan Bell <jonathan@raspberrypi.com>
> Cc: Phil Elwell <phil@raspberrypi.com>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> drivers/pinctrl/bcm/Kconfig | 13 +
> drivers/pinctrl/bcm/Makefile | 1 +
> drivers/pinctrl/bcm/pinctrl-brcmstb.c | 1217 +++++++++++++++++++++++++
> 3 files changed, 1231 insertions(+)
> create mode 100644 drivers/pinctrl/bcm/pinctrl-brcmstb.c
>
> diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
> index 35b51ce4298e..2e1b8d444f58 100644
> --- a/drivers/pinctrl/bcm/Kconfig
> +++ b/drivers/pinctrl/bcm/Kconfig
> @@ -3,6 +3,19 @@
> # Broadcom pinctrl drivers
> #
>
> +config PINCTRL_BRCMSTB
> + tristate "Broadcom STB product line pin controller driver"
> + depends on OF && (ARCH_BRCMSTB || COMPILE_TEST)
> + select PINMUX
> + select PINCONF
> + select GENERIC_PINCONF
> + help
> + This driver provide pin muxing and configuration functionality
> + for Broadcom STB product line chipsets. BCM2712 SoC is one of these
> + chipsets.
> +
> + If M is selected the module will be called pinctrl-brcmstb.
> +
> config PINCTRL_BCM281XX
> bool "Broadcom BCM281xx pinctrl driver"
> depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
> diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile
> index 82b868ec1471..5f790c14cc4c 100644
> --- a/drivers/pinctrl/bcm/Makefile
> +++ b/drivers/pinctrl/bcm/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
> obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
> obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
> obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o
> +obj-$(CONFIG_PINCTRL_BRCMSTB) += pinctrl-brcmstb.o
> obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
> obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
> obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
> diff --git a/drivers/pinctrl/bcm/pinctrl-brcmstb.c b/drivers/pinctrl/bcm/pinctrl-brcmstb.c
> new file mode 100644
> index 000000000000..143c8c2e1d6d
> --- /dev/null
> +++ b/drivers/pinctrl/bcm/pinctrl-brcmstb.c
> @@ -0,0 +1,1217 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Driver for Broadcom brcmstb GPIO units (pinctrl only)
> + *
Maybe you want to add your copyright here
> + * Copyright (C) 2021-3 Raspberry Pi Ltd.
> + * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
> + *
> + * Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
> + * pinctrl-nomadik.c, please see original file for copyright information
> + * pinctrl-tegra.c, please see original file for copyright information
> + */
> +
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/pinctrl/pinconf-generic.h>
> +#include <linux/platform_device.h>
> +#include <linux/seq_file.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define BRCMSTB_PULL_NONE 0
> +#define BRCMSTB_PULL_DOWN 1
> +#define BRCMSTB_PULL_UP 2
> +#define BRCMSTB_PULL_MASK 0x3
> +
> +#define BRCMSTB_FSEL_COUNT 9
> +#define BRCMSTB_FSEL_MASK 0xf
> +
> +#define FUNC(f) \
> + [func_##f] = #f
> +
> +#define PIN(i, f1, f2, f3, f4, f5, f6, f7, f8) \
> + [i] = { \
> + .funcs = { \
> + func_##f1, \
> + func_##f2, \
> + func_##f3, \
> + func_##f4, \
> + func_##f5, \
> + func_##f6, \
> + func_##f7, \
> + func_##f8, \
> + }, \
> + }
> +
> +#define MUX_BIT_VALID 0x8000
> +#define REG_BIT_INVALID 0xffff
> +
> +#define BIT_TO_REG(b) (((b) >> 5) << 2)
> +#define BIT_TO_SHIFT(b) ((b) & 0x1f)
> +
> +#define MUX_BIT(mr, mb) (MUX_BIT_VALID + ((mr) * 4) * 8 + (mb) * 4)
> +#define GPIO_REGS(n, mr, mb, pr, pb) \
> + [n] = { MUX_BIT(mr, mb), ((pr) * 4) * 8 + (pb) * 2 }
Please avoid these cryptic names: mr, mb, pr, pb
> +
> +#define EMMC_REGS(n, pr, pb) \
> + [n] = { 0, ((pr) * 4) * 8 + (pb) * 2 }
> +
> +#define AGPIO_REGS(n, mr, mb, pr, pb) \
> + [n] = { MUX_BIT(mr, mb), ((pr) * 4) * 8 + (pb) * 2 }
> +
> +#define SGPIO_REGS(n, mr, mb) \
> + [(n) + 32] = { MUX_BIT(mr, mb), REG_BIT_INVALID }
> +
> +#define GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
> +#define AGPIO_PIN(a) PINCTRL_PIN(a, "aon_gpio" #a)
> +#define SGPIO_PIN(a) PINCTRL_PIN((a) + 32, "aon_sgpio" #a)
> +
> +struct pin_regs {
> + u16 mux_bit;
> + u16 pad_bit;
> +};
> +
> +struct brcmstb_pin_funcs {
> + u8 funcs[BRCMSTB_FSEL_COUNT - 1];
> +};
> +
> +struct brcmstb_pinctrl {
> + struct device *dev;
> + void __iomem *base;
> + struct pinctrl_dev *pctl_dev;
> + struct pinctrl_desc pctl_desc;
> + const struct pin_regs *pin_regs;
> + const struct brcmstb_pin_funcs *pin_funcs;
> + const char *const *gpio_groups;
> + struct pinctrl_gpio_range gpio_range;
> + /* Protect FSEL registers */
> + spinlock_t lock;
fsel_lock ?
> +};
> +
> ...
> +
> +static const struct brcmstb_pin_funcs bcm2712_d0_aon_gpio_pin_funcs[] = {
> + PIN(0, ir_in, vc_spi0, vc_uart0, vc_i2c3, uart0, vc_i2c0, _, _),
> + PIN(1, vc_pwm0, vc_spi0, vc_uart0, vc_i2c3, uart0, aon_pwm, vc_i2c0, vc_pwm1),
> + PIN(2, vc_pwm0, vc_spi0, vc_uart0, ctl_hdmi_5v, uart0, aon_pwm, ir_in, vc_pwm1),
> + PIN(3, ir_in, vc_spi0, vc_uart0, uart0, sd_card_g, aon_gpclk, _, _),
> + PIN(4, gpclk0, vc_spi0, pm_led_out, aon_pwm, sd_card_g, vc_pwm0, _, _),
> + PIN(5, gpclk1, ir_in, aon_pwm, sd_card_g, vc_pwm0, _, _, _),
> + PIN(6, uart1, vc_uart2, ctl_hdmi_5v, gpclk2, vc_spi3, _, _, _),
> + PIN(7, _, _, _, _, _, _, _, _),
In case this pin is reserved or something a comment would be nice
> + PIN(8, uart1, vc_uart2, ctl_hdmi_5v, vc_spi0, vc_spi3, _, _, _),
> + PIN(9, uart1, vc_uart2, vc_uart0, aon_pwm, vc_spi0, vc_uart2, vc_spi3, _),
> + PIN(10, _, _, _, _, _, _, _, _),
> + PIN(11, _, _, _, _, _, _, _, _),
same as above
> + PIN(12, uart1, vc_uart2, vc_uart0, vc_spi0, usb_pwr, vc_uart2, vc_spi3, _),
> + PIN(13, bsc_m1, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3, _),
> + PIN(14, bsc_m1, aon_gpclk, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3),
> +};
> +
> ...
> +
> +static inline u32 brcmstb_reg_rd(struct brcmstb_pinctrl *pc, unsigned int reg)
> +{
> + return readl(pc->base + reg);
> +}
> +
> +static inline void brcmstb_reg_wr(struct brcmstb_pinctrl *pc, unsigned int reg,
> + u32 val)
> +{
> + writel(val, pc->base + reg);
> +}
> +
> +static enum brcmstb_funcs brcmstb_pinctrl_fsel_get(struct brcmstb_pinctrl *pc,
> + unsigned int pin)
> +{
> + u32 bit = pc->pin_regs[pin].mux_bit;
> + enum brcmstb_funcs func;
> + int fsel;
> + u32 val;
> +
> + if (!bit)
> + return func_gpio;
> +
> + bit &= ~MUX_BIT_VALID;
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + fsel = (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_FSEL_MASK;
> + func = pc->pin_funcs[pin].funcs[fsel];
> +
> + if (func >= func_count)
> + func = (enum brcmstb_funcs)fsel;
> +
> + dev_dbg(pc->dev, "get %04x: %08x (%u => %s)\n",
> + BIT_TO_REG(bit), val, pin,
> + brcmstb_func_names[func]);
> +
> + return func;
> +}
> +
> +static void brcmstb_pinctrl_fsel_set(struct brcmstb_pinctrl *pc,
> + unsigned int pin, enum brcmstb_funcs func)
I would prefer this function returns errors as int instead of silently
ignore them
> +{
> + u32 bit = pc->pin_regs[pin].mux_bit, val;
> + const u8 *pin_funcs;
> + unsigned long flags;
> + int fsel;
> + int cur;
> + int i;
> +
> + if (!bit || func >= func_count)
> + return;
> +
> + bit &= ~MUX_BIT_VALID;
> +
> + fsel = BRCMSTB_FSEL_COUNT;
> +
> + if (func >= BRCMSTB_FSEL_COUNT) {
> + /* Convert to an fsel number */
> + pin_funcs = pc->pin_funcs[pin].funcs;
> + for (i = 1; i < BRCMSTB_FSEL_COUNT; i++) {
> + if (pin_funcs[i - 1] == func) {
> + fsel = i;
> + break;
> + }
> + }
> + } else {
> + fsel = (enum brcmstb_funcs)func;
> + }
> +
> + if (fsel >= BRCMSTB_FSEL_COUNT)
> + return;
> +
> + spin_lock_irqsave(&pc->lock, flags);
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + cur = (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_FSEL_MASK;
> +
> + dev_dbg(pc->dev, "read %04x: %08x (%u => %s)\n",
> + BIT_TO_REG(bit), val, pin,
> + brcmstb_func_names[cur]);
> +
> + if (cur != fsel) {
> + val &= ~(BRCMSTB_FSEL_MASK << BIT_TO_SHIFT(bit));
> + val |= fsel << BIT_TO_SHIFT(bit);
> +
> + dev_dbg(pc->dev, "write %04x: %08x (%u <= %s)\n",
> + BIT_TO_REG(bit), val, pin,
> + brcmstb_func_names[fsel]);
> + brcmstb_reg_wr(pc, BIT_TO_REG(bit), val);
> + }
> +
> + spin_unlock_irqrestore(&pc->lock, flags);
> +}
> +
> +static int brcmstb_pctl_get_groups_count(struct pinctrl_dev *pctldev)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pc->pctl_desc.npins;
> +}
> +
> +static const char *brcmstb_pctl_get_group_name(struct pinctrl_dev *pctldev,
> + unsigned int selector)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pc->gpio_groups[selector];
> +}
> +
> +static int brcmstb_pctl_get_group_pins(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const unsigned int **pins,
> + unsigned int *num_pins)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + *pins = &pc->pctl_desc.pins[selector].number;
> + *num_pins = 1;
> +
> + return 0;
> +}
> +
> +static void brcmstb_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
> + struct seq_file *s, unsigned int offset)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + enum brcmstb_funcs fsel = brcmstb_pinctrl_fsel_get(pc, offset);
> + const char *fname = brcmstb_func_names[fsel];
> +
> + seq_printf(s, "function %s", fname);
> +}
> +
> +static void brcmstb_pctl_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *maps,
> + unsigned int num_maps)
> +{
> + int i;
> +
> + for (i = 0; i < num_maps; i++)
> + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
> + kfree(maps[i].data.configs.configs);
> +
> + kfree(maps);
> +}
> +
> +static const struct pinctrl_ops brcmstb_pctl_ops = {
> + .get_groups_count = brcmstb_pctl_get_groups_count,
> + .get_group_name = brcmstb_pctl_get_group_name,
> + .get_group_pins = brcmstb_pctl_get_group_pins,
> + .pin_dbg_show = brcmstb_pctl_pin_dbg_show,
> + .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
> + .dt_free_map = brcmstb_pctl_dt_free_map,
> +};
> +
> +static int brcmstb_pmx_free(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + /* disable by setting to GPIO */
> + brcmstb_pinctrl_fsel_set(pc, offset, func_gpio);
> + return 0;
> +}
> +
> +static int brcmstb_pmx_get_functions_count(struct pinctrl_dev *pctldev)
> +{
> + return func_count;
> +}
> +
> +static const char *brcmstb_pmx_get_function_name(struct pinctrl_dev *pctldev,
> + unsigned int selector)
> +{
> + return (selector < func_count) ? brcmstb_func_names[selector] : NULL;
> +}
> +
> +static int brcmstb_pmx_get_function_groups(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const char *const **groups,
> + unsigned *const num_groups)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + *groups = pc->gpio_groups;
> + *num_groups = pc->pctl_desc.npins;
> +
> + return 0;
> +}
> +
> +static int brcmstb_pmx_set(struct pinctrl_dev *pctldev,
> + unsigned int func_selector,
> + unsigned int group_selector)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + const struct pinctrl_desc *pctldesc = &pc->pctl_desc;
> + const struct pinctrl_pin_desc *pindesc;
> +
> + if (group_selector >= pctldesc->npins)
> + return -EINVAL;
> +
> + pindesc = &pctldesc->pins[group_selector];
> + brcmstb_pinctrl_fsel_set(pc, pindesc->number, func_selector);
return brcmstb_pinctrl_fsel_set
> +
> + return 0;
> +}
> +
> +static int brcmstb_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned int pin)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + brcmstb_pinctrl_fsel_set(pc, pin, func_gpio);
> +
> + return 0;
return brcmstb_pinctrl_fsel_set
> +}
> +
> +static void brcmstb_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned int offset)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> +
> + /* disable by setting to GPIO */
> + brcmstb_pinctrl_fsel_set(pc, offset, func_gpio);
> +}
> +
> +static const struct pinmux_ops brcmstb_pmx_ops = {
> + .free = brcmstb_pmx_free,
> + .get_functions_count = brcmstb_pmx_get_functions_count,
> + .get_function_name = brcmstb_pmx_get_function_name,
> + .get_function_groups = brcmstb_pmx_get_function_groups,
> + .set_mux = brcmstb_pmx_set,
> + .gpio_request_enable = brcmstb_pmx_gpio_request_enable,
> + .gpio_disable_free = brcmstb_pmx_gpio_disable_free,
> +};
> +
> +static unsigned int brcmstb_pull_config_get(struct brcmstb_pinctrl *pc,
> + unsigned int pin)
> +{
> + u32 bit = pc->pin_regs[pin].pad_bit, val;
> +
> + if (bit == REG_BIT_INVALID)
> + return BRCMSTB_PULL_NONE;
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + return (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_PULL_MASK;
> +}
> +
> +static void brcmstb_pull_config_set(struct brcmstb_pinctrl *pc,
> + unsigned int pin, unsigned int arg)
The same here, returning an error would be better
> +{
> + u32 bit = pc->pin_regs[pin].pad_bit, val;
> + unsigned long flags;
> +
> + if (bit == REG_BIT_INVALID) {
> + dev_warn(pc->dev, "Can't set pulls for %s\n",
> + pc->gpio_groups[pin]);
> + return;
> + }
> +
> + spin_lock_irqsave(&pc->lock, flags);
> +
> + val = brcmstb_reg_rd(pc, BIT_TO_REG(bit));
> + val &= ~(BRCMSTB_PULL_MASK << BIT_TO_SHIFT(bit));
> + val |= (arg << BIT_TO_SHIFT(bit));
> + brcmstb_reg_wr(pc, BIT_TO_REG(bit), val);
> +
> + spin_unlock_irqrestore(&pc->lock, flags);
> +}
> +
> +static int brcmstb_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
> + unsigned long *config)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + enum pin_config_param param = pinconf_to_config_param(*config);
> + u32 arg;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_NONE);
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_DOWN);
> + break;
> + case PIN_CONFIG_BIAS_PULL_UP:
> + arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_UP);
> + break;
> + default:
> + return -ENOTSUPP;
> + }
> +
> + *config = pinconf_to_config_packed(param, arg);
> +
> + return 0;
> +}
> +
> +static int brcmstb_pinconf_set(struct pinctrl_dev *pctldev,
> + unsigned int pin, unsigned long *configs,
> + unsigned int num_configs)
> +{
> + struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
> + u32 param, arg;
> + int i;
> +
> + for (i = 0; i < num_configs; i++) {
> + param = pinconf_to_config_param(configs[i]);
> + arg = pinconf_to_config_argument(configs[i]);
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_NONE);
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_DOWN);
> + break;
> + case PIN_CONFIG_BIAS_PULL_UP:
> + brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_UP);
In case brcmstb_pull_config_set would return an error, we shouldn't
ignore it here
Thanks
> + break;
> + default:
> + return -ENOTSUPP;
> + }
> + }
> +
> + return 0;
> +}
> +
> +
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node
2024-07-31 6:28 ` [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node Ivan T. Ivanov
2024-07-31 22:11 ` Florian Fainelli
@ 2024-08-02 18:49 ` Stefan Wahren
2024-08-02 19:08 ` Stefan Wahren
2 siblings, 0 replies; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 18:49 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel, kernel-list
Hi,
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> Add GPIO and related interrupt controller nodes and wire one
> of the lines to power button.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 21 +++++++++++++++++++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 21 +++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> index 8a0d20afebfe..06e926af16b7 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> @@ -2,6 +2,7 @@
> /dts-v1/;
>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> #include "bcm2712.dtsi"
>
> / {
> @@ -44,6 +45,21 @@ sd_vcc_reg: sd-vcc-reg {
> enable-active-high;
> gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
> };
> +
> + pwr-button {
gpio-keys
> + compatible = "gpio-keys";
> +
Please drop the empty line
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwr_button_pins>;
> + status = "okay";
> +
> + pwr_key: pwr {
power_button: power-button
or do we need keep the reference name for compatibility?
> + label = "pwr_button";
> + linux,code = <KEY_POWER>;
> + gpios = <&gio 20 GPIO_ACTIVE_LOW>;
> + debounce-interval = <50>;
> + };
> + };
> };
>
> /* The system UART */
> @@ -73,6 +89,11 @@ emmc_aon_cd_pins: emmc-aon-cd-pins {
> };
>
> &pinctrl {
> + pwr_button_pins: pwr-button-pins {
> + function = "gpio";
> + pins = "gpio20";
> + bias-pull-up;
> + };
>
> emmc_sd_pulls: emmc-sd-pulls {
> pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 1099171cd435..39d2419ffce2 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -271,6 +271,27 @@ pinctrl: pinctrl@7d504100 {
> reg = <0x7d504100 0x30>;
> };
>
> + main_irq: intc@7d508400 {
> + compatible = "brcm,bcm7271-l2-intc";
> + reg = <0x7d508400 0x10>;
> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gio: gpio@7d508500 {
> + compatible = "brcm,brcmstb-gpio";
> + reg = <0x7d508500 0x40>;
> + interrupt-parent = <&main_irq>;
> + interrupts = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + brcm,gpio-bank-widths = <32 22>;
> + brcm,gpio-direct;
> + };
> +
> pinctrl_aon: pinctrl@7d510700 {
> compatible = "brcm,bcm2712-aon-pinctrl";
> reg = <0x7d510700 0x20>;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
2024-07-31 6:28 ` [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node Ivan T. Ivanov
@ 2024-08-02 19:01 ` Stefan Wahren
2025-05-12 13:42 ` Ivan T. Ivanov
0 siblings, 1 reply; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 19:01 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel, Arend van Spriel, kernel-list
Hi,
[add Arend and Raspberry Pi devs]
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> Add SDIO2 node. On RPi5 it is connected to WiFi chip.
> Add related pin, gpio and regulator definitions and
> add WiFi node. With this and firmware already provided by
> distributions, at least on openSUSE Tumbleweed, this is
> sufficient to make WiFi operational on RPi5 \o/.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 55 +++++++++++++++++++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 13 +++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> index 06e926af16b7..b6bfe0abb774 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> @@ -46,6 +46,20 @@ sd_vcc_reg: sd-vcc-reg {
> gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
> };
>
> + wl_on_reg: wl-on-reg {
> + compatible = "regulator-fixed";
> + regulator-name = "wl-on-regulator";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + pinctrl-0 = <&wl_on_pins>;
> + pinctrl-names = "default";
> +
> + gpio = <&gio 28 GPIO_ACTIVE_HIGH>;
> +
> + startup-delay-us = <150000>;
> + enable-active-high;
> + };
I don't think this GPIO is a regulator from hardware perspective. I
guess it's the same reset pin we have on the older Raspberry Pis. Please
look at bcm283x-rpi-wifi-bt.dtsi for the wifi power sequence.
> +
> pwr-button {
> compatible = "gpio-keys";
>
> @@ -80,6 +94,25 @@ &sdio1 {
> cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
> };
>
> +/* SDIO2 drives the WLAN interface */
> +&sdio2 {
> + pinctrl-0 = <&sdio2_30_pins>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + vmmc-supply = <&wl_on_reg>;
> + sd-uhs-ddr50;
> + non-removable;
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + wifi: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + local-mac-address = [00 00 00 00 00 00];
I think we can drop this?
> + };
> +};
> +
> &pinctrl_aon {
> emmc_aon_cd_pins: emmc-aon-cd-pins {
> function = "sd_card_g";
> @@ -95,9 +128,31 @@ pwr_button_pins: pwr-button-pins {
> bias-pull-up;
> };
>
> + wl_on_pins: wl-on-pins {
> + function = "gpio";
> + pins = "gpio28";
> + };
> +
> emmc_sd_pulls: emmc-sd-pulls {
> pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
> bias-pull-up;
> };
>
> + sdio2_30_pins: sdio2-30-pins {
> + pin-clk {
> + function = "sd2";
> + pins = "gpio30";
> + bias-disable;
> + };
> + pin-cmd {
> + function = "sd2";
> + pins = "gpio31";
> + bias-pull-up;
> + };
> + pins-dat {
> + function = "sd2";
> + pins = "gpio32", "gpio33", "gpio34", "gpio35";
> + bias-pull-up;
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 39d2419ffce2..3c0663dc6712 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -27,6 +27,19 @@ sdio1: mmc@1000fff000 {
> mmc-ddr-3_3v;
> };
>
> + sdio2: mmc@1001100000 {
> + compatible = "brcm,bcm2712-sdhci";
> + reg = <0x10 0x01100000 0x260>,
> + <0x10 0x01100400 0x200>;
> + reg-names = "host", "cfg";
> + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_emmc2>;
> + sdhci-caps-mask = <0x0000C000 0x0>;
> + sdhci-caps = <0x0 0x0>;
> + mmc-ddr-3_3v;
> + status = "disabled";
> + };
> +
> gicv2: interrupt-controller@107fff9000 {
> interrupt-controller;
> #interrupt-cells = <3>;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node
2024-07-31 6:28 ` [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node Ivan T. Ivanov
2024-07-31 22:11 ` Florian Fainelli
2024-08-02 18:49 ` Stefan Wahren
@ 2024-08-02 19:08 ` Stefan Wahren
2024-08-05 9:37 ` Ivan T. Ivanov
2 siblings, 1 reply; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 19:08 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel
Hi Ivan,
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> Add GPIO and related interrupt controller nodes and wire one
> of the lines to power button.
>
Since we enable the GPIO controller here, i think we should provide the
relevant gpio-line-names for the Raspberry Pi 5 board. So gpioinfo works
from the beginning. Doesn't need to be in this patch directly.
Thanks
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA controller node.
2024-07-31 6:28 ` [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA " Ivan T. Ivanov
2024-07-31 22:13 ` Florian Fainelli
@ 2024-08-02 19:12 ` Stefan Wahren
1 sibling, 0 replies; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 19:12 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel
Hi Ivan,
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> On RPi5 device Bluetooth chips is connected to UARTA
> port. Add Bluetooth chips and related pin definitions.
> With this and firmware already provided by distributions,
> at least on openSUSE Tumbleweed, this is sufficient to make
> Bluetooth operational on RPi5 \o/.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 45 +++++++++++++++++++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 11 +++++
> 2 files changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> index b6bfe0abb774..a557cbd8ba17 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> @@ -133,11 +133,39 @@ wl_on_pins: wl-on-pins {
> pins = "gpio28";
> };
>
> + bt_shutdown_pins: bt-shutdown-pins {
> + function = "gpio";
> + pins = "gpio29";
> + };
> +
> emmc_sd_pulls: emmc-sd-pulls {
> pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
> bias-pull-up;
> };
>
> + uarta_24_pins: uarta-24-pins {
> + pin-rts {
> + function = "uart0";
> + pins = "gpio24";
> + bias-disable;
> + };
> + pin-cts {
> + function = "uart0";
> + pins = "gpio25";
> + bias-pull-up;
> + };
> + pin-txd {
> + function = "uart0";
> + pins = "gpio26";
> + bias-disable;
> + };
> + pin-rxd {
> + function = "uart0";
> + pins = "gpio27";
> + bias-pull-up;
> + };
> + };
> +
> sdio2_30_pins: sdio2-30-pins {
> pin-clk {
> function = "sd2";
> @@ -156,3 +184,20 @@ pins-dat {
> };
> };
> };
> +
> +/* uarta communicates with the BT module */
> +&uarta {
> + uart-has-rtscts;
> + auto-flow-control;
> + status = "okay";
> + clock-frequency = <96000000>;
> + pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>;
> + pinctrl-names = "default";
Please add status here
> +
> + bluetooth: bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + max-speed = <3000000>;
> + shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>;
> + local-bd-address = [ 00 00 00 00 00 00 ];
Can we drop this?
Thanks
> + };
> +};
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 3c0663dc6712..e972f94d6828 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -305,6 +305,17 @@ gio: gpio@7d508500 {
> brcm,gpio-direct;
> };
>
> + uarta: serial@7d50c000 {
> + compatible = "brcm,bcm7271-uart";
> + reg = <0x7d50c000 0x20>;
> + reg-names = "uart";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
> + skip-init;
> + status = "disabled";
> + };
> +
> pinctrl_aon: pinctrl@7d510700 {
> compatible = "brcm,bcm2712-aon-pinctrl";
> reg = <0x7d510700 0x20>;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 4/7] arm64: dts: broadcom: bcm2712: Add pin controller nodes
2024-07-31 6:28 ` [PATCH 4/7] arm64: dts: broadcom: bcm2712: Add pin controller nodes Ivan T. Ivanov
@ 2024-08-02 19:16 ` Stefan Wahren
0 siblings, 0 replies; 34+ messages in thread
From: Stefan Wahren @ 2024-08-02 19:16 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> Add pin-control devicetree nodes and used them to
> explicitly define uSD card interface pin configuration.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 20 +++++++++++++++++++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 10 ++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> index b5921437e09f..8a0d20afebfe 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> @@ -53,10 +53,30 @@ &uart0 {
>
> /* SDIO1 is used to drive the SD card */
> &sdio1 {
> + pinctrl-0 = <&emmc_sd_pulls>, <&emmc_aon_cd_pins>;
> + pinctrl-names = "default";
> vqmmc-supply = <&sd_io_1v8_reg>;
> vmmc-supply = <&sd_vcc_reg>;
> bus-width = <4>;
> sd-uhs-sdr50;
> sd-uhs-ddr50;
> sd-uhs-sdr104;
> + cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pinctrl_aon {
> + emmc_aon_cd_pins: emmc-aon-cd-pins {
> + function = "sd_card_g";
> + pins = "aon_gpio5";
> + bias-pull-up;
> + };
> +};
> +
> +&pinctrl {
> +
> + emmc_sd_pulls: emmc-sd-pulls {
> + pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
> + bias-pull-up;
> + };
> +
> };
Please keep the references in alphabetical order (pinctrl comes before
sdio). Except of this:
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 398df13148bd..1099171cd435 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -266,6 +266,16 @@ uart0: serial@7d001000 {
> status = "disabled";
> };
>
> + pinctrl: pinctrl@7d504100 {
> + compatible = "brcm,bcm2712-pinctrl";
> + reg = <0x7d504100 0x30>;
> + };
> +
> + pinctrl_aon: pinctrl@7d510700 {
> + compatible = "brcm,bcm2712-aon-pinctrl";
> + reg = <0x7d510700 0x20>;
> + };
> +
> interrupt-controller@7d517000 {
> compatible = "brcm,bcm7271-l2-intc";
> reg = <0x7d517000 0x10>;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver
2024-07-31 6:28 ` [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver Ivan T. Ivanov
2024-08-02 10:22 ` Phil Elwell
2024-08-02 18:36 ` Stefan Wahren
@ 2024-08-05 9:13 ` Stefan Wahren
2 siblings, 0 replies; 34+ messages in thread
From: Stefan Wahren @ 2024-08-05 9:13 UTC (permalink / raw)
To: Ivan T. Ivanov, linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, andrea.porta, linux-gpio, devicetree,
linux-arm-kernel, Jonathan Bell, Phil Elwell
Hi Ivan,
Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> This driver provide pin muxing and configuration functionality
> for BCM2712 SoC used by RPi5. According to [1] this chips is
> incarnation of chip used in Broadcom STB product line.
>
> [1] https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
>
> Cc: Jonathan Bell <jonathan@raspberrypi.com>
> Cc: Phil Elwell <phil@raspberrypi.com>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> ---
> drivers/pinctrl/bcm/Kconfig | 13 +
> drivers/pinctrl/bcm/Makefile | 1 +
> drivers/pinctrl/bcm/pinctrl-brcmstb.c | 1217 +++++++++++++++++++++++++
> 3 files changed, 1231 insertions(+)
> create mode 100644 drivers/pinctrl/bcm/pinctrl-brcmstb.c
>
> diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
> index 35b51ce4298e..2e1b8d444f58 100644
> --- a/drivers/pinctrl/bcm/Kconfig
> +++ b/drivers/pinctrl/bcm/Kconfig
> @@ -3,6 +3,19 @@
> # Broadcom pinctrl drivers
> #
>
> +config PINCTRL_BRCMSTB
> + tristate "Broadcom STB product line pin controller driver"
> + depends on OF && (ARCH_BRCMSTB || COMPILE_TEST)
> + select PINMUX
> + select PINCONF
> + select GENERIC_PINCONF
> + help
> + This driver provide pin muxing and configuration functionality
> + for Broadcom STB product line chipsets. BCM2712 SoC is one of these
> + chipsets.
> +
> + If M is selected the module will be called pinctrl-brcmstb.
> +
>
this driver should be enabled in arm64/defconfig at the end of the patch
series.
Thanks
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-08-01 14:19 ` Krzysztof Kozlowski
@ 2024-08-05 9:27 ` Ivan T. Ivanov
0 siblings, 0 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-08-05 9:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
wahrenst, andrea.porta, linux-gpio, devicetree, linux-arm-kernel
Hi,
On 08-01 16:19, Krzysztof Kozlowski wrote:
>
> On 01/08/2024 10:38, Ivan T. Ivanov wrote:
> > Hi,
> >
> > On 08-01 10:17, Krzysztof Kozlowski wrote:
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> >>
> >> bcm2712 is Rpi, so not really STB. The name is confusing. Please use
> >> compatible as filename, so:
> >> brcm,bcm2712-pinctrl.yaml
> >
> > According Florian it is:
> >
> > https://lore.kernel.org/lkml/f6601f73-cb22-4ba3-88c5-241be8421fc3@broadcom.com/
>
> OK, title can be like this, no problem, although then please expand what
> "STB" means.
Ok.
>
> Bindings still are supposed to use compatible as filename.
>
IIUC, you suggest to rename compatible string from brcm,bcm2712-pinctrl
to brcm,brcmstb-pinctrl?!
Regards,
Ivan
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node
2024-08-02 19:08 ` Stefan Wahren
@ 2024-08-05 9:37 ` Ivan T. Ivanov
0 siblings, 0 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2024-08-05 9:37 UTC (permalink / raw)
To: Stefan Wahren
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
andrea.porta, linux-gpio, devicetree, linux-arm-kernel
Hi,
On 08-02 21:08, Stefan Wahren wrote:
>
> Hi Ivan,
>
> Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> > Add GPIO and related interrupt controller nodes and wire one
> > of the lines to power button.
> >
> Since we enable the GPIO controller here, i think we should provide the
> relevant gpio-line-names for the Raspberry Pi 5 board. So gpioinfo works
> from the beginning. Doesn't need to be in this patch directly.
>
Sure, I was planning to send this later to not make this patchest too large.
Regards,
Ivan
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-08-02 18:09 ` Stefan Wahren
@ 2024-08-12 16:28 ` Dave Stevenson
2024-08-22 10:54 ` Stefan Wahren
0 siblings, 1 reply; 34+ messages in thread
From: Dave Stevenson @ 2024-08-12 16:28 UTC (permalink / raw)
To: Stefan Wahren
Cc: Ivan T. Ivanov, kernel-list, florian.fainelli, andrea.porta,
conor+dt, krzk+dt, linux-gpio, devicetree, linux-arm-kernel, robh,
linus.walleij
Hi Stefan
Sorry for the delay in responding - I was on holiday last week.
On Fri, 2 Aug 2024 at 19:10, Stefan Wahren <wahrenst@gmx.net> wrote:
>
> Hi,
>
> [add official Raspberry Pi kernel developer list]
>
> Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> > It looks like they are few revisions of this chip which varies
> > by number of pins. Perhaps not all of them are available on the
> > market. Perhaps some of them where early engineering samples,
> > I don't know. I decided to keep all of them just in case.
> The BCM2711 had also some revisions and we avoided successfully multiple
> versions of the RPi 4B DTS. So it would be nice if someone can explain
> if C0 & D0 are available in the market? Otherwise we may end up with
> multiple versions of the RPi 5 DTS.
AFAIK A0 and B0 silicon were never commercialised.
C0 is the current revision in use with Pi5.
D0 will be in devices imminently. CM5 will use it from launch, but
subsequently standard Pi5s will do as well.
In addition to putting in the few fixes that were desired, some
registers and DMA dreqs got shuffled around, hence some drivers will
need additional compatible strings (vc4 certainly does) and other
minor DT tweaks.
Checking our downstream dt files, we have bcm2712d0-rpi-5-b.dts[1]
that includes and patches the original (C0) bcm2712-rpi-5-b.dts[2].
The cleaner option would be to have a common bcm2712-rpi-5-b.dts(i)
and separate bcm2712c0-rpi-5-b.dts bcm2712d0-rpi-5-b.dts which include
the base and add the relevant customisations. Later a
bcm2712d0-rpi-cm5.dts DT should be able to include that same base file
as well.
I'm not quite sure why the GPIO names are redefined in our d0 file -
other than the unused ones using "-" instead of "", they appear
identical.
> I'm missing an explanation in the commit message, what's the difference
> between brcm,bcm2712-pinctrl and brcm,bcm2712-aon-pinctrl?
Two separate instantiations of the same IP block, but they differ in
the number of pins that are associated and the pinmux functions for
each of those pins. AFAIK there is no way from DT to specify those
pinmux function names, so otherwise
/sys/kernel/debug/pinctrl/<node>/pins will give the wrong function
mappings.
> According to the driver brcm,bcm2712-pinctrl is the same as
> brcm,bcm2712c0-pinctrl. So the former is more a fallback?
I'd need to check with Phil (who's on holiday this week) or Dom, but I
believe you are correct that "brcm,bcm2712-pinctrl" is a fallback.
Most likely due to our early DT files not having the c0 designation.
Obviously for mainline that is irrelevant, so dropping the
non-specific compatibles is fine.
I hope that makes some more sense.
Dave
[1] https://github.com/raspberrypi/linux/blob/rpi-6.6.y/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
[2] https://github.com/raspberrypi/linux/blob/rpi-6.6.y/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> Thanks
> >
> > Cc: Andrea della Porta <andrea.porta@suse.com>
> > Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> > ---
> > .../pinctrl/brcm,brcmstb-pinctrl.yaml | 73 +++++++++++++++++++
> > 1 file changed, 73 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> > new file mode 100644
> > index 000000000000..c5afdb49d784
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/brcm,brcmstb-pinctrl.yaml
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Broadcom STB family pin controller
> > +
> > +maintainers:
> > + - Ivan T. Ivanov <iivanov@suse.de>
> > +
> > +description:
> > + Broadcom's STB family memory-mapped pin controller.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - brcm,bcm2712-pinctrl
> > + - brcm,bcm2712-aon-pinctrl
> > + - brcm,bcm2712c0-pinctrl
> > + - brcm,bcm2712c0-aon-pinctrl
> > + - brcm,bcm2712d0-pinctrl
> > + - brcm,bcm2712d0-aon-pinctrl
> > +
> >
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2024-08-12 16:28 ` Dave Stevenson
@ 2024-08-22 10:54 ` Stefan Wahren
0 siblings, 0 replies; 34+ messages in thread
From: Stefan Wahren @ 2024-08-22 10:54 UTC (permalink / raw)
To: Dave Stevenson
Cc: Ivan T. Ivanov, kernel-list, florian.fainelli, andrea.porta,
conor+dt, krzk+dt, linux-gpio, devicetree, linux-arm-kernel, robh,
linus.walleij
Hi Dave,
Am 12.08.24 um 18:28 schrieb Dave Stevenson:
> Hi Stefan
>
> Sorry for the delay in responding - I was on holiday last week.
>
no problem and thanks for the explanations.
>> I'm missing an explanation in the commit message, what's the difference
>> between brcm,bcm2712-pinctrl and brcm,bcm2712-aon-pinctrl?
> Two separate instantiations of the same IP block, but they differ in
> the number of pins that are associated and the pinmux functions for
> each of those pins. AFAIK there is no way from DT to specify those
> pinmux function names, so otherwise
> /sys/kernel/debug/pinctrl/<node>/pins will give the wrong function
> mappings.
Yes, my request is that this or a similar explanation should go to the
commit message, because not all reviewers know the IP block. It would be
great to explain the aon part. Always on?
>> According to the driver brcm,bcm2712-pinctrl is the same as
>> brcm,bcm2712c0-pinctrl. So the former is more a fallback?
> I'd need to check with Phil (who's on holiday this week) or Dom, but I
> believe you are correct that "brcm,bcm2712-pinctrl" is a fallback.
> Most likely due to our early DT files not having the c0 designation.
> Obviously for mainline that is irrelevant, so dropping the
> non-specific compatibles is fine.
I agree.
Regards
>
> I hope that makes some more sense.
>
> Dave
>
> [1] https://github.com/raspberrypi/linux/blob/rpi-6.6.y/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
> [2] https://github.com/raspberrypi/linux/blob/rpi-6.6.y/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
2024-08-02 19:01 ` Stefan Wahren
@ 2025-05-12 13:42 ` Ivan T. Ivanov
0 siblings, 0 replies; 34+ messages in thread
From: Ivan T. Ivanov @ 2025-05-12 13:42 UTC (permalink / raw)
To: Stefan Wahren
Cc: linus.walleij, robh, krzk+dt, conor+dt, florian.fainelli,
andrea.porta, linux-gpio, devicetree, linux-arm-kernel,
Arend van Spriel, kernel-list
Hi,
I am sorry so long delayed answer. Shifting priorities.
On 08-02 21:01, Stefan Wahren wrote:
>
> Hi,
>
> [add Arend and Raspberry Pi devs]
>
> Am 31.07.24 um 08:28 schrieb Ivan T. Ivanov:
> > Add SDIO2 node. On RPi5 it is connected to WiFi chip.
> > Add related pin, gpio and regulator definitions and
> > add WiFi node. With this and firmware already provided by
> > distributions, at least on openSUSE Tumbleweed, this is
> > sufficient to make WiFi operational on RPi5 \o/.
> >
> > Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> > ---
> > .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 55 +++++++++++++++++++
> > arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 13 +++++
> > 2 files changed, 68 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> > index 06e926af16b7..b6bfe0abb774 100644
> > --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> > +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> > @@ -46,6 +46,20 @@ sd_vcc_reg: sd-vcc-reg {
> > gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
> > };
> >
> > + wl_on_reg: wl-on-reg {
> > + compatible = "regulator-fixed";
> > + regulator-name = "wl-on-regulator";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + pinctrl-0 = <&wl_on_pins>;
> > + pinctrl-names = "default";
> > +
> > + gpio = <&gio 28 GPIO_ACTIVE_HIGH>;
> > +
> > + startup-delay-us = <150000>;
> > + enable-active-high;
> > + };
> I don't think this GPIO is a regulator from hardware perspective. I
> guess it's the same reset pin we have on the older Raspberry Pis. Please
> look at bcm283x-rpi-wifi-bt.dtsi for the wifi power sequence.
FWICS, "mmc-pwrseq-simple" is more about proper reset sequence while
here we need power to be applied to the connected device.
And this is not a precedent. Just grep for "vmmc-supply = <&wlan"
> > +
> > pwr-button {
> > compatible = "gpio-keys";
> >
> > @@ -80,6 +94,25 @@ &sdio1 {
> > cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
> > };
> >
> > +/* SDIO2 drives the WLAN interface */
> > +&sdio2 {
> > + pinctrl-0 = <&sdio2_30_pins>;
> > + pinctrl-names = "default";
> > + bus-width = <4>;
> > + vmmc-supply = <&wl_on_reg>;
> > + sd-uhs-ddr50;
> > + non-removable;
> > + status = "okay";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + wifi: wifi@1 {
> > + reg = <1>;
> > + compatible = "brcm,bcm4329-fmac";
> > + local-mac-address = [00 00 00 00 00 00];
> I think we can drop this?
Sure.
Regards,
Ivan
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2025-07-15 18:31 Andrea della Porta
@ 2025-07-15 18:31 ` Andrea della Porta
2025-07-15 19:27 ` Rob Herring (Arm)
0 siblings, 1 reply; 34+ messages in thread
From: Andrea della Porta @ 2025-07-15 18:31 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt
Cc: conor+dt, florian.fainelli, wahrenst, linux-gpio, devicetree,
linux-arm-kernel, Catalin Marinas, Will Deacon, iivanov,
svarbanov, mbrugger, Andrea della Porta
From: "Ivan T. Ivanov" <iivanov@suse.de>
The STB pin controller represents a family whose silicon instances
are found e.g. on BCM2712 SoC.
In particular, on RaspberryPi 5, there are two separate instantiations
of the same IP block which differ in the number of pins that are
associated and the pinmux functions for each of those pins. The
-aon- variant stands for 'Always On'.
Depending on the revision of the BCM2712 (CO or D0), the pin
controller instance has slight differences in the register layout.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
---
This patch is based on linux-next/master
.../pinctrl/brcm,bcm2712c0-pinctrl.yaml | 123 ++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
new file mode 100644
index 000000000000..467a9362dbf8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB family pin controller
+
+maintainers:
+ - Ivan T. Ivanov <iivanov@suse.de>
+ - A. della Porta <andrea.porta@suse.com>
+
+description:
+ Broadcom's STB family of memory-mapped pin controllers.
+ This includes the pin controllers inside the BCM2712 SoC which
+ are instances of the STB family and has two silicon variants,
+ C0 and D0, which differs slightly in terms of registers layout.
+ The -aon- (Always On) variant is the same IP block but differs
+ in the number of pins that are associated and the pinmux functions
+ for each of those pins.
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2712c0-pinctrl
+ - brcm,bcm2712c0-aon-pinctrl
+ - brcm,bcm2712d0-pinctrl
+ - brcm,bcm2712d0-aon-pinctrl
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ '-state$':
+ oneOf:
+ - $ref: '#/$defs/brcmstb-pinctrl-state'
+ - patternProperties:
+ '-pins$':
+ $ref: '#/$defs/brcmstb-pinctrl-state'
+ additionalProperties: false
+
+$defs:
+ brcmstb-pinctrl-state:
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ description:
+ Pin controller client devices use pin configuration subnodes (children
+ and grandchildren) for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode (either this or "groups" must be specified).
+ items:
+ pattern: '^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$'
+
+ function:
+ enum: [ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8,
+ aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm,
+ arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2,
+ bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii,
+ ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c,
+ hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out,
+ ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0,
+ sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e,
+ sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0,
+ te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0,
+ vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1,
+ vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3,
+ vc_uart4 ]
+
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+
+ required:
+ - function
+ - pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ brcm_pinctrl: pinctrl@7d504100 {
+ compatible = "brcm,bcm2712c0-pinctrl";
+ reg = <0x7d504100 0x30>;
+
+ bt-shutdown-default-state {
+ function = "gpio";
+ pins = "gpio29";
+ };
+
+ uarta-default-state {
+ rts-tx-pins {
+ function = "uart0";
+ pins = "gpio24", "gpio26";
+ bias-disable;
+ };
+
+ cts-rx-pins {
+ function = "uart0";
+ pins = "gpio25", "gpio27";
+ bias-pull-up;
+ };
+ };
+ };
--
2.35.3
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller
2025-07-15 18:31 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Andrea della Porta
@ 2025-07-15 19:27 ` Rob Herring (Arm)
0 siblings, 0 replies; 34+ messages in thread
From: Rob Herring (Arm) @ 2025-07-15 19:27 UTC (permalink / raw)
To: Andrea della Porta
Cc: Catalin Marinas, linus.walleij, linux-gpio, Will Deacon,
florian.fainelli, krzk+dt, svarbanov, wahrenst, iivanov, conor+dt,
linux-arm-kernel, mbrugger, devicetree
On Tue, 15 Jul 2025 20:31:38 +0200, Andrea della Porta wrote:
> From: "Ivan T. Ivanov" <iivanov@suse.de>
>
> The STB pin controller represents a family whose silicon instances
> are found e.g. on BCM2712 SoC.
>
> In particular, on RaspberryPi 5, there are two separate instantiations
> of the same IP block which differ in the number of pins that are
> associated and the pinmux functions for each of those pins. The
> -aon- variant stands for 'Always On'.
>
> Depending on the revision of the BCM2712 (CO or D0), the pin
> controller instance has slight differences in the register layout.
>
> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
> Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
> ---
> This patch is based on linux-next/master
>
> .../pinctrl/brcm,bcm2712c0-pinctrl.yaml | 123 ++++++++++++++++++
> 1 file changed, 123 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml: $id: Cannot determine base path from $id, relative path/filename doesn't match actual path or filename
$id: http://devicetree.org/schemas/pinctrl/brcm,brcmstb-pinctrl.yaml
file: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/97c650c9967c0c3381c383dfe68bbe6966912604.1752584387.git.andrea.porta@suse.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2025-07-15 19:27 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-31 6:28 [PATCH 0/7] Add pin control driver for BCM2712 SoC Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Ivan T. Ivanov
2024-08-01 8:17 ` Krzysztof Kozlowski
2024-08-01 8:38 ` Ivan T. Ivanov
2024-08-01 14:19 ` Krzysztof Kozlowski
2024-08-05 9:27 ` Ivan T. Ivanov
2024-08-02 18:09 ` Stefan Wahren
2024-08-12 16:28 ` Dave Stevenson
2024-08-22 10:54 ` Stefan Wahren
2024-07-31 6:28 ` [PATCH 2/7] pinctrl: bcm: Add STB family pin controller driver Ivan T. Ivanov
2024-08-02 10:22 ` Phil Elwell
2024-08-02 18:36 ` Stefan Wahren
2024-08-05 9:13 ` Stefan Wahren
2024-07-31 6:28 ` [PATCH 3/7] arm64: dts: broadcom: Add support for BCM2712 Ivan T. Ivanov
2024-07-31 21:57 ` Florian Fainelli
2024-08-01 6:45 ` Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 4/7] arm64: dts: broadcom: bcm2712: Add pin controller nodes Ivan T. Ivanov
2024-08-02 19:16 ` Stefan Wahren
2024-07-31 6:28 ` [PATCH 5/7] arm64: dts: broadcom: bcm2712: Add one more GPIO node Ivan T. Ivanov
2024-07-31 22:11 ` Florian Fainelli
2024-08-01 7:19 ` Ivan T. Ivanov
2024-08-02 18:49 ` Stefan Wahren
2024-08-02 19:08 ` Stefan Wahren
2024-08-05 9:37 ` Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 6/7] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node Ivan T. Ivanov
2024-08-02 19:01 ` Stefan Wahren
2025-05-12 13:42 ` Ivan T. Ivanov
2024-07-31 6:28 ` [PATCH 7/7] arm64: dts: broadcom: bcm2712: Add UARTA " Ivan T. Ivanov
2024-07-31 22:13 ` Florian Fainelli
2024-08-01 7:50 ` Ivan T. Ivanov
2024-08-02 19:12 ` Stefan Wahren
2024-07-31 14:25 ` [PATCH 0/7] Add pin control driver for BCM2712 SoC Rob Herring (Arm)
-- strict thread matches above, loose matches on Subject: below --
2025-07-15 18:31 Andrea della Porta
2025-07-15 18:31 ` [PATCH 1/7] dt-bindings: pinctrl: Add support for Broadcom STB pin controller Andrea della Porta
2025-07-15 19:27 ` Rob Herring (Arm)
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