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[84.15.189.254]) by smtp.gmail.com with ESMTPSA id pw11-20020a17090720ab00b00a3f963c66a8sm454038ejb.121.2024.02.26.22.58.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Feb 2024 22:58:18 -0800 (PST) Message-ID: <3f629079-6809-4cae-bd4d-8b0ee4860196@gmail.com> Date: Tue, 27 Feb 2024 08:58:16 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] gpio: 74x164: Enable output pins after registers are reset Content-Language: en-US To: Andy Shevchenko Cc: linus.walleij@linaro.org, brgl@bgdev.pl, u.kleine-koenig@pengutronix.de, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240226134656.608559-1-arturas.moskvinas@gmail.com> From: Arturas Moskvinas In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hello, On 2/26/24 16:01, Andy Shevchenko wrote: > On Mon, Feb 26, 2024 at 03:46:56PM +0200, Arturas Moskvinas wrote: >> Move output enabling after chip registers are cleared. > Does this fix anything? If so, maybe elaborate a bit the potential behavioural > changes on the real lines. Chip outputs are enabled[1] before actual reset is performed[2] which might cause pin output value to flip flop if previous pin value was set to 1 in chip. Change fixes that behavior by making sure chip is fully reset before all outputs are enabled. Flip-flop can be noticed when module is removed and inserted again and one of the pins was changed to 1 before removal. 100 microsecond flipping is noticeable on oscilloscope (100khz SPI bus). For a properly reset chip - output is enabled around 100 microseconds (on 100khz SPI bus) later during probing process hence should be irrelevant behavioral change. [1] - https://elixir.bootlin.com/linux/v6.7.4/source/drivers/gpio/gpio-74x164.c#L130 [2] - https://elixir.bootlin.com/linux/v6.7.4/source/drivers/gpio/gpio-74x164.c#L150 Arturas Moskvinas