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[83.9.31.123]) by smtp.gmail.com with ESMTPSA id x28-20020ac25ddc000000b004d863fa8681sm749227lfq.173.2023.04.14.03.57.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Apr 2023 03:57:15 -0700 (PDT) Message-ID: <411c8a57-9c9e-c799-91c4-5338f9d15799@linaro.org> Date: Fri, 14 Apr 2023 12:57:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH V12 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and RDP433 variant To: Devi Priya , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, p.zabel@pengutronix.de, shawnguo@kernel.org, arnd@arndb.de, marcel.ziswiler@toradex.com, dmitry.baryshkov@linaro.org, geert+renesas@glider.be, rafal@milecki.pl, nfraprado@collabora.com, broonie@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: quic_srichara@quicinc.com, quic_gokulsri@quicinc.com, quic_sjaganat@quicinc.com, quic_kathirav@quicinc.com, quic_arajkuma@quicinc.com, quic_anusha@quicinc.com, quic_poovendh@quicinc.com References: <20230410135948.11970-1-quic_devipriy@quicinc.com> <20230410135948.11970-4-quic_devipriy@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 14.04.2023 12:01, Devi Priya wrote: > > > On 4/13/2023 2:16 AM, Konrad Dybcio wrote: >> >> >> On 10.04.2023 15:59, Devi Priya wrote: >>> Add initial device tree support for Qualcomm IPQ9574 SoC and >>> Reference Design Platform(RDP) 433 which is based on IPQ9574 >>> family of SoCs >>> >>> Co-developed-by: Anusha Rao >>> Signed-off-by: Anusha Rao >>> Co-developed-by: Poovendhan Selvaraj >>> Signed-off-by: Poovendhan Selvaraj >>> Signed-off-by: Devi Priya >>> --- >> >>> +    soc: soc@0 { >>> +        compatible = "simple-bus"; >>> +        #address-cells = <1>; >>> +        #size-cells = <1>; >>> +        ranges = <0 0 0 0xffffffff>; >> this is equal to: >> >> ranges; > > Konrad, on updating (ranges = <0 0 0 0xffffffff>; --> ranges;) > we see the below warnings: > arch/arm64/boot/dts/qcom/ipq9574.dtsi:103.3-10: Warning (ranges_format): > /soc@0:ranges: empty "ranges" property but its #address-cells (1) > differs from / (2) > arch/arm64/boot/dts/qcom/ipq9574.dtsi:103.3-10: Warning (ranges_format): /soc@0:ranges: empty "ranges" property but its #size-cells (1) differs > from / (2) > > Looks like, empty ranges property isn't supported if the parent and > child address spaces are non-identical. > Would you suggest to retain the ranges as such? > (ranges = <0 0 0 0xffffffff>;) > > Thanks, > Devi Priya Oh right, you have address/size cells = 2 at the top level. Forget about this change. Konrad >> >> Could you fix that up when applying, Bjorn, should there be >> no other issues? >> >> Reviewed-by: Konrad Dybcio >> > Thank you! >> Konrad >> >>> + >>> +        tlmm: pinctrl@1000000 { >>> +            compatible = "qcom,ipq9574-tlmm"; >>> +            reg = <0x01000000 0x300000>; >>> +            interrupts = ; >>> +            gpio-controller; >>> +            #gpio-cells = <2>; >>> +            gpio-ranges = <&tlmm 0 0 65>; >>> +            interrupt-controller; >>> +            #interrupt-cells = <2>; >>> + >>> +            uart2_pins: uart2-state { >>> +                pins = "gpio34", "gpio35"; >>> +                function = "blsp2_uart"; >>> +                drive-strength = <8>; >>> +                bias-disable; >>> +            }; >>> +        }; >>> + >>> +        gcc: clock-controller@1800000 { >>> +            compatible = "qcom,ipq9574-gcc"; >>> +            reg = <0x01800000 0x80000>; >>> +            clocks = <&xo_board_clk>, >>> +                 <&sleep_clk>, >>> +                 <0>, >>> +                 <0>, >>> +                 <0>, >>> +                 <0>, >>> +                 <0>; >>> +            #clock-cells = <1>; >>> +            #reset-cells = <1>; >>> +            #power-domain-cells = <1>; >>> +        }; >>> + >>> +        sdhc_1: mmc@7804000 { >>> +            compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; >>> +            reg = <0x07804000 0x1000>, <0x07805000 0x1000>; >>> +            reg-names = "hc", "cqhci"; >>> + >>> +            interrupts = , >>> +                     ; >>> +            interrupt-names = "hc_irq", "pwr_irq"; >>> + >>> +            clocks = <&gcc GCC_SDCC1_AHB_CLK>, >>> +                 <&gcc GCC_SDCC1_APPS_CLK>, >>> +                 <&xo_board_clk>; >>> +            clock-names = "iface", "core", "xo"; >>> +            non-removable; >>> +            status = "disabled"; >>> +        }; >>> + >>> +        blsp1_uart2: serial@78b1000 { >>> +            compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; >>> +            reg = <0x078b1000 0x200>; >>> +            interrupts = ; >>> +            clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, >>> +                 <&gcc GCC_BLSP1_AHB_CLK>; >>> +            clock-names = "core", "iface"; >>> +            status = "disabled"; >>> +        }; >>> + >>> +        intc: interrupt-controller@b000000 { >>> +            compatible = "qcom,msm-qgic2"; >>> +            reg = <0x0b000000 0x1000>,  /* GICD */ >>> +                  <0x0b002000 0x2000>,  /* GICC */ >>> +                  <0x0b001000 0x1000>,  /* GICH */ >>> +                  <0x0b004000 0x2000>;  /* GICV */ >>> +            #address-cells = <1>; >>> +            #size-cells = <1>; >>> +            interrupt-controller; >>> +            #interrupt-cells = <3>; >>> +            interrupts = ; >>> +            ranges = <0 0x0b00c000 0x3000>; >>> + >>> +            v2m0: v2m@0 { >>> +                compatible = "arm,gic-v2m-frame"; >>> +                reg = <0x00000000 0xffd>; >>> +                msi-controller; >>> +            }; >>> + >>> +            v2m1: v2m@1000 { >>> +                compatible = "arm,gic-v2m-frame"; >>> +                reg = <0x00001000 0xffd>; >>> +                msi-controller; >>> +            }; >>> + >>> +            v2m2: v2m@2000 { >>> +                compatible = "arm,gic-v2m-frame"; >>> +                reg = <0x00002000 0xffd>; >>> +                msi-controller; >>> +            }; >>> +        }; >>> + >>> +        timer@b120000 { >>> +            compatible = "arm,armv7-timer-mem"; >>> +            reg = <0x0b120000 0x1000>; >>> +            #address-cells = <1>; >>> +            #size-cells = <1>; >>> +            ranges; >>> + >>> +            frame@b120000 { >>> +                reg = <0x0b121000 0x1000>, >>> +                      <0x0b122000 0x1000>; >>> +                frame-number = <0>; >>> +                interrupts = , >>> +                         ; >>> +            }; >>> + >>> +            frame@b123000 { >>> +                reg = <0x0b123000 0x1000>; >>> +                frame-number = <1>; >>> +                interrupts = ; >>> +                status = "disabled"; >>> +            }; >>> + >>> +            frame@b124000 { >>> +                reg = <0x0b124000 0x1000>; >>> +                frame-number = <2>; >>> +                interrupts = ; >>> +                status = "disabled"; >>> +            }; >>> + >>> +            frame@b125000 { >>> +                reg = <0x0b125000 0x1000>; >>> +                frame-number = <3>; >>> +                interrupts = ; >>> +                status = "disabled"; >>> +            }; >>> + >>> +            frame@b126000 { >>> +                reg = <0x0b126000 0x1000>; >>> +                frame-number = <4>; >>> +                interrupts = ; >>> +                status = "disabled"; >>> +            }; >>> + >>> +            frame@b127000 { >>> +                reg = <0x0b127000 0x1000>; >>> +                frame-number = <5>; >>> +                interrupts = ; >>> +                status = "disabled"; >>> +            }; >>> + >>> +            frame@b128000 { >>> +                reg = <0x0b128000 0x1000>; >>> +                frame-number = <6>; >>> +                interrupts = ; >>> +                status = "disabled"; >>> +            }; >>> +        }; >>> +    }; >>> + >>> +    timer { >>> +        compatible = "arm,armv8-timer"; >>> +        interrupts = , >>> +                 , >>> +                 , >>> +                 ; >>> +    }; >>> +};