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[88.1.105.170]) by smtp.gmail.com with ESMTPSA id v6sm29753390wrx.32.2021.03.02.08.53.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Mar 2021 08:53:57 -0800 (PST) Subject: Re: [PATCH 01/12] Documentation: add BCM6328 pincontroller binding documentation To: Linus Walleij Cc: Florian Fainelli , Rob Herring , Jonas Gorski , Necip Fazil Yildiran , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" References: <20210225164216.21124-1-noltari@gmail.com> <20210225164216.21124-2-noltari@gmail.com> From: =?UTF-8?Q?=c3=81lvaro_Fern=c3=a1ndez_Rojas?= Message-ID: <418daebd-b35b-2edc-6f33-591bd97ba1f9@gmail.com> Date: Tue, 2 Mar 2021 17:53:56 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: es-ES Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Linus, I think it's better if we leave the interrupts out for now. It's not critical and it can be added later. Best regards, Álvaro. El 02/03/2021 a las 16:23, Linus Walleij escribió: > On Tue, Mar 2, 2021 at 3:57 PM Linus Walleij wrote: >> On Thu, Feb 25, 2021 at 5:42 PM Álvaro Fernández Rojas >> wrote: >> >>> Add binding documentation for the pincontrol core found in BCM6328 SoCs. >>> >>> Signed-off-by: Álvaro Fernández Rojas >>> Signed-off-by: Jonas Gorski >> (...) >>> + interrupts-extended: >>> + description: >>> + One interrupt per each of the 4 GPIO ports supported by the controller, >>> + sorted by port number ascending order. >>> + minItems: 4 >>> + maxItems: 4 >> >> I don't know if this is advisable, there are different ways >> of specifying interrupts so this may become ambiguous, >> I think Rob will know how/if to do this though. > > After reading the code I conclude this gpiochip is hierarchical so this should > just be dropped, and we only need interrupt-parent assigned. The > driver will know the hardware offsets between the interrupt parent > and the GPIO block, this is generally the case for > hierarchical interrupt controllers. > > Yours, > Linus Walleij >