From: Miao Wang <shankerwangmiao@gmail.com>
To: Linus Walleij <linusw@kernel.org>
Cc: Yinbo Zhu <zhuyinbo@loongson.cn>,
Bartosz Golaszewski <brgl@kernel.org>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
linux-gpio@vger.kernel.org
Subject: Re: [PATCH RFC 3/4] gpio: loongson-64bit: Add shared interrupt support
Date: Fri, 2 Oct 2026 01:47:16 +0800 [thread overview]
Message-ID: <44D04759-C409-4C4C-9FD0-737A8CF9B79A@gmail.com> (raw)
In-Reply-To: <C6A08AB5-069E-4CC6-8CA0-DEF22F369208@gmail.com>
Hi,
> 2026年10月1日 16:59,Miao Wang <shankerwangmiao@gmail.com> 写道:
>
> Hi Linus,
>
> Thanks for your suggestions.
>
>> 2026年10月01日 16:33,Linus Walleij <linusw@kernel.org> 写道:
>>
>> Hi Miao,
>>
>> thanks for your patch!
>>
>> On Fri, Sep 25, 2026 at 6:28 PM Miao Wang via B4 Relay
>> <devnull+shankerwangmiao.gmail.com@kernel.org> wrote:
>>
>>> +struct loongson_gpio_shared_per_parent_irq_data {
>>> + unsigned int parent_index;
>>> + unsigned int parent_irq;
>>> + /*
>>> + * The lock of the irq_desc of the parent irq also protects
>>> + * exclusive/usedby below. It must be taken before
>>> + * lgpio->shared_irq_data->lock.
>>> + */
>>> + struct irq_data *parent_irq_data;
>>> + struct loongson_gpio_chip *lgpio;
>>> +
>>> + /*
>>> + * exclusive: exclusive usage, only one gpio pin can use this parent irq.
>>> + * It will happen in two cases:
>>> + * - The parent irq is used by a gpio pin which is edge triggered, and
>>> + * thus cannot be used by other gpio pins which are mapped to the same
>>> + * parent irq.
>>> + * - The parent irq is used by a gpio pin which is level triggered, and
>>> + * the gpio chip lacks the polarity control register, and thus the
>>> + * interrupt polarity is controlled by the parent irq controller, and
>>> + * thus cannot be used by other gpio pins which are mapped to the
>>> + * same parent irq.
>>> + * When set, the request for other gpio pins which are mapped to this
>>> + * parent irq will be rejected.
>>> + */
>>> + unsigned int exclusive : 1;
>>
>> So use bool exclusive;
>>
>>> + /*
>>> + * usedby: When exclusive is set, these bits indicate the gpio pin which
>>> + * is using this parent irq. When exclusive is cleared, these bits
>>> + * indicate the number of gpio pins which are using this parent irq.
>>> + * When both exclusive and usedby are 0, it means that the parent irq is not
>>> + * used by any gpio pin.
>>> + */
>>> + unsigned int usedby : 31;
>>
>> Is this a bitmap? Then use a bitmap abstraction.
>
> When exclusive is 1, it is a pure number while when exclusive is 0,
> it is a bitmap.
To correct my self, usedby is not a bitmap. When exclusive is 1, it stores the using pin
id, while when exclusive is zero, it is a counter which stores the number of using pins.
Cheers,
Miao Wang
next prev parent reply other threads:[~2026-10-01 17:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 16:28 [PATCH RFC 0/4] gpio: loongson-64bit: add interrupt support for more models Miao Wang via B4 Relay
2026-09-25 16:28 ` [PATCH RFC 1/4] gpio: loongson-64bit: Support for irq controller on 2k2000 and 7a2000 Miao Wang via B4 Relay
2026-09-25 16:28 ` [PATCH RFC 2/4] gpio: loongson-64bit: Generalize interrupt controller initialization Miao Wang via B4 Relay
2026-09-25 16:28 ` [PATCH RFC 3/4] gpio: loongson-64bit: Add shared interrupt support Miao Wang via B4 Relay
2026-10-01 8:33 ` Linus Walleij
2026-10-01 8:59 ` Miao Wang
2026-10-01 11:54 ` Linus Walleij
2026-10-01 17:47 ` Miao Wang [this message]
2026-10-01 19:43 ` Linus Walleij
2026-10-02 4:03 ` Miao Wang
2026-09-25 16:28 ` [PATCH RFC 4/4] gpio: loongson-64bit: remove gpio_to_irq() handler Miao Wang via B4 Relay
2026-09-29 13:01 ` [PATCH RFC 0/4] gpio: loongson-64bit: add interrupt support for more models Bartosz Golaszewski
2026-09-29 13:18 ` Miao Wang
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