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AJvYcCWMacJ2VZNzbnRJg/frNNfaNqvtvXZundkk8SMx/KNvU85AFhmVVDJOe+qGaOT2fWv+aDY6xfJyyjpwarCDLGv7kH0G740ZNLNHKg== X-Gm-Message-State: AOJu0YzcjRPexNNwdxx2FuGvAybFPG+VjF5GotoRpZw10r+8tTZjOiBP 1kw6fkayorvNLEqtTs4zM7/iBUkfq5k3XQl3Dfh5cFwZTQuyxYUpFaDvnmjCYU8= X-Google-Smtp-Source: AGHT+IHkqS3HnQXP1SM4LUXFiNo/Si5rJY65Z+dzTqZYGUmZoPX12HJYXMHMRVy8hlem/Uo5GeZbEw== X-Received: by 2002:a05:6000:1e81:b0:35f:650:e8ff with SMTP id ffacd0b85a97d-35f0650ebb8mr5580030f8f.28.1717998796001; Sun, 09 Jun 2024 22:53:16 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421cc89e055sm25464975e9.13.2024.06.09.22.53.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 09 Jun 2024 22:53:14 -0700 (PDT) Message-ID: <48262d5c-4dde-40c5-991c-f373f24b2018@tuxon.dev> Date: Mon, 10 Jun 2024 08:53:13 +0300 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 06/15] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH Content-Language: en-US To: Prabhakar , Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Claudiu Beznea , Fabrizio Castro , Paul Barker , Lad Prabhakar References: <20240530173857.164073-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240530173857.164073-7-prabhakar.mahadev-lad.rj@bp.renesas.com> From: claudiu beznea In-Reply-To: <20240530173857.164073-7-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 30.05.2024 20:38, Prabhakar wrote: > From: Lad Prabhakar > > On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist, > resulting in invalid register offsets. Ensure that the register offsets > are valid before any read/write operations are performed. If the power > registers are not available, both SD and ETH will be set to '0'. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea # on RZ/G3S > --- > v2->v3 > - Included RB tag > > RFC->v2 > - Update check to != 0 instead of -EINVAL > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 89716e842c63..6e3b1adb95f6 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -2503,8 +2503,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) > rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); > > for (u8 i = 0; i < 2; i++) { > - cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); > - cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); > + if (regs->sd_ch) > + cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); > + if (regs->eth_poc) > + cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); > } > > cache->qspi = readb(pctrl->base + QSPI); > @@ -2535,8 +2537,10 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) > writeb(cache->qspi, pctrl->base + QSPI); > writeb(cache->eth_mode, pctrl->base + ETH_MODE); > for (u8 i = 0; i < 2; i++) { > - writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); > - writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); > + if (regs->sd_ch) > + writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); > + if (regs->eth_poc) > + writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); > } > > rzg2l_pinctrl_pm_setup_pfc(pctrl);