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Sun, 05 Apr 2026 10:43:32 -0700 (PDT) X-Received: by 2002:a17:902:e547:b0:2ae:6092:8d93 with SMTP id d9443c01a7336-2b2818329f3mr106632465ad.28.1775411011488; Sun, 05 Apr 2026 10:43:31 -0700 (PDT) Received: from [192.168.29.179] ([49.43.224.181]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2749cbd07sm104541985ad.72.2026.04.05.10.43.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 05 Apr 2026 10:43:31 -0700 (PDT) Message-ID: <49d6b663-89e8-4cae-854b-08ba4dd9268c@oss.qualcomm.com> Date: Sun, 5 Apr 2026 23:13:24 +0530 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] pinctrl: qcom: add the TLMM driver for the Nord platforms To: Bartosz Golaszewski , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Bartosz Golaszewski , Shawn Guo , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com> <20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com> Content-Language: en-US From: "Maulik Shah (mkshah)" In-Reply-To: <20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: n9VTyi8SYstdFW9VJsWJXVrwolGpdxn3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA1MDE4MCBTYWx0ZWRfX5CmcsRDEUssd ZjNRTl8NIKc79gXV/RB0dPcubkFvyxRz82xheQcK0b84y4okGXBlgnQRfzeRcWsA6Uz78yGXILs JxHUK/tc5zfBXGiPE66fjobvrH9Yvlc/lXxEXWLrD/fJI0W7/mVegY1PxSPuEz78b8Ah1BoQ8sc VHmGaJIvmm1m5kdgOlEBFFfCBs5HcWG4oFrLxu/oOO/Zxm3gL+8GJrSfLYFQZA2eOQYN22EYFTx 9hiK8l/+0zvZbOT0eaGSwo3BzylNMu1jjxqz/SwYxIRe0vUTKncOKIDf1L6QctXnV8C2sqxFvwm JwvjNQnO9UoWP+EzJLxiqjaslEi2heuJQRDUCdyJzhtXUxv+oHMRsFl6567aZBcvVeH5Btt52c4 LeTA8qRfTt4MfF/iQX7G4xDxSieiAWWhRenpjR0acju6T7/O8MTVKpcwNqXA53Luv3b9kHUeBFO 4cTRMFwvg/RP0kmyvWA== X-Proofpoint-GUID: n9VTyi8SYstdFW9VJsWJXVrwolGpdxn3 X-Authority-Analysis: v=2.4 cv=AuzjHe9P c=1 sm=1 tr=0 ts=69d29f45 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=oIx2Y1K4xXJD395LZaDjnw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=mS-AFIv6WIZp_N3KX8YA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-05_06,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604050180 On 4/3/2026 6:57 PM, Bartosz Golaszewski wrote: > Add support for the TLMM controller on the Qualcomm Nord platform. > > Co-developed-by: Shawn Guo > Signed-off-by: Shawn Guo > Signed-off-by: Bartosz Golaszewski > --- > drivers/pinctrl/qcom/Kconfig.msm | 7 + > drivers/pinctrl/qcom/Makefile | 1 + > drivers/pinctrl/qcom/pinctrl-nord.c | 3297 +++++++++++++++++++++++++++++++++++ > 3 files changed, 3305 insertions(+) > > diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm > index 6df6159fa5f89f9f0470e700b4698dc8849ed515..6698e2a50b2f67b1aadb4a840339e769c92f95f8 100644 > --- a/drivers/pinctrl/qcom/Kconfig.msm > +++ b/drivers/pinctrl/qcom/Kconfig.msm > @@ -261,6 +261,13 @@ config PINCTRL_SA8775P > This is the pinctrl, pinmux and pinconf driver for the Qualcomm > TLMM block found on the Qualcomm SA8775P platforms. > > +config PINCTRL_NORD > + tristate "Qualcomm Technologies Inc NORD (SA8797p) pin controller driver" > + depends on ARM64 || COMPILE_TEST > + help > + This is the pinctrl, pinmux and pinconf driver for the Qualcomm > + TLMM block found on the Qualcomm NORD platforms. > + > config PINCTRL_SAR2130P > tristate "Qualcomm Technologies Inc SAR2130P pin controller driver" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile > index a8fd12f90d6e6f8e139097cc0a81d6f178f09000..ba6e9408373ff4327bb0c092f1f30889998503a1 100644 > --- a/drivers/pinctrl/qcom/Makefile > +++ b/drivers/pinctrl/qcom/Makefile > @@ -35,6 +35,7 @@ obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o > obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o > obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o > obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o > +obj-$(CONFIG_PINCTRL_NORD) += pinctrl-nord.o > obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o > obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o > obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o > diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c > new file mode 100644 > index 0000000000000000000000000000000000000000..82e519abaf75771817a0f811c6af80c4f98e93ed > --- /dev/null > +++ b/drivers/pinctrl/qcom/pinctrl-nord.c > @@ -0,0 +1,3297 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. This should be a year-less copyright as per internal guidance. Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > + > +#include "pinctrl-msm.h" > + > +#define REG_SIZE 0x1000 > +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ > + { \ > + .grp = PINCTRL_PINGROUP("gpio" #id, \ > + gpio##id##_pins, \ > + ARRAY_SIZE(gpio##id##_pins)), \ > + .ctl_reg = REG_SIZE * id, \ > + .io_reg = 0x4 + REG_SIZE * id, \ > + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ > + .intr_status_reg = 0xc + REG_SIZE * id, \ > + .intr_target_reg = 0x8 + REG_SIZE * id, \ > + .mux_bit = 2, \ > + .pull_bit = 0, \ > + .drv_bit = 6, \ > + .egpio_enable = 12, \ > + .egpio_present = 11, \ > + .oe_bit = 9, \ > + .in_bit = 0, \ > + .out_bit = 1, \ > + .intr_enable_bit = 0, \ > + .intr_status_bit = 0, \ > + .intr_target_bit = 5, \ Similar to pinctrl-kaanapali.c, Nord platform have these bit positions as, .intr_wakeup_present_bit = 6, .intr_wakeup_enable_bit = 7, .intr_target_bit = 8, > + .intr_target_kpss_val = 3, \ > + .intr_raw_status_bit = 4, \ > + .intr_polarity_bit = 1, \ > + .intr_detection_bit = 2, \ > + .intr_detection_width = 2, \ > + .funcs = (int[]){ \ > + msm_mux_gpio, /* gpio mode */ \ > + msm_mux_##f1, \ > + msm_mux_##f2, \ > + msm_mux_##f3, \ > + msm_mux_##f4, \ > + msm_mux_##f5, \ > + msm_mux_##f6, \ > + msm_mux_##f7, \ > + msm_mux_##f8, \ > + msm_mux_##f9, \ > + msm_mux_##f10, \ > + msm_mux_##f11 /* egpio mode */ \ > + }, \ > + .nfuncs = 12, \ > + } > + > +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ > + { \ > + .grp = PINCTRL_PINGROUP(#pg_name, \ > + pg_name##_pins, \ > + ARRAY_SIZE(pg_name##_pins)), \ > + .ctl_reg = ctl, \ > + .io_reg = 0, \ > + .intr_cfg_reg = 0, \ > + .intr_status_reg = 0, \ > + .intr_target_reg = 0, \ > + .mux_bit = -1, \ > + .pull_bit = pull, \ > + .drv_bit = drv, \ > + .oe_bit = -1, \ > + .in_bit = -1, \ > + .out_bit = -1, \ > + .intr_enable_bit = -1, \ > + .intr_status_bit = -1, \ > + .intr_target_bit = -1, \ > + .intr_raw_status_bit = -1, \ > + .intr_polarity_bit = -1, \ > + .intr_detection_bit = -1, \ > + .intr_detection_width = -1, \ > + } > + Remove unused #define SDC_QDSD_PINGROUP. > +#define UFS_RESET(pg_name, offset) \ > + { \ > + .grp = PINCTRL_PINGROUP(#pg_name, \ > + pg_name##_pins, \ > + ARRAY_SIZE(pg_name##_pins)), \ > + .ctl_reg = offset, \ > + .io_reg = offset + 0x4, \ > + .intr_cfg_reg = 0, \ > + .intr_status_reg = 0, \ > + .intr_target_reg = 0, \ > + .mux_bit = -1, \ > + .pull_bit = 3, \ > + .drv_bit = 0, \ > + .oe_bit = -1, \ > + .in_bit = -1, \ > + .out_bit = 0, \ > + .intr_enable_bit = -1, \ > + .intr_status_bit = -1, \ > + .intr_target_bit = -1, \ > + .intr_raw_status_bit = -1, \ > + .intr_polarity_bit = -1, \ > + .intr_detection_bit = -1, \ > + .intr_detection_width = -1, \ > + } > + > +#define QUP_I3C(qup_mode, qup_offset) \ > + { \ > + .mode = qup_mode, \ > + .offset = qup_offset, \ > + } > + Same, Remove unused #define QUP_I3C. Thanks, Maulik