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Tue, 23 Dec 2025 17:42:34 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16986777472253226495 EX-QQ-RecipientCnt: 15 Date: Tue, 23 Dec 2025 17:42:33 +0800 From: Troy Mitchell To: Yixun Lan , Troy Mitchell Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: Re: [PATCH 2/2] pinctrl: spacemit: support I/O power domain configuration Message-ID: <4D38DBB2D5EA96CC+aUpkCTp00KxEuU_Z@kernel.org> References: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-0-5f1090a487c7@linux.spacemit.com> <20251223-kx-pinctrl-aib-io-pwr-domain-v1-2-5f1090a487c7@linux.spacemit.com> <20251223093228-GYA1986709@gentoo.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251223093228-GYA1986709@gentoo.org> X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: MJXRjF2gqSz5kbJX3NdAPN2/6CaTTJUmCupiFHjPyYDhgUtrCFwD2XN4 6Yr+2Tl6CqHl/DzDChXtL7mWc71iYXJ6+hiIwmz3TRSMlNnlT2CDLpcHSVUhJckGdCxnLXQ z3RMTbF3or3TXwjrzuD407ZSZ3j3cdITlQP5/YHqudPPXGvr8Gtiazk9ZploUSn5+7nr1A3 kRHqPd+JU56/9rdUkZ/k2/YpyawwYgDP315Fbbx4bBEeEJbteAHbBMHoJ8yN3Q+PJJPUGqc UNR0Y4LMKdWNYNOWH/LWJXr5jt637CbupC8HYely/L9+UB3Q9Yl1iwJ/wGBtUnNkJaInHCN DwrNDjGhupkG3jrmmncxChpLyNA0nI8Nbj/4qA+cBD+1aFeiwVxq7wR7+YTeNnCMsJbVh9q krZOmMeAUfu+d1NvulVhB3gdl0lIaBUbveJK9OwknaE5OmL4b5Sc/aezrPKC4Ump3SlANl3 6evIPE12TiKf58uoqfpwqPRGCrfKfFXVtm8zzJYiCH5/s96qdWMZ+B+DGJXQ7a7TFQwOwsd TNRNAVKx/NvXcUl8aqiv0rcrqXZp430K2P4FwwclIm5LbJMfBzXFn3ffYM/nnQTm6cnEJwJ KgroVQwUIjRHueS4XvC61ltb1gj3MN7YicSZl+iZyVI2EJ+AasFvuraoheGv9TxQGM7BvMZ PzqPCW7PyFyrQpH9f5UUpP/uynPZY1JbFK5qdWrDRi98BwrV8kTXC0WapBM87eGx+/8zQjB VIhMmutNcUCQxDWc3DHPbEyYWMU9uq18iRb8BZuN0TahiCx4ZKNUWySPv3uyBmugxUSKwnv ue5UzDXusZktu6IsZ5eEeI6NGvmvSnkMlyayezONRxCAAfcFvpHT64ObWrgNg3bPQhixzYp hNJpZEisCt+cc6RXkdGccdxRnj+jXKQ0kMbHqZX2mnGarSkaILPs/6Rpgk5+nO1cbSKCVtf TNuv0bEiDIf7ZFKHs5GNUUG9CbW21cOTm+7fnWTyed/2HrgVBXA2ET7ZgDeta9kkA4C9+NU LieSP5QXoK0ciQMr8i6FRgFX19V9RZdrcoWt9HtgdykUCaGrk/yuDF5Jfnw30vomjnLVgrh 65xSE6zd0ZN3SbGeiKTHvsfy+xfYp0BukzHCir8hzuHaGiV8HTM1iVDGu3Lo4BOrQ7iEsMt nkIPtgrQgPQExEiy7M5jPFTiPyHBZg0cgfac X-QQ-XMRINFO: Mp0Kj//9VHAxzExpfF+O8yhSrljjwrznVg== X-QQ-RECHKSPAM: 0 On Tue, Dec 23, 2025 at 05:32:28PM +0800, Yixun Lan wrote: > Hi Troy, > > On 17:11 Tue 23 Dec , Troy Mitchell wrote: > > IO domain power control registers are used to configure the operating > > voltage of dual-voltage GPIO banks. By default, these registers are > > configured for 3.3V operation. As a result, even when a GPIO bank is > > externally supplied with 1.8V, the internal logic continues to > > operate in the 3.3V domain, which may lead to functional failures. > > > > This patch adds support for programming the IO domain power control > > registers, allowing dual-voltage GPIO banks to be explicitly configured > > for 1.8V operation when required. > > > > Care must be taken when configuring these registers. If a GPIO bank is > > externally supplied with 3.3V while the corresponding IO power domain > > is configured for 1.8V, external current injection (back-powering) > > may occur, potentially causing damage to the GPIO pin. > > > > Due to these hardware constraints and safety considerations, the IO > > domain power control registers are implemented as secure registers. > > Access to these registers requires unlocking via the AIB Secure Access > > Register (ASAR) in the APBC block before a single read or write > > operation can be performed. > > > > Signed-off-by: Troy Mitchell > > --- > > arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- > > drivers/pinctrl/spacemit/pinctrl-k1.c | 131 +++++++++++++++++++++++++++++++++- > > 2 files changed, 131 insertions(+), 4 deletions(-) > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > > index 7818ca4979b6a7755722919a5958512aa11950ab..23ecb19624f227f3c39de35bf3078379f7a2490e 100644 > > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi > dtsi should go as separated patch, then route to SoC tree OH I forgot that. Thanks. > > > @@ -565,10 +565,12 @@ i2c8: i2c@d401d800 { > > > > pinctrl: pinctrl@d401e000 { > > compatible = "spacemit,k1-pinctrl"; > > - reg = <0x0 0xd401e000 0x0 0x400>; > > + reg = <0x0 0xd401e000 0x0 0x400>, > > + <0x0 0xd401e800 0x0 0x34>; > > clocks = <&syscon_apbc CLK_AIB>, > > <&syscon_apbc CLK_AIB_BUS>; > > clock-names = "func", "bus"; > > + spacemit,apbc = <&syscon_apbc 0x50>; > > }; > > static int spacemit_pinctrl_probe(struct platform_device *pdev) > > { > > + struct device_node *np = pdev->dev.of_node; > > struct device *dev = &pdev->dev; > > struct spacemit_pinctrl *pctrl; > > struct clk *func_clk, *bus_clk; > > @@ -816,6 +927,18 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) > > if (IS_ERR(pctrl->regs)) > > return PTR_ERR(pctrl->regs); > > > > + pctrl->io_pd_reg = devm_platform_ioremap_resource(pdev, 1); > > + if (IS_ERR(pctrl->io_pd_reg)) > > + return PTR_ERR(pctrl->io_pd_reg); > > + > > + pctrl->regmap_apbc = > > + syscon_regmap_lookup_by_phandle_args(np, "spacemit,apbc", 1, > > + &pctrl->regmap_apbc_offset); > Can you simply use syscon_regmap_lookup_by_phandle(), then define > #define APBC_ASFAR 0x50 > #define APBC_ASSAR 0x54 I think it just a minor issue. I will keep it. But if anyone else thinks the same way as Yixun, please let me know. - Troy