* [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC
@ 2024-10-22 15:56 Antonio Borneo
2024-10-22 15:56 ` [PATCH 01/14] pinctrl: stm32: Declare stm32_pmx_get_mode() as static Antonio Borneo
` (14 more replies)
0 siblings, 15 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
This series introduces the support for the new SoC
- STM32MP215,
- STM32MP235,
by adding the support for the new functionalities
- irq affinity,
- Resource Isolation Framework (RIF),
- Reserved (RSVD) pinmux function,
- IO synchronization parameters,
- compile the driver as module.
Some minor code reorganization is also introduced.
Regards,
Antonio Borneo
Amelie Delaunay (2):
pinctrl: stm32: Add stm32mp215 pinctrl support
dt-bindings: pinctrl: stm32: support for stm32mp215 and additional
packages
Antonio Borneo (4):
pinctrl: stm32: Declare stm32_pmx_get_mode() as static
pinctrl: stm32: Rework stm32_pconf_parse_conf()
pinctrl: stm32: Add RIF support for stm32mp257
dt-bindings: pinctrl: stm32: add support for stm32mp235
Cheick Traore (1):
pinctrl: stm32: Manage irq affinity settings
Clément Le Goffic (2):
pinctrl: stm32: Add stm32mp235 pinctrl support
pinctrl: stm32: Add new package to stm32mp257 pinctrl support
Fabien Dessenne (4):
pinctrl: stm32: Handle RSVD pin configuration
dt-bindings: pinctrl: stm32: add RSVD mux function
pinctrl: stm32: Support IO synchronization parameters
dt-bindings: pinctrl: stm32: support IO synchronization parameters
Stephane Danieau (1):
pinctrl: stm32: Allow compile as module for stm32mp257
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 62 +-
arch/arm64/Kconfig.platforms | 1 -
drivers/pinctrl/stm32/Kconfig | 18 +-
drivers/pinctrl/stm32/Makefile | 2 +
drivers/pinctrl/stm32/pinctrl-stm32.c | 365 +++-
drivers/pinctrl/stm32/pinctrl-stm32.h | 27 +-
drivers/pinctrl/stm32/pinctrl-stm32mp215.c | 1807 ++++++++++++++++
drivers/pinctrl/stm32/pinctrl-stm32mp235.c | 1906 +++++++++++++++++
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 305 +--
include/dt-bindings/pinctrl/stm32-pinfunc.h | 4 +
10 files changed, 4326 insertions(+), 171 deletions(-)
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp215.c
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp235.c
base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
--
2.34.1
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/14] pinctrl: stm32: Declare stm32_pmx_get_mode() as static
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 02/14] pinctrl: stm32: Manage irq affinity settings Antonio Borneo
` (13 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
The commit acaa037970f6 ("pinctrl: stm32: Implement .get_direction
gpio_chip callback") exported the function stm32_pmx_get_mode()
and the struct stm32_gpio_bank, but these were never used outside
the file that defines them.
Declare the function as static, drop it from the include file and
drop also the struct, not anymore visible outside the file.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 5 +++--
drivers/pinctrl/stm32/pinctrl-stm32.h | 4 ----
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index a8673739871d8..fc767965d91c6 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -121,6 +121,8 @@ struct stm32_pinctrl {
spinlock_t irqmux_lock;
};
+static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
+
static inline int stm32_gpio_pin(int gpio)
{
return gpio % STM32_GPIO_PINS_PER_BANK;
@@ -794,8 +796,7 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
return err;
}
-void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
- u32 *alt)
+static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt)
{
u32 val;
int alt_shift = (pin % 8) * 4;
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 5e5de92ddd58c..8790fef2d58a2 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -65,11 +65,7 @@ struct stm32_pinctrl_match_data {
bool secure_control;
};
-struct stm32_gpio_bank;
-
int stm32_pctl_probe(struct platform_device *pdev);
-void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
- int pin, u32 *mode, u32 *alt);
int stm32_pinctrl_suspend(struct device *dev);
int stm32_pinctrl_resume(struct device *dev);
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/14] pinctrl: stm32: Manage irq affinity settings
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
2024-10-22 15:56 ` [PATCH 01/14] pinctrl: stm32: Declare stm32_pmx_get_mode() as static Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 03/14] pinctrl: stm32: Handle RSVD pin configuration Antonio Borneo
` (12 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Cheick Traore <cheick.traore@foss.st.com>
Trying to set the affinity of the interrupts associated to stm32
pinctrl results in a write error.
Fill struct irq_chip::irq_set_affinity to use the default helper
function.
Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index fc767965d91c6..30fa39688a8c0 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -409,6 +409,7 @@ static struct irq_chip stm32_gpio_irq_chip = {
.irq_set_wake = irq_chip_set_wake_parent,
.irq_request_resources = stm32_gpio_irq_request_resources,
.irq_release_resources = stm32_gpio_irq_release_resources,
+ .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
};
static int stm32_gpio_domain_translate(struct irq_domain *d,
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/14] pinctrl: stm32: Handle RSVD pin configuration
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
2024-10-22 15:56 ` [PATCH 01/14] pinctrl: stm32: Declare stm32_pmx_get_mode() as static Antonio Borneo
2024-10-22 15:56 ` [PATCH 02/14] pinctrl: stm32: Manage irq affinity settings Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function Antonio Borneo
` (11 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Fabien Dessenne <fabien.dessenne@foss.st.com>
When a pin is assigned to a coprocessor not running Linux, the pin
should be flagged in the DT as reserved and not usable by Linux.
Add pin configuration RSVD (Reserved) and instrument the driver to
not update the mux setting.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 9 +++++++++
drivers/pinctrl/stm32/pinctrl-stm32.h | 3 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 30fa39688a8c0..cb7929feb6a0a 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -76,6 +76,7 @@ static const char * const stm32_gpio_functions[] = {
"af8", "af9", "af10",
"af11", "af12", "af13",
"af14", "af15", "analog",
+ "reserved",
};
struct stm32_pinctrl_group {
@@ -540,6 +541,9 @@ static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
if (pin->pin.number != pin_num)
continue;
+ if (fnum == STM32_PIN_RSVD)
+ return true;
+
for (k = 0; k < STM32_CONFIG_NUM; k++) {
if (func->num == fnum)
return true;
@@ -839,6 +843,11 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
}
+ if (function == STM32_PIN_RSVD) {
+ dev_dbg(pctl->dev, "Reserved pins, skipping HW update.\n");
+ return 0;
+ }
+
bank = gpiochip_get_data(range->gc);
pin = stm32_gpio_pin(g->pin);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 8790fef2d58a2..a5f62fb271442 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -17,7 +17,8 @@
#define STM32_PIN_GPIO 0
#define STM32_PIN_AF(x) ((x) + 1)
#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1)
-#define STM32_CONFIG_NUM (STM32_PIN_ANALOG + 1)
+#define STM32_PIN_RSVD (STM32_PIN_ANALOG + 1)
+#define STM32_CONFIG_NUM (STM32_PIN_RSVD + 1)
/* package information */
#define STM32MP_PKG_AA BIT(0)
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (2 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 03/14] pinctrl: stm32: Handle RSVD pin configuration Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-23 8:46 ` Krzysztof Kozlowski
2024-10-23 8:47 ` Krzysztof Kozlowski
2024-10-22 15:56 ` [PATCH 05/14] pinctrl: stm32: Rework stm32_pconf_parse_conf() Antonio Borneo
` (10 subsequent siblings)
14 siblings, 2 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Fabien Dessenne <fabien.dessenne@foss.st.com>
Document the RSVD (Reserved) mux function, used to reserve pins
for a coprocessor not running Linux.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
.../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 8 ++++++++
include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index a28d77748095a..5d17d6487ae9c 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -160,9 +160,13 @@ patternProperties:
* ...
* 16 : Alternate Function 15
* 17 : Analog
+ * 18 : Reserved
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
+ Setting the pinmux's function to the Reserved (RSVD) value is used to inform
+ the driver that it shall not apply the mux setting. This can be used to
+ reserve some pins, for example to a co-processor not running Linux.
Some examples of using macro:
/* GPIO A9 set as alternate function 2 */
... {
@@ -176,6 +180,10 @@ patternProperties:
... {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
+ /* GPIO A9 reserved for co-processor */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, RSVD)>;
+ };
bias-disable:
type: boolean
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index 28ad0235086a6..af3fd388329a0 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -26,6 +26,7 @@
#define AF14 0xf
#define AF15 0x10
#define ANALOG 0x11
+#define RSVD 0x12
/* define Pins number*/
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/14] pinctrl: stm32: Rework stm32_pconf_parse_conf()
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (3 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 06/14] pinctrl: stm32: Support IO synchronization parameters Antonio Borneo
` (9 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
Reduce the number of parameters of the function by moving inside
the decoding of the field 'config'.
While there:
- change the type of 'param' to 'unsigned int' to handle the extra
values not in 'enum pin_config_param';
- change the type of 'arg' to 'u32' to avoid additional conversions
and align to 'u32' the corresponding param of __stm32_gpio_set().
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index cb7929feb6a0a..b387f6caaf3f0 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -197,7 +197,7 @@ static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
/* GPIO functions */
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
- unsigned offset, int value)
+ unsigned int offset, u32 value)
{
stm32_gpio_backup_value(bank, offset, value);
@@ -1072,10 +1072,11 @@ static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
}
static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
- unsigned int pin, enum pin_config_param param,
- enum pin_config_param arg)
+ unsigned int pin, unsigned long config)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int param = pinconf_to_config_param(config);
+ u32 arg = pinconf_to_config_argument(config);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset, ret = 0;
@@ -1144,9 +1145,7 @@ static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
for (i = 0; i < num_configs; i++) {
mutex_lock(&pctldev->mutex);
- ret = stm32_pconf_parse_conf(pctldev, g->pin,
- pinconf_to_config_param(configs[i]),
- pinconf_to_config_argument(configs[i]));
+ ret = stm32_pconf_parse_conf(pctldev, g->pin, configs[i]);
mutex_unlock(&pctldev->mutex);
if (ret < 0)
return ret;
@@ -1163,9 +1162,7 @@ static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
int i, ret;
for (i = 0; i < num_configs; i++) {
- ret = stm32_pconf_parse_conf(pctldev, pin,
- pinconf_to_config_param(configs[i]),
- pinconf_to_config_argument(configs[i]));
+ ret = stm32_pconf_parse_conf(pctldev, pin, configs[i]);
if (ret < 0)
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/14] pinctrl: stm32: Support IO synchronization parameters
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (4 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 05/14] pinctrl: stm32: Rework stm32_pconf_parse_conf() Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 07/14] dt-bindings: pinctrl: stm32: support " Antonio Borneo
` (8 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Fabien Dessenne <fabien.dessenne@foss.st.com>
Support the following IO synchronization parameters:
- Delay (in ns)
- Delay path (input / output)
- Clock edge (single / double edge)
- Clock inversion
- Retiming
These settings allow a fine tuning of the high speed interface signals.
Update the debugfs pinconf-pins entry so it shows these parameters if one
of them is set.
Enable this feature for the stm32mp257 SoC.
Co-developed-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 207 +++++++++++++++++++++
drivers/pinctrl/stm32/pinctrl-stm32.h | 1 +
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 2 +
3 files changed, 210 insertions(+)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index b387f6caaf3f0..5b9c637ca0c93 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -46,6 +46,13 @@
#define STM32_GPIO_AFRL 0x20
#define STM32_GPIO_AFRH 0x24
#define STM32_GPIO_SECCFGR 0x30
+#define STM32_GPIO_DELAYRL 0x40
+#define STM32_GPIO_ADVCFGRL 0x48
+
+#define STM32_GPIO_ADVCFGR_DLYPATH_POS 0
+#define STM32_GPIO_ADVCFGR_DE_POS 1
+#define STM32_GPIO_ADVCFGR_INVCLK_POS 2
+#define STM32_GPIO_ADVCFGR_RET_POS 3
/* custom bitfield to backup pin status */
#define STM32_GPIO_BKP_MODE_SHIFT 0
@@ -58,12 +65,23 @@
#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
#define STM32_GPIO_BKP_TYPE 10
#define STM32_GPIO_BKP_VAL 11
+#define STM32_GPIO_BKP_ADVCFG_SHIFT 12
+#define STM32_GPIO_BKP_ADVCFG_MASK GENMASK(15, 12)
+#define STM32_GPIO_BKP_DELAY_SHIFT 16
+#define STM32_GPIO_BKP_DELAY_MASK GENMASK(19, 16)
#define STM32_GPIO_PINS_PER_BANK 16
#define STM32_GPIO_IRQ_LINE 16
#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
+/* Vendor specific pin configurations */
+#define STM32_GPIO_PIN_CONFIG_DELAY_PATH (PIN_CONFIG_END + 1)
+#define STM32_GPIO_PIN_CONFIG_CLK_EDGE (PIN_CONFIG_END + 2)
+#define STM32_GPIO_PIN_CONFIG_CLK_TYPE (PIN_CONFIG_END + 3)
+#define STM32_GPIO_PIN_CONFIG_RETIME (PIN_CONFIG_END + 4)
+#define STM32_GPIO_PIN_CONFIG_DELAY (PIN_CONFIG_END + 5)
+
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
@@ -79,6 +97,14 @@ static const char * const stm32_gpio_functions[] = {
"reserved",
};
+static const struct pinconf_generic_params stm32_gpio_bindings[] = {
+ {"st,io-delay-path", STM32_GPIO_PIN_CONFIG_DELAY_PATH, 0},
+ {"st,io-clk-edge", STM32_GPIO_PIN_CONFIG_CLK_EDGE, 0},
+ {"st,io-clk-type", STM32_GPIO_PIN_CONFIG_CLK_TYPE, 0},
+ {"st,io-retime", STM32_GPIO_PIN_CONFIG_RETIME, 0},
+ {"st,io-delay", STM32_GPIO_PIN_CONFIG_DELAY, 0},
+};
+
struct stm32_pinctrl_group {
const char *name;
unsigned long config;
@@ -99,6 +125,7 @@ struct stm32_gpio_bank {
u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
bool secure_control;
+ bool io_sync_control;
};
struct stm32_pinctrl {
@@ -194,6 +221,18 @@ static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
}
+static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 bpos, u32 bval)
+{
+ bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_ADVCFG_SHIFT + bpos);
+ bank->pin_backup[offset] |= bval << (STM32_GPIO_BKP_ADVCFG_SHIFT + bpos);
+}
+
+static void stm32_gpio_backup_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay)
+{
+ bank->pin_backup[offset] &= ~STM32_GPIO_BKP_DELAY_MASK;
+ bank->pin_backup[offset] |= delay << STM32_GPIO_BKP_DELAY_SHIFT;
+}
+
/* GPIO functions */
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
@@ -1051,6 +1090,106 @@ static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
return (val >> (offset * 2));
}
+static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 bpos, u32 bval)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
+ int advcfgr_bit = bpos + (offset % 8) * 4;
+ unsigned long flags;
+ int err = 0;
+ u32 val;
+
+ if (!bank->io_sync_control)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&bank->lock, flags);
+
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+ }
+
+ val = readl_relaxed(bank->base + advcfgr_offset);
+ val &= ~BIT(advcfgr_bit);
+ val |= bval << advcfgr_bit;
+ writel_relaxed(val, bank->base + advcfgr_offset);
+
+ if (pctl->hwlock)
+ hwspin_unlock_in_atomic(pctl->hwlock);
+
+ stm32_gpio_backup_advcfg(bank, offset, bpos, bval);
+
+unlock:
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ return err;
+}
+
+static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 bpos)
+{
+ int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
+ int advcfgr_bit = bpos + (offset % 8) * 4;
+ u32 val;
+
+ val = readl_relaxed(bank->base + advcfgr_offset);
+ val &= BIT(advcfgr_bit);
+
+ return val >> advcfgr_bit;
+}
+
+static int stm32_pconf_set_delay(struct stm32_gpio_bank *bank, int offset, u32 delay)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
+ int delay_shift = (offset % 8) * 4;
+ unsigned long flags;
+ int err = 0;
+ u32 val;
+
+ if (!bank->io_sync_control)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&bank->lock, flags);
+
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+ }
+
+ val = readl_relaxed(bank->base + delay_offset);
+ val &= ~GENMASK(delay_shift + 3, delay_shift);
+ val |= (delay << delay_shift);
+ writel_relaxed(val, bank->base + delay_offset);
+
+ if (pctl->hwlock)
+ hwspin_unlock_in_atomic(pctl->hwlock);
+
+ stm32_gpio_backup_delay(bank, offset, delay);
+
+unlock:
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ return err;
+}
+
+static u32 stm32_pconf_get_delay(struct stm32_gpio_bank *bank, int offset)
+{
+ int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
+ int delay_shift = (offset % 8) * 4;
+ u32 val;
+
+ val = readl_relaxed(bank->base + delay_offset);
+ val &= GENMASK(delay_shift + 3, delay_shift);
+
+ return val >> delay_shift;
+}
+
static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
unsigned int offset, bool dir)
{
@@ -1118,6 +1257,21 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
__stm32_gpio_set(bank, offset, arg);
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
+ case STM32_GPIO_PIN_CONFIG_DELAY_PATH:
+ ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_POS, arg);
+ break;
+ case STM32_GPIO_PIN_CONFIG_CLK_EDGE:
+ ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DE_POS, arg);
+ break;
+ case STM32_GPIO_PIN_CONFIG_CLK_TYPE:
+ ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_INVCLK_POS, arg);
+ break;
+ case STM32_GPIO_PIN_CONFIG_RETIME:
+ ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_RET_POS, arg);
+ break;
+ case STM32_GPIO_PIN_CONFIG_DELAY:
+ ret = stm32_pconf_set_delay(bank, offset, arg);
+ break;
default:
ret = -ENOTSUPP;
}
@@ -1260,6 +1414,22 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
case 3:
break;
}
+
+ if (bank->io_sync_control) {
+ u32 retime, clk_type, clk_edge, delay_path, delay;
+
+ retime = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_RET_POS);
+ clk_type = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_INVCLK_POS);
+ clk_edge = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DE_POS);
+ delay_path = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_POS);
+ delay = stm32_pconf_get_delay(bank, offset);
+
+ if (retime || clk_type || clk_edge || delay_path || delay)
+ seq_printf(s, " - Retime:%d InvClk:%d DblEdge:%d DelayIn:%d",
+ retime, clk_type, clk_edge, delay_path);
+ if (delay)
+ seq_printf(s, " - Delay: %d (%d ps)", delay, delay * 250);
+ }
}
static const struct pinconf_ops stm32_pconf_ops = {
@@ -1358,6 +1528,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
bank->bank_nr = bank_nr;
bank->bank_ioport_nr = bank_ioport_nr;
bank->secure_control = pctl->match_data->secure_control;
+ bank->io_sync_control = pctl->match_data->io_sync_control;
spin_lock_init(&bank->lock);
if (pctl->domain) {
@@ -1604,6 +1775,8 @@ int stm32_pctl_probe(struct platform_device *pdev)
pctl->pctl_desc.confops = &stm32_pconf_ops;
pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
pctl->pctl_desc.pmxops = &stm32_pmx_ops;
+ pctl->pctl_desc.num_custom_params = ARRAY_SIZE(stm32_gpio_bindings);
+ pctl->pctl_desc.custom_params = stm32_gpio_bindings;
pctl->dev = &pdev->dev;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
@@ -1663,6 +1836,16 @@ int stm32_pctl_probe(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused stm32_pinctrl_restore_advcfgr(struct stm32_gpio_bank *bank,
+ int offset, u32 bpos)
+{
+ u32 val;
+
+ val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_ADVCFG_SHIFT + bpos);
+ val >>= (STM32_GPIO_BKP_ADVCFG_SHIFT + bpos);
+ return stm32_pconf_set_advcfgr(bank, offset, bpos, val);
+}
+
static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
struct stm32_pinctrl *pctl, u32 pin)
{
@@ -1720,6 +1903,30 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
if (ret)
return ret;
+ if (bank->io_sync_control) {
+ ret = stm32_pinctrl_restore_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_POS);
+ if (ret)
+ return ret;
+
+ ret = stm32_pinctrl_restore_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DE_POS);
+ if (ret)
+ return ret;
+
+ ret = stm32_pinctrl_restore_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_INVCLK_POS);
+ if (ret)
+ return ret;
+
+ ret = stm32_pinctrl_restore_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_RET_POS);
+ if (ret)
+ return ret;
+
+ val = bank->pin_backup[offset] & STM32_GPIO_BKP_DELAY_MASK;
+ val >>= STM32_GPIO_BKP_DELAY_SHIFT;
+ ret = stm32_pconf_set_delay(bank, offset, val);
+ if (ret)
+ return ret;
+ }
+
if (pin_is_irq)
regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index a5f62fb271442..9b319036f206d 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -64,6 +64,7 @@ struct stm32_pinctrl_match_data {
const struct stm32_desc_pin *pins;
const unsigned int npins;
bool secure_control;
+ bool io_sync_control;
};
int stm32_pctl_probe(struct platform_device *pdev);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
index 23aebd4695e99..293b7acd82a3e 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
@@ -2542,11 +2542,13 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
static struct stm32_pinctrl_match_data stm32mp257_match_data = {
.pins = stm32mp257_pins,
.npins = ARRAY_SIZE(stm32mp257_pins),
+ .io_sync_control = true,
};
static struct stm32_pinctrl_match_data stm32mp257_z_match_data = {
.pins = stm32mp257_z_pins,
.npins = ARRAY_SIZE(stm32mp257_z_pins),
+ .io_sync_control = true,
};
static const struct of_device_id stm32mp257_pctrl_match[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/14] dt-bindings: pinctrl: stm32: support IO synchronization parameters
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (5 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 06/14] pinctrl: stm32: Support IO synchronization parameters Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-23 8:49 ` Krzysztof Kozlowski
2024-10-24 22:38 ` Linus Walleij
2024-10-22 15:56 ` [PATCH 08/14] pinctrl: stm32: Add RIF support for stm32mp257 Antonio Borneo
` (7 subsequent siblings)
14 siblings, 2 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Fabien Dessenne <fabien.dessenne@foss.st.com>
Support the following IO synchronization parameters:
- Delay (in ns)
- Delay path (input / output)
- Clock edge (single / double edge)
- Clock inversion
- Retiming
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index 5d17d6487ae9c..9a7ecfea6eb5b 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -207,6 +207,54 @@ patternProperties:
3: High speed
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
+ st,io-delay-path:
+ description: |
+ IO synchronization delay path location
+ 0: Delay switched into the output path
+ 1: Delay switched into the input path
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ st,io-clk-edge:
+ description: |
+ IO synchronization clock edge
+ 0: Data single-edge (changing on rising or falling clock edge)
+ 1: Data double-edge (changing on both clock edges)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ st,io-clk-type:
+ description: |
+ IO synchronization clock inversion
+ 0: IO clocks not inverted. Data retimed to rising clock edge
+ 1: IO clocks inverted. Data retimed to falling clock edge
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ st,io-retime:
+ description: |
+ IO synchronization data retime
+ 0: Data not synchronized or retimed on clock edges
+ 1: Data retimed to either rising or falling clock edge
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ st,io-delay:
+ description: |
+ IO synchronization delay applied to the input or output path
+ 0: No delay
+ 1: Delay 0.30 ns
+ 2: Delay 0.50 ns
+ 3: Delay 0.75 ns
+ 4: Delay 1.00 ns
+ 5: Delay 1.25 ns
+ 6: Delay 1.50 ns
+ 7: Delay 1.75 ns
+ 8: Delay 2.00 ns
+ 9: Delay 2.25 ns
+ 10: Delay 2.50 ns
+ 11: Delay 2.75 ns
+ 12: Delay 3.00 ns
+ 13: Delay 3.25 ns
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 13
required:
- pinmux
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/14] pinctrl: stm32: Add RIF support for stm32mp257
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (6 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 07/14] dt-bindings: pinctrl: stm32: support " Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 09/14] pinctrl: stm32: Allow compile as module " Antonio Borneo
` (6 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
On SoC stm32mp257, GPIO supports security and isolation compliant
with the Resource Isolation Framework (RIF). Each GPIO line can be
assigned to different security and compartment domains.
Add the generic code to handle the RIF configuration set by the
secure world and initialize the GPIO valid mask accordingly.
Enable the RIF support for stm32mp257.
Co-developed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 121 ++++++++++++++++++++-
drivers/pinctrl/stm32/pinctrl-stm32.h | 1 +
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 4 +
3 files changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 5b9c637ca0c93..b6e7e34508592 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -6,6 +6,7 @@
*
* Heavily based on Mediatek's pinctrl driver
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/hwspinlock.h>
@@ -35,6 +36,8 @@
#include "../pinctrl-utils.h"
#include "pinctrl-stm32.h"
+#define STM32_GPIO_CID1 1
+
#define STM32_GPIO_MODER 0x00
#define STM32_GPIO_TYPER 0x04
#define STM32_GPIO_SPEEDR 0x08
@@ -48,12 +51,22 @@
#define STM32_GPIO_SECCFGR 0x30
#define STM32_GPIO_DELAYRL 0x40
#define STM32_GPIO_ADVCFGRL 0x48
+#define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x)))
+#define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x)))
#define STM32_GPIO_ADVCFGR_DLYPATH_POS 0
#define STM32_GPIO_ADVCFGR_DE_POS 1
#define STM32_GPIO_ADVCFGR_INVCLK_POS 2
#define STM32_GPIO_ADVCFGR_RET_POS 3
+#define STM32_GPIO_CIDCFGR_CFEN BIT(0)
+#define STM32_GPIO_CIDCFGR_SEMEN BIT(1)
+#define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4)
+#define STM32_GPIO_CIDCFGR_SEMWL_CID1 BIT(16 + STM32_GPIO_CID1)
+
+#define STM32_GPIO_SEMCR_SEM_MUTEX BIT(0)
+#define STM32_GPIO_SEMCR_SEMCID_MASK GENMASK(5, 4)
+
/* custom bitfield to backup pin status */
#define STM32_GPIO_BKP_MODE_SHIFT 0
#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
@@ -126,6 +139,7 @@ struct stm32_gpio_bank {
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
bool secure_control;
bool io_sync_control;
+ bool rif_control;
};
struct stm32_pinctrl {
@@ -233,6 +247,80 @@ static void stm32_gpio_backup_delay(struct stm32_gpio_bank *bank, u32 offset, u3
bank->pin_backup[offset] |= delay << STM32_GPIO_BKP_DELAY_SHIFT;
}
+/* RIF functions */
+
+static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
+{
+ u32 cid;
+
+ cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
+
+ if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
+ return true;
+
+ if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
+ if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+ }
+
+ if (cid & STM32_GPIO_CIDCFGR_SEMWL_CID1)
+ return true;
+
+ return false;
+}
+
+static bool stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
+{
+ u32 cid, sem;
+
+ cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
+
+ if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
+ return true;
+
+ if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
+ if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+ }
+
+ if (!(cid & STM32_GPIO_CIDCFGR_SEMWL_CID1))
+ return false;
+
+ sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
+ if (sem & STM32_GPIO_SEMCR_SEM_MUTEX) {
+ if (FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+ }
+
+ writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));
+
+ sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
+ if (sem & STM32_GPIO_SEMCR_SEM_MUTEX &&
+ FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+}
+
+static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
+{
+ u32 cid;
+
+ cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
+
+ if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
+ return;
+
+ if (cid & STM32_GPIO_CIDCFGR_SEMEN)
+ writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));
+}
+
/* GPIO functions */
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
@@ -259,9 +347,26 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
return -EINVAL;
}
+ if (bank->rif_control) {
+ if (!stm32_gpio_rif_acquire_semaphore(bank, offset)) {
+ dev_err(pctl->dev, "pin %d not available.\n", pin);
+ return -EINVAL;
+ }
+ }
+
return pinctrl_gpio_request(chip, offset);
}
+static void stm32_gpio_free(struct gpio_chip *chip, unsigned int offset)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+
+ pinctrl_gpio_free(chip, offset);
+
+ if (bank->rif_control)
+ stm32_gpio_rif_release_semaphore(bank, offset);
+}
+
static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
@@ -342,12 +447,25 @@ static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
}
}
+ if (bank->rif_control) {
+ for (i = 0; i < ngpios; i++) {
+ if (!test_bit(i, valid_mask))
+ continue;
+
+ if (stm32_gpio_rif_valid(bank, i))
+ continue;
+
+ dev_dbg(pctl->dev, "RIF semaphore ownership conflict, GPIO %u", i);
+ clear_bit(i, valid_mask);
+ }
+ }
+
return 0;
}
static const struct gpio_chip stm32_gpio_template = {
.request = stm32_gpio_request,
- .free = pinctrl_gpio_free,
+ .free = stm32_gpio_free,
.get = stm32_gpio_get,
.set = stm32_gpio_set,
.direction_input = pinctrl_gpio_direction_input,
@@ -1529,6 +1647,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
bank->bank_ioport_nr = bank_ioport_nr;
bank->secure_control = pctl->match_data->secure_control;
bank->io_sync_control = pctl->match_data->io_sync_control;
+ bank->rif_control = pctl->match_data->rif_control;
spin_lock_init(&bank->lock);
if (pctl->domain) {
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 9b319036f206d..b8caebc55cfc5 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -65,6 +65,7 @@ struct stm32_pinctrl_match_data {
const unsigned int npins;
bool secure_control;
bool io_sync_control;
+ bool rif_control;
};
int stm32_pctl_probe(struct platform_device *pdev);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
index 293b7acd82a3e..a374918030788 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
@@ -2543,12 +2543,16 @@ static struct stm32_pinctrl_match_data stm32mp257_match_data = {
.pins = stm32mp257_pins,
.npins = ARRAY_SIZE(stm32mp257_pins),
.io_sync_control = true,
+ .secure_control = true,
+ .rif_control = true,
};
static struct stm32_pinctrl_match_data stm32mp257_z_match_data = {
.pins = stm32mp257_z_pins,
.npins = ARRAY_SIZE(stm32mp257_z_pins),
.io_sync_control = true,
+ .secure_control = true,
+ .rif_control = true,
};
static const struct of_device_id stm32mp257_pctrl_match[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/14] pinctrl: stm32: Allow compile as module for stm32mp257
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (7 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 08/14] pinctrl: stm32: Add RIF support for stm32mp257 Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 10/14] pinctrl: stm32: Add stm32mp215 pinctrl support Antonio Borneo
` (5 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Stephane Danieau <stephane.danieau@foss.st.com>
Add ability to build pinctrl for stm32mp257 as a kernel module.
Add kernel-doc to the exported symbols.
Drop the Kconfig symbol MACH_STM32MP25, as it has never been
defined.
Signed-off-by: Stephane Danieau <stephane.danieau@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
arch/arm64/Kconfig.platforms | 1 -
drivers/pinctrl/stm32/Kconfig | 6 +++---
drivers/pinctrl/stm32/pinctrl-stm32.c | 7 +++++++
drivers/pinctrl/stm32/pinctrl-stm32.h | 14 ++++++++++++++
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 11 ++++++-----
5 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6c6d11536b42e..ab77cc49b4ed7 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -308,7 +308,6 @@ config ARCH_STM32
bool "STMicroelectronics STM32 SoC Family"
select GPIOLIB
select PINCTRL
- select PINCTRL_STM32MP257
select ARM_SMC_MBOX
select ARM_SCMI_PROTOCOL
select REGULATOR
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 2656d3d3ae402..6c18ac9cdeec2 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -2,7 +2,7 @@
if ARCH_STM32 || COMPILE_TEST
config PINCTRL_STM32
- bool
+ tristate
depends on OF
select PINMUX
select GENERIC_PINCONF
@@ -53,8 +53,8 @@ config PINCTRL_STM32MP157
select PINCTRL_STM32
config PINCTRL_STM32MP257
- bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25
+ tristate "STMicroelectronics STM32MP257 pin control"
depends on OF && HAS_IOMEM
- default MACH_STM32MP25
+ default ARM64 || COMPILE_TEST
select PINCTRL_STM32
endif
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index b6e7e34508592..5da2114b81420 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -1954,6 +1954,7 @@ int stm32_pctl_probe(struct platform_device *pdev)
return 0;
}
+EXPORT_SYMBOL(stm32_pctl_probe);
static int __maybe_unused stm32_pinctrl_restore_advcfgr(struct stm32_gpio_bank *bank,
int offset, u32 bpos)
@@ -2062,6 +2063,7 @@ int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
return 0;
}
+EXPORT_SYMBOL(stm32_pinctrl_suspend);
int __maybe_unused stm32_pinctrl_resume(struct device *dev)
{
@@ -2077,3 +2079,8 @@ int __maybe_unused stm32_pinctrl_resume(struct device *dev)
return 0;
}
+EXPORT_SYMBOL(stm32_pinctrl_resume);
+
+MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@foss.st.com>");
+MODULE_DESCRIPTION("STM32 core pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index b8caebc55cfc5..d17cbdbba4482 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -68,8 +68,22 @@ struct stm32_pinctrl_match_data {
bool rif_control;
};
+/**
+ * stm32_pctl_probe() - Common probe for stm32 pinctrl drivers.
+ * @pdev: Pinctrl platform device.
+ */
int stm32_pctl_probe(struct platform_device *pdev);
+
+/**
+ * stm32_pinctrl_suspend() - Common suspend for stm32 pinctrl drivers.
+ * @dev: Pinctrl device.
+ */
int stm32_pinctrl_suspend(struct device *dev);
+
+/**
+ * stm32_pinctrl_resume() - Common resume for stm32 pinctrl drivers.
+ * @dev: Pinctrl device.
+ */
int stm32_pinctrl_resume(struct device *dev);
#endif /* __PINCTRL_STM32_H */
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
index a374918030788..6709bddd97186 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
@@ -4,6 +4,7 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -2566,6 +2567,7 @@ static const struct of_device_id stm32mp257_pctrl_match[] = {
},
{ }
};
+MODULE_DEVICE_TABLE(of, stm32mp257_pctrl_match);
static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(stm32_pinctrl_suspend, stm32_pinctrl_resume)
@@ -2579,9 +2581,8 @@ static struct platform_driver stm32mp257_pinctrl_driver = {
.pm = &stm32_pinctrl_dev_pm_ops,
},
};
+module_platform_driver(stm32mp257_pinctrl_driver);
-static int __init stm32mp257_pinctrl_init(void)
-{
- return platform_driver_register(&stm32mp257_pinctrl_driver);
-}
-arch_initcall(stm32mp257_pinctrl_init);
+MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@foss.st.com>");
+MODULE_DESCRIPTION("STM32MP257 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/14] pinctrl: stm32: Add stm32mp215 pinctrl support
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (8 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 09/14] pinctrl: stm32: Allow compile as module " Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages Antonio Borneo
` (4 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Amelie Delaunay <amelie.delaunay@foss.st.com>
Add stm32mp215 pinctrl support.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/Kconfig | 6 +
drivers/pinctrl/stm32/Makefile | 1 +
drivers/pinctrl/stm32/pinctrl-stm32.h | 3 +
drivers/pinctrl/stm32/pinctrl-stm32mp215.c | 1807 ++++++++++++++++++++
4 files changed, 1817 insertions(+)
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp215.c
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 6c18ac9cdeec2..69e35309f3dcd 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -52,6 +52,12 @@ config PINCTRL_STM32MP157
default MACH_STM32MP157
select PINCTRL_STM32
+config PINCTRL_STM32MP215
+ tristate "STMicroelectronics STM32MP215 pin control"
+ depends on OF && HAS_IOMEM
+ default ARM64 || COMPILE_TEST
+ select PINCTRL_STM32
+
config PINCTRL_STM32MP257
tristate "STMicroelectronics STM32MP257 pin control"
depends on OF && HAS_IOMEM
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index 7b17464d8de1d..20c66053c82ca 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o
obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o
obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o
obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o
+obj-$(CONFIG_PINCTRL_STM32MP215) += pinctrl-stm32mp215.o
obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index d17cbdbba4482..1d576aad029d1 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -28,6 +28,9 @@
#define STM32MP_PKG_AI BIT(8)
#define STM32MP_PKG_AK BIT(10)
#define STM32MP_PKG_AL BIT(11)
+#define STM32MP_PKG_AM BIT(12)
+#define STM32MP_PKG_AN BIT(13)
+#define STM32MP_PKG_AO BIT(14)
struct stm32_desc_function {
const char *name;
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp215.c b/drivers/pinctrl/stm32/pinctrl-stm32mp215.c
new file mode 100644
index 0000000000000..9d2fd70191f23
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp215.c
@@ -0,0 +1,1807 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) STMicroelectronics 2024 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32mp215_pins[] = {
+ STM32_PIN_PKG(
+ PINCTRL_PIN(0, "PA0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "LPTIM1_CH2"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "UART5_TX"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(8, "TIM3_ETR"),
+ STM32_FUNCTION(9, "TIM5_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD2"),
+ STM32_FUNCTION(13, "FMC_NL"),
+ STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(1, "PA1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(3, "SPI6_MISO"),
+ STM32_FUNCTION(5, "SAI3_SD_A"),
+ STM32_FUNCTION(6, "USART1_RTS"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(8, "TIM4_CH2"),
+ STM32_FUNCTION(9, "I2C1_SDA"),
+ STM32_FUNCTION(12, "LCD_R3"),
+ STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(2, "PA2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "LPTIM2_IN1"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "I3C1_SDA"),
+ STM32_FUNCTION(11, "I2C1_SDA"),
+ STM32_FUNCTION(12, "LCD_B0"),
+ STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(3, "PA3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "LPTIM2_ETR"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "I3C1_SCL"),
+ STM32_FUNCTION(10, "I2C3_SMBA"),
+ STM32_FUNCTION(11, "I2C1_SCL"),
+ STM32_FUNCTION(12, "LCD_B1"),
+ STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(4, "PA4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(7, "USART2_TX"),
+ STM32_FUNCTION(8, "FDCAN2_TX"),
+ STM32_FUNCTION(9, "TIM2_CH1"),
+ STM32_FUNCTION(11, "LCD_R1"),
+ STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(5, "PA5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA5"),
+ STM32_FUNCTION(4, "SPI4_MOSI"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "USART2_RTS"),
+ STM32_FUNCTION(8, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM2_CH4"),
+ STM32_FUNCTION(11, "LCD_G0"),
+ STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(6, "PA6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA6"),
+ STM32_FUNCTION(4, "SPI4_SCK"),
+ STM32_FUNCTION(5, "SAI2_FS_B"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(9, "TIM2_ETR"),
+ STM32_FUNCTION(11, "LCD_G4"),
+ STM32_FUNCTION(13, "FMC_NE1"),
+ STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(7, "PA7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA7"),
+ STM32_FUNCTION(3, "CK_IN"),
+ STM32_FUNCTION(4, "SPI6_RDY"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(8, "TIM4_ETR"),
+ STM32_FUNCTION(9, "I2C2_SMBA"),
+ STM32_FUNCTION(11, "LCD_B5"),
+ STM32_FUNCTION(12, "I2C3_SMBA"),
+ STM32_FUNCTION(13, "I2C1_SMBA"),
+ STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(8, "PA8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA8"),
+ STM32_FUNCTION(2, "LPTIM2_CH2"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "USART2_RX"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(13, "LCD_B2"),
+ STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(9, "PA9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA9"),
+ STM32_FUNCTION(4, "SPI4_NSS"),
+ STM32_FUNCTION(5, "SAI2_SCK_B"),
+ STM32_FUNCTION(7, "USART2_CTS USART2_NSS"),
+ STM32_FUNCTION(8, "LPTIM5_ETR"),
+ STM32_FUNCTION(9, "TIM2_CH3"),
+ STM32_FUNCTION(11, "ETH1_MDC"),
+ STM32_FUNCTION(13, "LCD_G7"),
+ STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(10, "PA10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA10"),
+ STM32_FUNCTION(4, "SPI4_MISO"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "USART2_RX"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(9, "TIM2_CH2"),
+ STM32_FUNCTION(11, "ETH1_MDIO"),
+ STM32_FUNCTION(13, "LCD_R6"),
+ STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(11, "PA11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA11"),
+ STM32_FUNCTION(2, "SPI6_SCK"),
+ STM32_FUNCTION(3, "LPTIM2_CH1"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(12, "PA12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOA12"),
+ STM32_FUNCTION(3, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "SAI3_FS_A"),
+ STM32_FUNCTION(8, "TIM4_CH1"),
+ STM32_FUNCTION(9, "I2C1_SCL"),
+ STM32_FUNCTION(11, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(13, "PA13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA13"),
+ STM32_FUNCTION(2, "SPI6_RDY"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "LPTIM2_ETR"),
+ STM32_FUNCTION(6, "MDF1_CKI3"),
+ STM32_FUNCTION(7, "USART2_CTS USART2_NSS"),
+ STM32_FUNCTION(10, "I2C3_SMBA"),
+ STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(14, "PA14"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA14"),
+ STM32_FUNCTION(2, "SPI6_NSS"),
+ STM32_FUNCTION(3, "LPTIM2_CH2"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(6, "MDF1_CCK1"),
+ STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(15, "PA15"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOA15"),
+ STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(7, "USART2_RX"),
+ STM32_FUNCTION(10, "I2C3_SDA"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(17, "PB1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB1"),
+ STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "TIM16_CH1N"),
+ STM32_FUNCTION(13, "FMC_NCE4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(18, "PB2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB2"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(6, "MDF1_CKI3"),
+ STM32_FUNCTION(7, "TIM17_BKIN"),
+ STM32_FUNCTION(8, "TIM16_BKIN"),
+ STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(19, "PB3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB3"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(6, "MDF1_SDI3"),
+ STM32_FUNCTION(13, "FMC_NCE3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(21, "PB5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB5"),
+ STM32_FUNCTION(3, "I2S2_MCK"),
+ STM32_FUNCTION(4, "UART4_RTS"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(13, "FMC_AD8 FMC_D8"),
+ STM32_FUNCTION(14, "I3C2_SCL"),
+ STM32_FUNCTION(15, "SDMMC3_D123DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(22, "PB6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB6"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "UART4_RX"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(13, "FMC_AD9 FMC_D9"),
+ STM32_FUNCTION(15, "SDMMC3_D0DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(23, "PB7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB7"),
+ STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(4, "UART4_TX"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(13, "FMC_AD10 FMC_D10"),
+ STM32_FUNCTION(15, "SDMMC3_CDIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(25, "PB9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB9"),
+ STM32_FUNCTION(2, "SPI3_RDY"),
+ STM32_FUNCTION(7, "USART1_RTS"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(10, "TIM10_CH1"),
+ STM32_FUNCTION(13, "FMC_AD13 FMC_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(26, "PB10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOB10"),
+ STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(8, "TIM17_CH1N"),
+ STM32_FUNCTION(13, "FMC_AD15 FMC_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(27, "PB11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOB11"),
+ STM32_FUNCTION(2, "I2S3_MCK"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(13, "FMC_AD14 FMC_D14"),
+ STM32_FUNCTION(14, "OCTOSPI1_NCS2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(28, "PB12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOB12"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(11, "SDMMC3_D2"),
+ STM32_FUNCTION(12, "FMC_NWAIT"),
+ STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(29, "PB13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOB13"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(11, "SDMMC3_CK"),
+ STM32_FUNCTION(12, "FMC_AD5 FMC_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(30, "PB14"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOB14"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(10, "TIM4_CH2"),
+ STM32_FUNCTION(11, "SDMMC3_D0"),
+ STM32_FUNCTION(12, "FMC_AD7 FMC_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(31, "PB15"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOB15"),
+ STM32_FUNCTION(2, "LPTIM1_IN2"),
+ STM32_FUNCTION(3, "SPI5_SCK"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(6, "UART5_RX"),
+ STM32_FUNCTION(8, "TIM3_CH2"),
+ STM32_FUNCTION(9, "TIM5_CH1"),
+ STM32_FUNCTION(11, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_A18"),
+ STM32_FUNCTION(14, "LCD_R4"),
+ STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(32, "PC0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC0"),
+ STM32_FUNCTION(2, "LPTIM1_CH1"),
+ STM32_FUNCTION(4, "SPI6_SCK"),
+ STM32_FUNCTION(5, "SAI3_MCLK_B"),
+ STM32_FUNCTION(6, "USART6_TX"),
+ STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RMII_REF_CLK"),
+ STM32_FUNCTION(12, "ETH1_MII_TX_CLK"),
+ STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"),
+ STM32_FUNCTION(14, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(33, "PC1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC1"),
+ STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(7, "USART2_TX"),
+ STM32_FUNCTION(10, "I2C3_SCL"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(34, "PC2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC2"),
+ STM32_FUNCTION(2, "SPI6_MOSI"),
+ STM32_FUNCTION(3, "LPTIM2_IN1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(6, "MDF1_SDI3"),
+ STM32_FUNCTION(7, "USART2_RTS"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(35, "PC3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC3"),
+ STM32_FUNCTION(2, "LPTIM1_IN2"),
+ STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(4, "SPI6_RDY"),
+ STM32_FUNCTION(7, "USART6_RTS"),
+ STM32_FUNCTION(8, "FDCAN2_TX"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
+ STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
+ STM32_FUNCTION(14, "LCD_G6"),
+ STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(36, "PC4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC4"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(5, "SAI3_FS_B"),
+ STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"),
+ STM32_FUNCTION(13, "ETH1_RGMII_CLK125"),
+ STM32_FUNCTION(14, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(37, "PC5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC5"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN1"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(10, "I2C1_SDA"),
+ STM32_FUNCTION(11, "ETH2_MDIO"),
+ STM32_FUNCTION(12, "ETH1_MII_COL"),
+ STM32_FUNCTION(13, "FMC_A25"),
+ STM32_FUNCTION(14, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(38, "PC6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC6"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(9, "TIM8_CH1"),
+ STM32_FUNCTION(10, "I2C1_SCL"),
+ STM32_FUNCTION(11, "ETH2_MDC"),
+ STM32_FUNCTION(12, "ETH1_MII_CRS"),
+ STM32_FUNCTION(13, "FMC_A24"),
+ STM32_FUNCTION(14, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(39, "PC7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC7"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "SAI3_SD_B"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"),
+ STM32_FUNCTION(12, "ETH1_MII_TXD2"),
+ STM32_FUNCTION(14, "LCD_B4"),
+ STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(40, "PC8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC8"),
+ STM32_FUNCTION(2, "LPTIM1_ETR"),
+ STM32_FUNCTION(4, "SPI6_NSS"),
+ STM32_FUNCTION(5, "SAI3_SCK_B"),
+ STM32_FUNCTION(7, "USART6_CTS USART6_NSS"),
+ STM32_FUNCTION(9, "TIM8_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"),
+ STM32_FUNCTION(12, "ETH1_MII_TXD3"),
+ STM32_FUNCTION(14, "LCD_B3"),
+ STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(41, "PC9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC9"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(5, "SAI2_SCK_A"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(10, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
+ STM32_FUNCTION(13, "FMC_A22"),
+ STM32_FUNCTION(14, "LCD_G2"),
+ STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(42, "PC10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC10"),
+ STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(10, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
+ STM32_FUNCTION(12, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(13, "FMC_A23"),
+ STM32_FUNCTION(14, "LCD_G3"),
+ STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(43, "PC11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC11"),
+ STM32_FUNCTION(2, "LPTIM1_CH1"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(5, "SAI2_MCLK_A"),
+ STM32_FUNCTION(6, "UART5_RTS"),
+ STM32_FUNCTION(7, "USART3_RTS"),
+ STM32_FUNCTION(8, "TIM3_CH1"),
+ STM32_FUNCTION(9, "TIM5_ETR"),
+ STM32_FUNCTION(10, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
+ STM32_FUNCTION(13, "FMC_NBL1"),
+ STM32_FUNCTION(14, "LCD_R2"),
+ STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(44, "PC12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC12"),
+ STM32_FUNCTION(2, "LPTIM1_CH2"),
+ STM32_FUNCTION(4, "I3C3_SCL"),
+ STM32_FUNCTION(5, "I3C2_SCL"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(10, "I2C3_SCL"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
+ STM32_FUNCTION(12, "ETH1_MII_RXD3"),
+ STM32_FUNCTION(14, "LCD_G1"),
+ STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(45, "PC13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOC13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(48, "PD0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD0"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(4, "SAI1_D2"),
+ STM32_FUNCTION(6, "SAI4_FS_A"),
+ STM32_FUNCTION(7, "UART7_RX"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "OCTOSPI1_CLK"),
+ STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(49, "PD1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD1"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SAI1_CK2"),
+ STM32_FUNCTION(6, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "UART7_RTS"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(11, "OCTOSPI1_NCLK"),
+ STM32_FUNCTION(12, "OCTOSPI1_NCS2"),
+ STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(50, "PD2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD2"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(4, "SAI1_CK1"),
+ STM32_FUNCTION(6, "SAI4_SCK_A"),
+ STM32_FUNCTION(7, "UART7_CTS"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(11, "OCTOSPI1_DQS"),
+ STM32_FUNCTION(12, "OCTOSPI1_NCS2"),
+ STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(51, "PD3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD3"),
+ STM32_FUNCTION(2, "SAI1_MCLK_A"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(4, "SAI1_D1"),
+ STM32_FUNCTION(6, "SAI4_MCLK_A"),
+ STM32_FUNCTION(7, "UART7_TX"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "SDVSEL2"),
+ STM32_FUNCTION(11, "OCTOSPI1_NCS1"),
+ STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(52, "PD4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD4"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "SPI4_MISO"),
+ STM32_FUNCTION(3, "HDP3"),
+ STM32_FUNCTION(4, "SAI1_D3"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(10, "TIM4_CH1"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO0"),
+ STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(53, "PD5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD5"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "SPI4_NSS"),
+ STM32_FUNCTION(3, "HDP4"),
+ STM32_FUNCTION(4, "SAI1_D4"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(10, "TIM4_CH2"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO1"),
+ STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(54, "PD6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD6"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "SPI4_MOSI"),
+ STM32_FUNCTION(3, "HDP5"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(10, "TIM4_CH3"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO2"),
+ STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(55, "PD7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD7"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "SPI4_SCK"),
+ STM32_FUNCTION(3, "SPI1_RDY"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(10, "TIM4_CH4"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO3"),
+ STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(56, "PD8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD8"),
+ STM32_FUNCTION(1, "TRACED4"),
+ STM32_FUNCTION(2, "SPI4_RDY"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(4, "SAI1_FS_A"),
+ STM32_FUNCTION(5, "UART4_CTS"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(10, "TIM4_ETR"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO4"),
+ STM32_FUNCTION(12, "SDMMC1_D7"),
+ STM32_FUNCTION(13, "SDMMC1_D123DIR"),
+ STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(57, "PD9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD9"),
+ STM32_FUNCTION(1, "TRACED5"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(4, "SAI1_SD_A"),
+ STM32_FUNCTION(5, "UART4_RTS"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO5"),
+ STM32_FUNCTION(12, "SDMMC1_D6"),
+ STM32_FUNCTION(13, "SDMMC1_D0DIR"),
+ STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(58, "PD10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD10"),
+ STM32_FUNCTION(1, "TRACED6"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(4, "SAI1_SCK_A"),
+ STM32_FUNCTION(5, "UART4_RX"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(7, "I2C1_SDA"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO6"),
+ STM32_FUNCTION(12, "SDMMC1_D5"),
+ STM32_FUNCTION(13, "SDMMC1_CDIR"),
+ STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(59, "PD11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD11"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SAI1_MCLK_A"),
+ STM32_FUNCTION(5, "UART4_TX"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(7, "I2C1_SCL"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "OCTOSPI1_IO7"),
+ STM32_FUNCTION(12, "SDMMC1_D4"),
+ STM32_FUNCTION(13, "SDMMC1_CKIN"),
+ STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(60, "PD12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD12"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(10, "TIM4_ETR"),
+ STM32_FUNCTION(11, "SDMMC3_CMD"),
+ STM32_FUNCTION(12, "FMC_AD6 FMC_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(61, "PD13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD13"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(10, "TIM4_CH4"),
+ STM32_FUNCTION(11, "SDMMC3_D1"),
+ STM32_FUNCTION(12, "FMC_AD11 FMC_D11"),
+ STM32_FUNCTION(13, "FMC_NWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(62, "PD14"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD14"),
+ STM32_FUNCTION(2, "I2S2_MCK"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(12, "FMC_AD4 FMC_D4"),
+ STM32_FUNCTION(13, "SDMMC3_D3"),
+ STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(63, "PD15"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOD15"),
+ STM32_FUNCTION(2, "SPI1_RDY"),
+ STM32_FUNCTION(7, "I2C2_SDA"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "TIM5_ETR"),
+ STM32_FUNCTION(12, "FMC_AD3 FMC_D3"),
+ STM32_FUNCTION(13, "SDMMC3_CKIN"),
+ STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(64, "PE0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE0"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "LPTIM2_CH1"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPI3_RDY"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(11, "SDMMC1_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(65, "PE1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE1"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "LPTIM2_CH2"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(4, "I2S3_MCK"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(11, "SDMMC1_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(66, "PE2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE2"),
+ STM32_FUNCTION(2, "LPTIM2_ETR"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(11, "SDMMC1_CMD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(67, "PE3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE3"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(3, "SPI1_RDY"),
+ STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "SDMMC1_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(68, "PE4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE4"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "LPTIM2_IN1"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(7, "USART3_CTS USART3_NSS"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(11, "SDMMC1_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(69, "PE5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE5"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "LPTIM2_IN2"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(7, "USART3_RTS"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(11, "SDMMC1_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(70, "PE6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE6"),
+ STM32_FUNCTION(2, "SPI4_RDY"),
+ STM32_FUNCTION(5, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(12, "FMC_AD1 FMC_D1"),
+ STM32_FUNCTION(13, "SDMMC2_D6"),
+ STM32_FUNCTION(14, "SDMMC2_D0DIR"),
+ STM32_FUNCTION(15, "SDMMC2_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(71, "PE7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE7"),
+ STM32_FUNCTION(4, "SAI4_D4"),
+ STM32_FUNCTION(5, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(11, "TIM14_CH1"),
+ STM32_FUNCTION(12, "FMC_AD2 FMC_D2"),
+ STM32_FUNCTION(13, "SDMMC2_D7"),
+ STM32_FUNCTION(14, "SDMMC2_D123DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(72, "PE8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE8"),
+ STM32_FUNCTION(2, "SPI4_MOSI"),
+ STM32_FUNCTION(4, "SAI4_CK1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_A"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(12, "FMC_A17 FMC_ALE"),
+ STM32_FUNCTION(13, "SDMMC2_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(73, "PE9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE9"),
+ STM32_FUNCTION(2, "SPI4_MISO"),
+ STM32_FUNCTION(4, "SAI4_D2"),
+ STM32_FUNCTION(5, "SAI4_FS_A"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(12, "FMC_AD0 FMC_D0"),
+ STM32_FUNCTION(13, "SDMMC2_D5"),
+ STM32_FUNCTION(14, "SDMMC2_CDIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(74, "PE10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE10"),
+ STM32_FUNCTION(2, "SPI4_SCK"),
+ STM32_FUNCTION(4, "SAI4_D1"),
+ STM32_FUNCTION(5, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(11, "FMC_NE3"),
+ STM32_FUNCTION(12, "FMC_NCE2"),
+ STM32_FUNCTION(13, "SDMMC2_D4"),
+ STM32_FUNCTION(14, "SDMMC2_CKIN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(75, "PE11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE11"),
+ STM32_FUNCTION(4, "SAI4_D3"),
+ STM32_FUNCTION(5, "SAI1_FS_A"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(12, "FMC_A16 FMC_CLE"),
+ STM32_FUNCTION(13, "SDMMC2_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(76, "PE12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE12"),
+ STM32_FUNCTION(2, "SPI4_NSS"),
+ STM32_FUNCTION(4, "SAI4_CK2"),
+ STM32_FUNCTION(5, "SAI4_SCK_A"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(7, "USART1_RTS"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(11, "FMC_NE2"),
+ STM32_FUNCTION(12, "FMC_NCE1"),
+ STM32_FUNCTION(13, "SDMMC2_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(77, "PE13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOE13"),
+ STM32_FUNCTION(5, "SAI1_SD_A"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(12, "FMC_RNB"),
+ STM32_FUNCTION(13, "SDMMC2_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(78, "PE14"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOE14"),
+ STM32_FUNCTION(5, "SAI1_MCLK_A"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(12, "FMC_NWE"),
+ STM32_FUNCTION(13, "SDMMC2_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(79, "PE15"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOE15"),
+ STM32_FUNCTION(5, "SAI1_SCK_A"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(12, "FMC_NOE"),
+ STM32_FUNCTION(13, "SDMMC2_CMD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(80, "PF0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF0"),
+ STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(8, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM12_CH2"),
+ STM32_FUNCTION(10, "I2C2_SDA"),
+ STM32_FUNCTION(11, "ETH1_MDC"),
+ STM32_FUNCTION(12, "ETH2_MII_CRS"),
+ STM32_FUNCTION(14, "I3C2_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(81, "PF1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF1"),
+ STM32_FUNCTION(2, "SPI6_MISO"),
+ STM32_FUNCTION(3, "LPTIM2_IN2"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(82, "PF2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF2"),
+ STM32_FUNCTION(3, "SPI3_RDY"),
+ STM32_FUNCTION(7, "I2C1_SMBA"),
+ STM32_FUNCTION(9, "TIM12_CH1"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(11, "ETH1_MDIO"),
+ STM32_FUNCTION(12, "ETH2_MII_COL"),
+ STM32_FUNCTION(13, "FMC_NE4"),
+ STM32_FUNCTION(14, "I3C2_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(83, "PF3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF3"),
+ STM32_FUNCTION(5, "SAI2_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(8, "TIM3_CH4"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_A20"),
+ STM32_FUNCTION(14, "LCD_R6"),
+ STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(84, "PF4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF4"),
+ STM32_FUNCTION(2, "RTC_OUT2"),
+ STM32_FUNCTION(3, "SPI6_NSS"),
+ STM32_FUNCTION(5, "SAI3_SCK_A"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(8, "TIM4_CH4"),
+ STM32_FUNCTION(9, "ETH1_MDC"),
+ STM32_FUNCTION(10, "ETH2_CLK"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(12, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(14, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(85, "PF5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF5"),
+ STM32_FUNCTION(3, "SPI6_SCK"),
+ STM32_FUNCTION(5, "SAI3_MCLK_A"),
+ STM32_FUNCTION(7, "USART6_TX"),
+ STM32_FUNCTION(8, "TIM4_CH3"),
+ STM32_FUNCTION(9, "ETH1_MDIO"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_PHY_INTN"),
+ STM32_FUNCTION(12, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(14, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(86, "PF6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF6"),
+ STM32_FUNCTION(2, "RTC_OUT2"),
+ STM32_FUNCTION(4, "SAI3_MCLK_B"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(8, "TIM12_CH1"),
+ STM32_FUNCTION(10, "I2C3_SMBA"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
+ STM32_FUNCTION(14, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(87, "PF7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF7"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN1"),
+ STM32_FUNCTION(4, "SPI6_SCK"),
+ STM32_FUNCTION(5, "SAI3_SD_A"),
+ STM32_FUNCTION(8, "TIM2_ETR"),
+ STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"),
+ STM32_FUNCTION(12, "ETH2_MII_TX_CLK"),
+ STM32_FUNCTION(14, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(88, "PF8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF8"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(4, "SAI3_SCK_B"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(8, "TIM12_CH2"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_RGMII_CLK125"),
+ STM32_FUNCTION(12, "ETH2_MII_RX_ER"),
+ STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RMII_CRS_DV"),
+ STM32_FUNCTION(14, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(89, "PF9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF9"),
+ STM32_FUNCTION(4, "SAI3_SD_B"),
+ STM32_FUNCTION(5, "SAI2_SD_A"),
+ STM32_FUNCTION(8, "TIM2_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
+ STM32_FUNCTION(12, "ETH2_MDIO"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(90, "PF10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF10"),
+ STM32_FUNCTION(2, "MCO2"),
+ STM32_FUNCTION(3, "SPI3_RDY"),
+ STM32_FUNCTION(5, "SAI2_MCLK_A"),
+ STM32_FUNCTION(8, "TIM2_CH3"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(91, "PF11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF11"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(4, "SPI6_RDY"),
+ STM32_FUNCTION(5, "SAI2_SCK_A"),
+ STM32_FUNCTION(8, "TIM2_CH4"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(92, "PF12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF12"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(9, "TIM5_CH1"),
+ STM32_FUNCTION(14, "LCD_CLK"),
+ STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(93, "PF13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF13"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(3, "CK_IN"),
+ STM32_FUNCTION(4, "USART6_TX"),
+ STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(7, "USART3_CTS USART3_NSS"),
+ STM32_FUNCTION(9, "TIM3_CH3"),
+ STM32_FUNCTION(14, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(95, "PF15"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOF15"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI2_RDY"),
+ STM32_FUNCTION(4, "USART6_CTS USART6_NSS"),
+ STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(8, "TIM2_CH2"),
+ STM32_FUNCTION(9, "TIM3_ETR"),
+ STM32_FUNCTION(14, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(96, "PG0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG0"),
+ STM32_FUNCTION(2, "LPTIM1_IN1"),
+ STM32_FUNCTION(4, "I3C3_SDA"),
+ STM32_FUNCTION(5, "I3C2_SDA"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "I2C3_SDA"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"),
+ STM32_FUNCTION(12, "ETH1_MII_RXD2"),
+ STM32_FUNCTION(14, "LCD_G5"),
+ STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(97, "PG1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG1"),
+ STM32_FUNCTION(2, "LPTIM1_IN1"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "I3C3_SCL"),
+ STM32_FUNCTION(5, "SAI2_SD_A"),
+ STM32_FUNCTION(6, "UART5_CTS"),
+ STM32_FUNCTION(7, "USART3_CTS USART3_NSS"),
+ STM32_FUNCTION(9, "TIM5_CH4"),
+ STM32_FUNCTION(10, "I2C3_SCL"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_ER"),
+ STM32_FUNCTION(12, "ETH2_MII_RXD3"),
+ STM32_FUNCTION(13, "FMC_NBL0"),
+ STM32_FUNCTION(14, "LCD_VSYNC"),
+ STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(98, "PG2"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG2"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "I3C3_SDA"),
+ STM32_FUNCTION(5, "SAI2_FS_A"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(9, "TIM5_CH3"),
+ STM32_FUNCTION(10, "I2C3_SDA"),
+ STM32_FUNCTION(11, "ETH2_MII_TX_CLK"),
+ STM32_FUNCTION(12, "ETH2_RGMII_CLK125"),
+ STM32_FUNCTION(13, "FMC_CLK"),
+ STM32_FUNCTION(14, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(99, "PG3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG3"),
+ STM32_FUNCTION(2, "LPTIM1_ETR"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(5, "SAI2_FS_B"),
+ STM32_FUNCTION(8, "TIM3_CH3"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(10, "ETH2_CLK"),
+ STM32_FUNCTION(11, "ETH2_PHY_INTN"),
+ STM32_FUNCTION(13, "FMC_A19"),
+ STM32_FUNCTION(14, "LCD_R5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(100, "PG4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG4"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SAI3_FS_B"),
+ STM32_FUNCTION(8, "LPTIM4_IN1"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(12, "ETH2_MDC"),
+ STM32_FUNCTION(13, "FMC_A21"),
+ STM32_FUNCTION(14, "LCD_R7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(101, "PG5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG5"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "HDP3"),
+ STM32_FUNCTION(4, "USART6_RTS"),
+ STM32_FUNCTION(8, "TIM2_CH3"),
+ STM32_FUNCTION(14, "LCD_R5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(103, "PG7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOG7"),
+ STM32_FUNCTION(1, "TRACED5"),
+ STM32_FUNCTION(2, "HDP5"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(9, "TIM5_ETR"),
+ STM32_FUNCTION(14, "LCD_R7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(104, "PG8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOG8"),
+ STM32_FUNCTION(1, "TRACED6"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(4, "SPI1_RDY"),
+ STM32_FUNCTION(5, "USART6_CK"),
+ STM32_FUNCTION(6, "UART5_RTS"),
+ STM32_FUNCTION(9, "TIM5_CH3"),
+ STM32_FUNCTION(14, "LCD_G2"),
+ STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(105, "PG9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOG9"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(6, "UART5_TX"),
+ STM32_FUNCTION(9, "TIM5_CH4"),
+ STM32_FUNCTION(14, "LCD_G3"),
+ STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(106, "PG10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOG10"),
+ STM32_FUNCTION(1, "TRACED8"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(6, "UART5_RX"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(14, "LCD_G4"),
+ STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(107, "PG11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG11"),
+ STM32_FUNCTION(1, "TRACED9"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(14, "LCD_G5"),
+ STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(108, "PG12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG12"),
+ STM32_FUNCTION(1, "TRACED10"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(14, "LCD_G6"),
+ STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(109, "PG13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOG13"),
+ STM32_FUNCTION(1, "TRACED11"),
+ STM32_FUNCTION(2, "HDP3"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(10, "I2C1_SCL"),
+ STM32_FUNCTION(11, "I3C1_SCL"),
+ STM32_FUNCTION(14, "LCD_G7"),
+ STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(110, "PG14"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOG14"),
+ STM32_FUNCTION(1, "TRACED12"),
+ STM32_FUNCTION(2, "HDP4"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(14, "LCD_B1"),
+ STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(111, "PG15"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOG15"),
+ STM32_FUNCTION(1, "TRACED13"),
+ STM32_FUNCTION(2, "HDP5"),
+ STM32_FUNCTION(4, "LPTIM1_CH2"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(14, "LCD_B2"),
+ STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(116, "PH4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH4"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(7, "UART7_TX"),
+ STM32_FUNCTION(8, "TIM17_BKIN"),
+ STM32_FUNCTION(10, "TIM5_CH2"),
+ STM32_FUNCTION(11, "LCD_R0"),
+ STM32_FUNCTION(13, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(117, "PH5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH5"),
+ STM32_FUNCTION(1, "DBTRGO"),
+ STM32_FUNCTION(2, "DBTRGI"),
+ STM32_FUNCTION(5, "SAI2_FS_A"),
+ STM32_FUNCTION(8, "TIM2_CH1"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(11, "LCD_G1"),
+ STM32_FUNCTION(13, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(119, "PH7"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOH7"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(5, "UART4_TX"),
+ STM32_FUNCTION(7, "UART7_RTS"),
+ STM32_FUNCTION(8, "TIM17_CH1"),
+ STM32_FUNCTION(10, "TIM5_CH4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(120, "PH8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOH8"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(5, "UART4_RX"),
+ STM32_FUNCTION(7, "UART7_CTS"),
+ STM32_FUNCTION(10, "TIM5_CH1"),
+ STM32_FUNCTION(11, "I2C3_SMBA"),
+ STM32_FUNCTION(12, "I2C2_SMBA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(121, "PH9"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH9"),
+ STM32_FUNCTION(4, "SPI6_NSS"),
+ STM32_FUNCTION(5, "SAI3_MCLK_A"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(11, "ETH1_RGMII_CLK125"),
+ STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(122, "PH10"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH10"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "SAI3_SCK_A"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(10, "ETH2_MDC"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(123, "PH11"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH11"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(5, "SAI3_FS_A"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(10, "ETH2_MDIO"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(124, "PH12"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH12"),
+ STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(125, "PH13"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOH13"),
+ STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(128, "PI0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOI0"),
+ STM32_FUNCTION(1, "TRACED14"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(4, "LPTIM1_IN1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(14, "LCD_B3"),
+ STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(129, "PI1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOI1"),
+ STM32_FUNCTION(1, "TRACED15"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "I2C1_SDA"),
+ STM32_FUNCTION(11, "I3C1_SDA"),
+ STM32_FUNCTION(14, "LCD_B4"),
+ STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(132, "PI4"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN | STM32MP_PKG_AO,
+ STM32_FUNCTION(0, "GPIOI4"),
+ STM32_FUNCTION(4, "LPTIM1_CH1"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(14, "LCD_B7"),
+ STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(133, "PI5"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOI5"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(6, "UART5_CTS"),
+ STM32_FUNCTION(9, "TIM5_CH2"),
+ STM32_FUNCTION(14, "LCD_DE"),
+ STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(134, "PI6"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOI6"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(8, "TIM2_ETR"),
+ STM32_FUNCTION(9, "TIM3_CH1"),
+ STM32_FUNCTION(14, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(136, "PI8"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOI8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static const struct stm32_desc_pin stm32mp215_z_pins[] = {
+ STM32_PIN_PKG(
+ PINCTRL_PIN(400, "PZ0"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOZ0"),
+ STM32_FUNCTION(3, "LPTIM3_IN1"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "TIM8_CH1"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM5_OUT"),
+ STM32_FUNCTION(9, "I2C3_SDA"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(12, "I3C3_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(401, "PZ1"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOZ1"),
+ STM32_FUNCTION(3, "LPTIM3_CH1"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(5, "TIM8_CH2"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM5_ETR"),
+ STM32_FUNCTION(9, "I2C3_SCL"),
+ STM32_FUNCTION(10, "I2C3_SMBA"),
+ STM32_FUNCTION(12, "I3C3_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(403, "PZ3"),
+ STM32MP_PKG_AL | STM32MP_PKG_AM | STM32MP_PKG_AN,
+ STM32_FUNCTION(0, "GPIOZ3"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(3, "LPTIM3_ETR"),
+ STM32_FUNCTION(4, "SPI6_NSS"),
+ STM32_FUNCTION(5, "MDF1_SDI3"),
+ STM32_FUNCTION(7, "LPUART1_CTS"),
+ STM32_FUNCTION(8, "LPTIM4_IN1"),
+ STM32_FUNCTION(9, "I2C3_SDA"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(12, "I3C3_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static struct stm32_pinctrl_match_data stm32mp215_match_data = {
+ .pins = stm32mp215_pins,
+ .npins = ARRAY_SIZE(stm32mp215_pins),
+ .io_sync_control = true,
+ .secure_control = true,
+ .rif_control = true,
+};
+
+static struct stm32_pinctrl_match_data stm32mp215_z_match_data = {
+ .pins = stm32mp215_z_pins,
+ .npins = ARRAY_SIZE(stm32mp215_z_pins),
+ .io_sync_control = true,
+ .secure_control = true,
+ .rif_control = true,
+};
+
+static const struct of_device_id stm32mp215_pctrl_match[] = {
+ {
+ .compatible = "st,stm32mp215-pinctrl",
+ .data = &stm32mp215_match_data,
+ },
+ {
+ .compatible = "st,stm32mp215-z-pinctrl",
+ .data = &stm32mp215_z_match_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, stm32mp215_pctrl_match);
+
+static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(stm32_pinctrl_suspend, stm32_pinctrl_resume)
+};
+
+static struct platform_driver stm32mp215_pinctrl_driver = {
+ .probe = stm32_pctl_probe,
+ .driver = {
+ .name = "stm32mp215-pinctrl",
+ .of_match_table = stm32mp215_pctrl_match,
+ .pm = &stm32_pinctrl_dev_pm_ops,
+ },
+};
+module_platform_driver(stm32mp215_pinctrl_driver);
+
+MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@foss.st.com>");
+MODULE_DESCRIPTION("STM32MP215 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (9 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 10/14] pinctrl: stm32: Add stm32mp215 pinctrl support Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-23 8:51 ` Krzysztof Kozlowski
2024-10-22 15:56 ` [PATCH 12/14] pinctrl: stm32: Add stm32mp235 pinctrl support Antonio Borneo
` (3 subsequent siblings)
14 siblings, 1 reply; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Amelie Delaunay <amelie.delaunay@foss.st.com>
Add support for st,stm32mp215-pinctrl and st,stm32mp215-z-pinctrl.
Add packages AM, AN and AO (values : 0x1000, 0x2000 and 0x8000)
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
.../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +++-
include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index 9a7ecfea6eb5b..0a2d644dbece3 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -27,6 +27,8 @@ properties:
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl
+ - st,stm32mp215-pinctrl
+ - st,stm32mp215-z-pinctrl
- st,stm32mp257-pinctrl
- st,stm32mp257-z-pinctrl
@@ -59,7 +61,7 @@ properties:
Indicates the SOC package used.
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
$ref: /schemas/types.yaml#/definitions/uint32
- enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
+ enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800, 0x1000, 0x2000, 0x4000]
patternProperties:
'^gpio@[0-9a-f]*$':
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index af3fd388329a0..01bc8be78ef72 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -41,6 +41,9 @@
#define STM32MP_PKG_AI 0x100
#define STM32MP_PKG_AK 0x400
#define STM32MP_PKG_AL 0x800
+#define STM32MP_PKG_AM 0x1000
+#define STM32MP_PKG_AN 0x2000
+#define STM32MP_PKG_AO 0x4000
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/14] pinctrl: stm32: Add stm32mp235 pinctrl support
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (10 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-22 15:56 ` [PATCH 13/14] dt-bindings: pinctrl: stm32: add support for stm32mp235 Antonio Borneo
` (2 subsequent siblings)
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Clément Le Goffic <clement.legoffic@foss.st.com>
Add stm32mp235 pinctrl support.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/Kconfig | 6 +
drivers/pinctrl/stm32/Makefile | 1 +
drivers/pinctrl/stm32/pinctrl-stm32mp235.c | 1906 ++++++++++++++++++++
3 files changed, 1913 insertions(+)
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp235.c
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 69e35309f3dcd..e8efc9472618a 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -58,6 +58,12 @@ config PINCTRL_STM32MP215
default ARM64 || COMPILE_TEST
select PINCTRL_STM32
+config PINCTRL_STM32MP235
+ tristate "STMicroelectronics STM32MP235 pin control"
+ depends on OF && HAS_IOMEM
+ default ARM64 || COMPILE_TEST
+ select PINCTRL_STM32
+
config PINCTRL_STM32MP257
tristate "STMicroelectronics STM32MP257 pin control"
depends on OF && HAS_IOMEM
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index 20c66053c82ca..0e0ffa14b72cd 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o
obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o
obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o
obj-$(CONFIG_PINCTRL_STM32MP215) += pinctrl-stm32mp215.o
+obj-$(CONFIG_PINCTRL_STM32MP235) += pinctrl-stm32mp235.o
obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp235.c b/drivers/pinctrl/stm32/pinctrl-stm32mp235.c
new file mode 100644
index 0000000000000..1f5793a4acdbf
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp235.c
@@ -0,0 +1,1906 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) STMicroelectronics 2024 - All Rights Reserved
+ * Author: Clément Le Goffic <clement.legoffic@foss.st.com> for STMicroelectronics.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-stm32.h"
+static const struct stm32_desc_pin stm32mp235_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(0, "PA0"),
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "LPTIM1_CH2"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "UART5_TX"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(8, "TIM3_ETR"),
+ STM32_FUNCTION(9, "TIM5_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD2"),
+ STM32_FUNCTION(13, "FMC_NL"),
+ STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(1, "PA1"),
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(5, "SAI3_SD_A"),
+ STM32_FUNCTION(6, "USART1_RTS USART1_DE"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(8, "TIM4_CH2"),
+ STM32_FUNCTION(12, "LCD_R3"),
+ STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(2, "PA2"),
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "LPTIM2_IN1"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "I3C1_SDA"),
+ STM32_FUNCTION(11, "I2C1_SDA"),
+ STM32_FUNCTION(12, "LCD_B0"),
+ STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(3, "PA3"),
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "LPTIM2_ETR"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "I3C1_SCL"),
+ STM32_FUNCTION(10, "I2C7_SMBA"),
+ STM32_FUNCTION(11, "I2C1_SCL"),
+ STM32_FUNCTION(12, "LCD_B1"),
+ STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(4, "PA4"),
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(7, "USART2_TX"),
+ STM32_FUNCTION(8, "FDCAN2_TX"),
+ STM32_FUNCTION(9, "TIM2_CH1"),
+ STM32_FUNCTION(11, "LCD_R1"),
+ STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(5, "PA5"),
+ STM32_FUNCTION(0, "GPIOA5"),
+ STM32_FUNCTION(4, "SPI4_MOSI"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "USART2_RTS USART2_DE"),
+ STM32_FUNCTION(8, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM2_CH4"),
+ STM32_FUNCTION(11, "LCD_G0"),
+ STM32_FUNCTION(13, "FMC_A0"),
+ STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(6, "PA6"),
+ STM32_FUNCTION(0, "GPIOA6"),
+ STM32_FUNCTION(4, "SPI4_SCK"),
+ STM32_FUNCTION(5, "SAI2_FS_B"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(9, "TIM2_ETR"),
+ STM32_FUNCTION(11, "LCD_G4"),
+ STM32_FUNCTION(13, "FMC_NE1"),
+ STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(7, "PA7"),
+ STM32_FUNCTION(0, "GPIOA7"),
+ STM32_FUNCTION(3, "AUDIOCLK"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(8, "TIM4_ETR"),
+ STM32_FUNCTION(9, "I2C2_SMBA"),
+ STM32_FUNCTION(11, "LCD_B5"),
+ STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(8, "PA8"),
+ STM32_FUNCTION(0, "GPIOA8"),
+ STM32_FUNCTION(2, "LPTIM2_CH2"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "USART2_RX"),
+ STM32_FUNCTION(13, "LCD_B2"),
+ STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(9, "PA9"),
+ STM32_FUNCTION(0, "GPIOA9"),
+ STM32_FUNCTION(4, "SPI4_NSS"),
+ STM32_FUNCTION(5, "SAI2_SCK_B"),
+ STM32_FUNCTION(7, "USART2_CTS USART2_NSS"),
+ STM32_FUNCTION(8, "LPTIM5_ETR"),
+ STM32_FUNCTION(9, "TIM2_CH3"),
+ STM32_FUNCTION(11, "ETH1_MDC"),
+ STM32_FUNCTION(13, "LCD_G7"),
+ STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(10, "PA10"),
+ STM32_FUNCTION(0, "GPIOA10"),
+ STM32_FUNCTION(4, "SPI4_MISO"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "USART2_RX"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(9, "TIM2_CH2"),
+ STM32_FUNCTION(11, "ETH1_MDIO"),
+ STM32_FUNCTION(13, "LCD_R6"),
+ STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(11, "PA11"),
+ STM32_FUNCTION(0, "GPIOA11"),
+ STM32_FUNCTION(2, "SPI8_SCK"),
+ STM32_FUNCTION(3, "LPTIM2_CH1"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(12, "PA12"),
+ STM32_FUNCTION(0, "GPIOA12"),
+ STM32_FUNCTION(5, "SAI3_FS_A"),
+ STM32_FUNCTION(8, "TIM4_CH1"),
+ STM32_FUNCTION(11, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(13, "PA13"),
+ STM32_FUNCTION(0, "GPIOA13"),
+ STM32_FUNCTION(2, "SPI8_RDY"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "LPTIM2_ETR"),
+ STM32_FUNCTION(6, "MDF1_CKI3"),
+ STM32_FUNCTION(7, "USART2_CTS USART2_NSS"),
+ STM32_FUNCTION(10, "I2C7_SMBA"),
+ STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(14, "PA14"),
+ STM32_FUNCTION(0, "GPIOA14"),
+ STM32_FUNCTION(2, "SPI8_NSS"),
+ STM32_FUNCTION(3, "LPTIM2_CH2"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(6, "MDF1_CCK1"),
+ STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(15, "PA15"),
+ STM32_FUNCTION(0, "GPIOA15"),
+ STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(7, "USART2_RX"),
+ STM32_FUNCTION(10, "I2C7_SDA"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(16, "PB0"),
+ STM32_FUNCTION(0, "GPIOB0"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(8, "TIM16_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(17, "PB1"),
+ STM32_FUNCTION(0, "GPIOB1"),
+ STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "TIM16_CH1N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO1"),
+ STM32_FUNCTION(13, "FMC_NCE4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(18, "PB2"),
+ STM32_FUNCTION(0, "GPIOB2"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(6, "MDF1_CKI3"),
+ STM32_FUNCTION(7, "TIM17_BKIN"),
+ STM32_FUNCTION(8, "TIM16_BKIN"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(19, "PB3"),
+ STM32_FUNCTION(0, "GPIOB3"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(6, "MDF1_SDI3"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO3"),
+ STM32_FUNCTION(13, "FMC_NCE3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(20, "PB4"),
+ STM32_FUNCTION(0, "GPIOB4"),
+ STM32_FUNCTION(3, "SPI2_RDY"),
+ STM32_FUNCTION(4, "UART4_CTS"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(7, "TIM14_CH1"),
+ STM32_FUNCTION(10, "I2C2_SDA"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO4"),
+ STM32_FUNCTION(14, "I3C2_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(21, "PB5"),
+ STM32_FUNCTION(0, "GPIOB5"),
+ STM32_FUNCTION(3, "I2S2_MCK"),
+ STM32_FUNCTION(4, "UART4_RTS UART4_DE"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO5"),
+ STM32_FUNCTION(13, "FMC_AD8 FMC_D8"),
+ STM32_FUNCTION(14, "I3C2_SCL"),
+ STM32_FUNCTION(15, "SDMMC3_D123DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(22, "PB6"),
+ STM32_FUNCTION(0, "GPIOB6"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "UART4_RX"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO6"),
+ STM32_FUNCTION(13, "FMC_AD9 FMC_D9"),
+ STM32_FUNCTION(15, "SDMMC3_D0DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(23, "PB7"),
+ STM32_FUNCTION(0, "GPIOB7"),
+ STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(4, "UART4_TX"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO7"),
+ STM32_FUNCTION(13, "FMC_AD10 FMC_D10"),
+ STM32_FUNCTION(15, "SDMMC3_CDIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(24, "PB8"),
+ STM32_FUNCTION(0, "GPIOB8"),
+ STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(8, "TIM17_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_NCS1"),
+ STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(25, "PB9"),
+ STM32_FUNCTION(0, "GPIOB9"),
+ STM32_FUNCTION(2, "SPI3_RDY"),
+ STM32_FUNCTION(7, "USART1_RTS USART1_DE"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(10, "TIM10_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_DQS"),
+ STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"),
+ STM32_FUNCTION(13, "FMC_AD13 FMC_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(26, "PB10"),
+ STM32_FUNCTION(0, "GPIOB10"),
+ STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(8, "TIM17_CH1N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_CLK"),
+ STM32_FUNCTION(13, "FMC_AD15 FMC_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(27, "PB11"),
+ STM32_FUNCTION(0, "GPIOB11"),
+ STM32_FUNCTION(2, "I2S3_MCK"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_NCLK"),
+ STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"),
+ STM32_FUNCTION(13, "FMC_AD14 FMC_D14"),
+ STM32_FUNCTION(14, "OCTOSPIM_P1_NCS2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(28, "PB12"),
+ STM32_FUNCTION(0, "GPIOB12"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(10, "DSI_TE"),
+ STM32_FUNCTION(11, "SDMMC3_D2"),
+ STM32_FUNCTION(12, "FMC_NWAIT"),
+ STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(29, "PB13"),
+ STM32_FUNCTION(0, "GPIOB13"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(11, "SDMMC3_CK"),
+ STM32_FUNCTION(12, "FMC_AD5 FMC_D5"),
+ STM32_FUNCTION(13, "FMC_AD0 FMC_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(30, "PB14"),
+ STM32_FUNCTION(0, "GPIOB14"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(10, "TIM4_CH2"),
+ STM32_FUNCTION(11, "SDMMC3_D0"),
+ STM32_FUNCTION(12, "FMC_AD7 FMC_D7"),
+ STM32_FUNCTION(13, "FMC_AD2 FMC_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(31, "PB15"),
+ STM32_FUNCTION(0, "GPIOB15"),
+ STM32_FUNCTION(2, "LPTIM1_IN2"),
+ STM32_FUNCTION(3, "SPI5_SCK"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(6, "UART5_RX"),
+ STM32_FUNCTION(8, "TIM3_CH2"),
+ STM32_FUNCTION(9, "TIM5_CH1"),
+ STM32_FUNCTION(11, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_A18"),
+ STM32_FUNCTION(14, "LCD_R4"),
+ STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(32, "PC0"),
+ STM32_FUNCTION(0, "GPIOC0"),
+ STM32_FUNCTION(2, "LPTIM1_CH1"),
+ STM32_FUNCTION(5, "SAI3_MCLK_B"),
+ STM32_FUNCTION(6, "USART6_TX"),
+ STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RMII_REF_CLK"),
+ STM32_FUNCTION(12, "ETH1_MII_TX_CLK"),
+ STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"),
+ STM32_FUNCTION(14, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(33, "PC1"),
+ STM32_FUNCTION(0, "GPIOC1"),
+ STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(7, "USART2_TX"),
+ STM32_FUNCTION(10, "I2C7_SCL"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(34, "PC2"),
+ STM32_FUNCTION(0, "GPIOC2"),
+ STM32_FUNCTION(2, "SPI8_MOSI"),
+ STM32_FUNCTION(3, "LPTIM2_IN1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(6, "MDF1_SDI3"),
+ STM32_FUNCTION(7, "USART2_RTS USART2_DE"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(35, "PC3"),
+ STM32_FUNCTION(0, "GPIOC3"),
+ STM32_FUNCTION(2, "LPTIM1_IN2"),
+ STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(7, "USART6_RTS USART6_DE"),
+ STM32_FUNCTION(8, "FDCAN2_TX"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
+ STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
+ STM32_FUNCTION(14, "LCD_G6"),
+ STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(36, "PC4"),
+ STM32_FUNCTION(0, "GPIOC4"),
+ STM32_FUNCTION(5, "SAI3_FS_B"),
+ STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"),
+ STM32_FUNCTION(13, "ETH1_RGMII_CLK125"),
+ STM32_FUNCTION(14, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(37, "PC5"),
+ STM32_FUNCTION(0, "GPIOC5"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN1"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(11, "ETH2_MDIO"),
+ STM32_FUNCTION(12, "ETH1_MII_COL"),
+ STM32_FUNCTION(13, "FMC_A25"),
+ STM32_FUNCTION(14, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(38, "PC6"),
+ STM32_FUNCTION(0, "GPIOC6"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(9, "TIM8_CH1"),
+ STM32_FUNCTION(11, "ETH2_MDC"),
+ STM32_FUNCTION(12, "ETH1_MII_CRS"),
+ STM32_FUNCTION(13, "FMC_A24"),
+ STM32_FUNCTION(14, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(39, "PC7"),
+ STM32_FUNCTION(0, "GPIOC7"),
+ STM32_FUNCTION(5, "SAI3_SD_B"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"),
+ STM32_FUNCTION(12, "ETH1_MII_TXD2"),
+ STM32_FUNCTION(14, "LCD_B4"),
+ STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(40, "PC8"),
+ STM32_FUNCTION(0, "GPIOC8"),
+ STM32_FUNCTION(2, "LPTIM1_ETR"),
+ STM32_FUNCTION(5, "SAI3_SCK_B"),
+ STM32_FUNCTION(7, "USART6_CTS USART6_NSS"),
+ STM32_FUNCTION(9, "TIM8_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"),
+ STM32_FUNCTION(12, "ETH1_MII_TXD3"),
+ STM32_FUNCTION(14, "LCD_B3"),
+ STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(41, "PC9"),
+ STM32_FUNCTION(0, "GPIOC9"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(5, "SAI2_SCK_A"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(10, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
+ STM32_FUNCTION(12, "USB3DR_OVRCUR"),
+ STM32_FUNCTION(13, "FMC_A22"),
+ STM32_FUNCTION(14, "LCD_G2"),
+ STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(42, "PC10"),
+ STM32_FUNCTION(0, "GPIOC10"),
+ STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(10, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
+ STM32_FUNCTION(12, "USB3DR_VBUSEN"),
+ STM32_FUNCTION(13, "FMC_A23"),
+ STM32_FUNCTION(14, "LCD_G3"),
+ STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(43, "PC11"),
+ STM32_FUNCTION(0, "GPIOC11"),
+ STM32_FUNCTION(2, "LPTIM1_CH1"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(5, "SAI2_MCLK_A"),
+ STM32_FUNCTION(6, "UART5_RTS UART5_DE"),
+ STM32_FUNCTION(7, "USART3_RTS USART3_DE"),
+ STM32_FUNCTION(8, "TIM3_CH1"),
+ STM32_FUNCTION(9, "TIM5_ETR"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
+ STM32_FUNCTION(13, "FMC_NBL1"),
+ STM32_FUNCTION(14, "LCD_R2"),
+ STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(44, "PC12"),
+ STM32_FUNCTION(0, "GPIOC12"),
+ STM32_FUNCTION(2, "LPTIM1_CH2"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
+ STM32_FUNCTION(12, "ETH1_MII_RXD3"),
+ STM32_FUNCTION(14, "LCD_G1"),
+ STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(45, "PC13"),
+ STM32_FUNCTION(0, "GPIOC13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(48, "PD0"),
+ STM32_FUNCTION(0, "GPIOD0"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(4, "SAI1_D2"),
+ STM32_FUNCTION(6, "SAI4_FS_A"),
+ STM32_FUNCTION(7, "UART7_RX"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_CLK"),
+ STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(49, "PD1"),
+ STM32_FUNCTION(0, "GPIOD1"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SAI1_CK2"),
+ STM32_FUNCTION(6, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "UART7_RTS UART7_DE"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_NCLK"),
+ STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"),
+ STM32_FUNCTION(13, "OCTOSPIM_P2_NCS2"),
+ STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(50, "PD2"),
+ STM32_FUNCTION(0, "GPIOD2"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(4, "SAI1_CK1"),
+ STM32_FUNCTION(6, "SAI4_SCK_A"),
+ STM32_FUNCTION(7, "UART7_CTS"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_DQS"),
+ STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"),
+ STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(51, "PD3"),
+ STM32_FUNCTION(0, "GPIOD3"),
+ STM32_FUNCTION(2, "SAI1_MCLK_A"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(4, "SAI1_D1"),
+ STM32_FUNCTION(6, "SAI4_MCLK_A"),
+ STM32_FUNCTION(7, "UART7_TX"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "SDVSEL2"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_NCS1"),
+ STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(52, "PD4"),
+ STM32_FUNCTION(0, "GPIOD4"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "SPI4_MISO"),
+ STM32_FUNCTION(3, "HDP3"),
+ STM32_FUNCTION(4, "SAI1_D3"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(10, "TIM4_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO0"),
+ STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(53, "PD5"),
+ STM32_FUNCTION(0, "GPIOD5"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "SPI4_NSS"),
+ STM32_FUNCTION(3, "HDP4"),
+ STM32_FUNCTION(4, "SAI1_D4"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(10, "TIM4_CH2"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO1"),
+ STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(54, "PD6"),
+ STM32_FUNCTION(0, "GPIOD6"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "SPI4_MOSI"),
+ STM32_FUNCTION(3, "HDP5"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(10, "TIM4_CH3"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO2"),
+ STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(55, "PD7"),
+ STM32_FUNCTION(0, "GPIOD7"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "SPI4_SCK"),
+ STM32_FUNCTION(3, "SPI1_RDY"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(10, "TIM4_CH4"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO3"),
+ STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(56, "PD8"),
+ STM32_FUNCTION(0, "GPIOD8"),
+ STM32_FUNCTION(1, "TRACED4"),
+ STM32_FUNCTION(2, "SPI4_RDY"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(4, "SAI1_FS_A"),
+ STM32_FUNCTION(5, "UART4_CTS"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(10, "TIM4_ETR"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO4"),
+ STM32_FUNCTION(12, "SDMMC1_D7"),
+ STM32_FUNCTION(13, "SDMMC1_D123DIR"),
+ STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(57, "PD9"),
+ STM32_FUNCTION(0, "GPIOD9"),
+ STM32_FUNCTION(1, "TRACED5"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(4, "SAI1_SD_A"),
+ STM32_FUNCTION(5, "UART4_RTS UART4_DE"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO5"),
+ STM32_FUNCTION(12, "SDMMC1_D6"),
+ STM32_FUNCTION(13, "SDMMC1_D0DIR"),
+ STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(58, "PD10"),
+ STM32_FUNCTION(0, "GPIOD10"),
+ STM32_FUNCTION(1, "TRACED6"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(4, "SAI1_SCK_A"),
+ STM32_FUNCTION(5, "UART4_RX"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO6"),
+ STM32_FUNCTION(12, "SDMMC1_D5"),
+ STM32_FUNCTION(13, "SDMMC1_CDIR"),
+ STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(59, "PD11"),
+ STM32_FUNCTION(0, "GPIOD11"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SAI1_MCLK_A"),
+ STM32_FUNCTION(5, "UART4_TX"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO7"),
+ STM32_FUNCTION(12, "SDMMC1_D4"),
+ STM32_FUNCTION(13, "SDMMC1_CKIN"),
+ STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(60, "PD12"),
+ STM32_FUNCTION(0, "GPIOD12"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(10, "TIM4_ETR"),
+ STM32_FUNCTION(11, "SDMMC3_CMD"),
+ STM32_FUNCTION(12, "FMC_AD6 FMC_D6"),
+ STM32_FUNCTION(13, "FMC_AD1 FMC_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(61, "PD13"),
+ STM32_FUNCTION(0, "GPIOD13"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(10, "TIM4_CH4"),
+ STM32_FUNCTION(11, "SDMMC3_D1"),
+ STM32_FUNCTION(12, "FMC_AD11 FMC_D11"),
+ STM32_FUNCTION(13, "FMC_NWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(62, "PD14"),
+ STM32_FUNCTION(0, "GPIOD14"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "I2C7_SDA"),
+ STM32_FUNCTION(12, "FMC_AD4 FMC_D4"),
+ STM32_FUNCTION(13, "SDMMC3_D3"),
+ STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(63, "PD15"),
+ STM32_FUNCTION(0, "GPIOD15"),
+ STM32_FUNCTION(2, "SPI1_RDY"),
+ STM32_FUNCTION(6, "DSI_TE"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "TIM5_ETR"),
+ STM32_FUNCTION(11, "I2C7_SCL"),
+ STM32_FUNCTION(12, "FMC_AD3 FMC_D3"),
+ STM32_FUNCTION(13, "SDMMC3_CKIN"),
+ STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(64, "PE0"),
+ STM32_FUNCTION(0, "GPIOE0"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "LPTIM2_CH1"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPI3_RDY"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(11, "SDMMC1_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(65, "PE1"),
+ STM32_FUNCTION(0, "GPIOE1"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "LPTIM2_CH2"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(4, "I2S3_MCK"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(11, "SDMMC1_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(66, "PE2"),
+ STM32_FUNCTION(0, "GPIOE2"),
+ STM32_FUNCTION(2, "LPTIM2_ETR"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(11, "SDMMC1_CMD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(67, "PE3"),
+ STM32_FUNCTION(0, "GPIOE3"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(3, "SPI1_RDY"),
+ STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "SDMMC1_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(68, "PE4"),
+ STM32_FUNCTION(0, "GPIOE4"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "LPTIM2_IN1"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(7, "USART3_CTS USART3_NSS"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(11, "SDMMC1_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(69, "PE5"),
+ STM32_FUNCTION(0, "GPIOE5"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "LPTIM2_IN2"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(7, "USART3_RTS USART3_DE"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(11, "SDMMC1_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(70, "PE6"),
+ STM32_FUNCTION(0, "GPIOE6"),
+ STM32_FUNCTION(2, "SPI4_RDY"),
+ STM32_FUNCTION(5, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(12, "FMC_AD1 FMC_D1"),
+ STM32_FUNCTION(13, "SDMMC2_D6"),
+ STM32_FUNCTION(14, "SDMMC2_D0DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(71, "PE7"),
+ STM32_FUNCTION(0, "GPIOE7"),
+ STM32_FUNCTION(4, "SAI4_D4"),
+ STM32_FUNCTION(5, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(11, "TIM14_CH1"),
+ STM32_FUNCTION(12, "FMC_AD2 FMC_D2"),
+ STM32_FUNCTION(13, "SDMMC2_D7"),
+ STM32_FUNCTION(14, "SDMMC2_D123DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(72, "PE8"),
+ STM32_FUNCTION(0, "GPIOE8"),
+ STM32_FUNCTION(2, "SPI4_MOSI"),
+ STM32_FUNCTION(4, "SAI4_CK1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_A"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(12, "FMC_A17 FMC_ALE"),
+ STM32_FUNCTION(13, "SDMMC2_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(73, "PE9"),
+ STM32_FUNCTION(0, "GPIOE9"),
+ STM32_FUNCTION(2, "SPI4_MISO"),
+ STM32_FUNCTION(4, "SAI4_D2"),
+ STM32_FUNCTION(5, "SAI4_FS_A"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(12, "FMC_AD0 FMC_D0"),
+ STM32_FUNCTION(13, "SDMMC2_D5"),
+ STM32_FUNCTION(14, "SDMMC2_CDIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(74, "PE10"),
+ STM32_FUNCTION(0, "GPIOE10"),
+ STM32_FUNCTION(2, "SPI4_SCK"),
+ STM32_FUNCTION(4, "SAI4_D1"),
+ STM32_FUNCTION(5, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(11, "FMC_NE3"),
+ STM32_FUNCTION(12, "FMC_NCE2"),
+ STM32_FUNCTION(13, "SDMMC2_D4"),
+ STM32_FUNCTION(14, "SDMMC2_CKIN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(75, "PE11"),
+ STM32_FUNCTION(0, "GPIOE11"),
+ STM32_FUNCTION(4, "SAI4_D3"),
+ STM32_FUNCTION(5, "SAI1_FS_A"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(12, "FMC_A16 FMC_CLE"),
+ STM32_FUNCTION(13, "SDMMC2_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(76, "PE12"),
+ STM32_FUNCTION(0, "GPIOE12"),
+ STM32_FUNCTION(2, "SPI4_NSS"),
+ STM32_FUNCTION(4, "SAI4_CK2"),
+ STM32_FUNCTION(5, "SAI4_SCK_A"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(7, "USART1_RTS USART1_DE"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(11, "FMC_NE2"),
+ STM32_FUNCTION(12, "FMC_NCE1"),
+ STM32_FUNCTION(13, "SDMMC2_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(77, "PE13"),
+ STM32_FUNCTION(0, "GPIOE13"),
+ STM32_FUNCTION(5, "SAI1_SD_A"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(12, "FMC_RNB"),
+ STM32_FUNCTION(13, "SDMMC2_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(78, "PE14"),
+ STM32_FUNCTION(0, "GPIOE14"),
+ STM32_FUNCTION(5, "SAI1_MCLK_A"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(12, "FMC_NWE"),
+ STM32_FUNCTION(13, "SDMMC2_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(79, "PE15"),
+ STM32_FUNCTION(0, "GPIOE15"),
+ STM32_FUNCTION(5, "SAI1_SCK_A"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(12, "FMC_NOE"),
+ STM32_FUNCTION(13, "SDMMC2_CMD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(80, "PF0"),
+ STM32_FUNCTION(0, "GPIOF0"),
+ STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(8, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM12_CH2"),
+ STM32_FUNCTION(10, "I2C2_SDA"),
+ STM32_FUNCTION(11, "ETH1_MDC"),
+ STM32_FUNCTION(12, "ETH2_MII_CRS"),
+ STM32_FUNCTION(14, "I3C2_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(81, "PF1"),
+ STM32_FUNCTION(0, "GPIOF1"),
+ STM32_FUNCTION(2, "SPI8_MISO"),
+ STM32_FUNCTION(3, "LPTIM2_IN2"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(82, "PF2"),
+ STM32_FUNCTION(0, "GPIOF2"),
+ STM32_FUNCTION(3, "SPI3_RDY"),
+ STM32_FUNCTION(9, "TIM12_CH1"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(11, "ETH1_MDIO"),
+ STM32_FUNCTION(12, "ETH2_MII_COL"),
+ STM32_FUNCTION(13, "FMC_NE4"),
+ STM32_FUNCTION(14, "I3C2_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(83, "PF3"),
+ STM32_FUNCTION(0, "GPIOF3"),
+ STM32_FUNCTION(5, "SAI2_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(8, "TIM3_CH4"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_A20"),
+ STM32_FUNCTION(14, "LCD_R6"),
+ STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(84, "PF4"),
+ STM32_FUNCTION(0, "GPIOF4"),
+ STM32_FUNCTION(2, "RTC_OUT2"),
+ STM32_FUNCTION(5, "SAI3_SCK_A"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(8, "TIM4_CH4"),
+ STM32_FUNCTION(9, "ETH1_MDC"),
+ STM32_FUNCTION(10, "ETH2_CLK"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(12, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(14, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(85, "PF5"),
+ STM32_FUNCTION(0, "GPIOF5"),
+ STM32_FUNCTION(5, "SAI3_MCLK_A"),
+ STM32_FUNCTION(7, "USART6_TX"),
+ STM32_FUNCTION(8, "TIM4_CH3"),
+ STM32_FUNCTION(9, "ETH1_MDIO"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_PHY_INTN"),
+ STM32_FUNCTION(12, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(14, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(86, "PF6"),
+ STM32_FUNCTION(0, "GPIOF6"),
+ STM32_FUNCTION(2, "RTC_OUT2"),
+ STM32_FUNCTION(4, "SAI3_MCLK_B"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(8, "TIM12_CH1"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
+ STM32_FUNCTION(14, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(87, "PF7"),
+ STM32_FUNCTION(0, "GPIOF7"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN1"),
+ STM32_FUNCTION(5, "SAI3_SD_A"),
+ STM32_FUNCTION(8, "TIM2_ETR"),
+ STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"),
+ STM32_FUNCTION(12, "ETH2_MII_TX_CLK"),
+ STM32_FUNCTION(14, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(88, "PF8"),
+ STM32_FUNCTION(0, "GPIOF8"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(4, "SAI3_SCK_B"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(8, "TIM12_CH2"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_RGMII_CLK125"),
+ STM32_FUNCTION(12, "ETH2_MII_RX_ER"),
+ STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RMII_CRS_DV"),
+ STM32_FUNCTION(14, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(89, "PF9"),
+ STM32_FUNCTION(0, "GPIOF9"),
+ STM32_FUNCTION(4, "SAI3_SD_B"),
+ STM32_FUNCTION(5, "SAI2_SD_A"),
+ STM32_FUNCTION(8, "TIM2_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
+ STM32_FUNCTION(12, "ETH2_MDIO"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(90, "PF10"),
+ STM32_FUNCTION(0, "GPIOF10"),
+ STM32_FUNCTION(2, "MCO2"),
+ STM32_FUNCTION(3, "SPI3_RDY"),
+ STM32_FUNCTION(5, "SAI2_MCLK_A"),
+ STM32_FUNCTION(8, "TIM2_CH3"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(91, "PF11"),
+ STM32_FUNCTION(0, "GPIOF11"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(5, "SAI2_SCK_A"),
+ STM32_FUNCTION(8, "TIM2_CH4"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(92, "PF12"),
+ STM32_FUNCTION(0, "GPIOF12"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(9, "TIM5_CH1"),
+ STM32_FUNCTION(14, "LCD_CLK"),
+ STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(93, "PF13"),
+ STM32_FUNCTION(0, "GPIOF13"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(3, "AUDIOCLK"),
+ STM32_FUNCTION(4, "USART6_TX"),
+ STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(7, "USART3_CTS USART3_NSS"),
+ STM32_FUNCTION(9, "TIM3_CH3"),
+ STM32_FUNCTION(14, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(94, "PF14"),
+ STM32_FUNCTION(0, "GPIOF14"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(4, "USART6_RX"),
+ STM32_FUNCTION(7, "USART3_RTS USART3_DE"),
+ STM32_FUNCTION(9, "TIM3_CH4"),
+ STM32_FUNCTION(14, "LCD_R3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(95, "PF15"),
+ STM32_FUNCTION(0, "GPIOF15"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI2_RDY"),
+ STM32_FUNCTION(4, "USART6_CTS USART6_NSS"),
+ STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(8, "TIM2_CH2"),
+ STM32_FUNCTION(9, "TIM3_ETR"),
+ STM32_FUNCTION(14, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(96, "PG0"),
+ STM32_FUNCTION(0, "GPIOG0"),
+ STM32_FUNCTION(2, "LPTIM1_IN1"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"),
+ STM32_FUNCTION(12, "ETH1_MII_RXD2"),
+ STM32_FUNCTION(14, "LCD_G5"),
+ STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(97, "PG1"),
+ STM32_FUNCTION(0, "GPIOG1"),
+ STM32_FUNCTION(2, "LPTIM1_IN1"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(5, "SAI2_SD_A"),
+ STM32_FUNCTION(6, "UART5_CTS"),
+ STM32_FUNCTION(7, "USART3_CTS USART3_NSS"),
+ STM32_FUNCTION(9, "TIM5_CH4"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_ER"),
+ STM32_FUNCTION(12, "ETH2_MII_RXD3"),
+ STM32_FUNCTION(13, "FMC_NBL0"),
+ STM32_FUNCTION(14, "LCD_VSYNC"),
+ STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(98, "PG2"),
+ STM32_FUNCTION(0, "GPIOG2"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(5, "SAI2_FS_A"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(9, "TIM5_CH3"),
+ STM32_FUNCTION(11, "ETH2_MII_TX_CLK"),
+ STM32_FUNCTION(12, "ETH2_RGMII_CLK125"),
+ STM32_FUNCTION(13, "FMC_CLK"),
+ STM32_FUNCTION(14, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(99, "PG3"),
+ STM32_FUNCTION(0, "GPIOG3"),
+ STM32_FUNCTION(2, "LPTIM1_ETR"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(5, "SAI2_FS_B"),
+ STM32_FUNCTION(8, "TIM3_CH3"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(10, "ETH2_CLK"),
+ STM32_FUNCTION(11, "ETH2_PHY_INTN"),
+ STM32_FUNCTION(13, "FMC_A19"),
+ STM32_FUNCTION(14, "LCD_R5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(100, "PG4"),
+ STM32_FUNCTION(0, "GPIOG4"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SAI3_FS_B"),
+ STM32_FUNCTION(8, "LPTIM4_IN1"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(12, "ETH2_MDC"),
+ STM32_FUNCTION(13, "FMC_A21"),
+ STM32_FUNCTION(14, "LCD_R7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(101, "PG5"),
+ STM32_FUNCTION(0, "GPIOG5"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "HDP3"),
+ STM32_FUNCTION(4, "USART6_RTS USART6_DE"),
+ STM32_FUNCTION(8, "TIM2_CH3"),
+ STM32_FUNCTION(14, "LCD_R5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(102, "PG6"),
+ STM32_FUNCTION(0, "GPIOG6"),
+ STM32_FUNCTION(1, "TRACED4"),
+ STM32_FUNCTION(2, "HDP4"),
+ STM32_FUNCTION(3, "SPI5_SCK"),
+ STM32_FUNCTION(4, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(8, "TIM2_CH4"),
+ STM32_FUNCTION(14, "LCD_R6"),
+ STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(103, "PG7"),
+ STM32_FUNCTION(0, "GPIOG7"),
+ STM32_FUNCTION(1, "TRACED5"),
+ STM32_FUNCTION(2, "HDP5"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(9, "TIM5_ETR"),
+ STM32_FUNCTION(14, "LCD_R7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(104, "PG8"),
+ STM32_FUNCTION(0, "GPIOG8"),
+ STM32_FUNCTION(1, "TRACED6"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(4, "SPI1_RDY"),
+ STM32_FUNCTION(5, "USART6_CK"),
+ STM32_FUNCTION(6, "UART5_RTS UART5_DE"),
+ STM32_FUNCTION(9, "TIM5_CH3"),
+ STM32_FUNCTION(14, "LCD_G2"),
+ STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(105, "PG9"),
+ STM32_FUNCTION(0, "GPIOG9"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(6, "UART5_TX"),
+ STM32_FUNCTION(9, "TIM5_CH4"),
+ STM32_FUNCTION(14, "LCD_G3"),
+ STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(106, "PG10"),
+ STM32_FUNCTION(0, "GPIOG10"),
+ STM32_FUNCTION(1, "TRACED8"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(6, "UART5_RX"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(14, "LCD_G4"),
+ STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(107, "PG11"),
+ STM32_FUNCTION(0, "GPIOG11"),
+ STM32_FUNCTION(1, "TRACED9"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(14, "LCD_G5"),
+ STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(108, "PG12"),
+ STM32_FUNCTION(0, "GPIOG12"),
+ STM32_FUNCTION(1, "TRACED10"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(14, "LCD_G6"),
+ STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(109, "PG13"),
+ STM32_FUNCTION(0, "GPIOG13"),
+ STM32_FUNCTION(1, "TRACED11"),
+ STM32_FUNCTION(2, "HDP3"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(10, "I2C1_SCL"),
+ STM32_FUNCTION(11, "I3C1_SCL"),
+ STM32_FUNCTION(14, "LCD_G7"),
+ STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(110, "PG14"),
+ STM32_FUNCTION(0, "GPIOG14"),
+ STM32_FUNCTION(1, "TRACED12"),
+ STM32_FUNCTION(2, "HDP4"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(14, "LCD_B1"),
+ STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(111, "PG15"),
+ STM32_FUNCTION(0, "GPIOG15"),
+ STM32_FUNCTION(1, "TRACED13"),
+ STM32_FUNCTION(2, "HDP5"),
+ STM32_FUNCTION(4, "LPTIM1_CH2"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(14, "LCD_B2"),
+ STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(114, "PH2"),
+ STM32_FUNCTION(0, "GPIOH2"),
+ STM32_FUNCTION(2, "LPTIM2_CH1"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(8, "TIM16_CH1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(115, "PH3"),
+ STM32_FUNCTION(0, "GPIOH3"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(7, "UART7_RX"),
+ STM32_FUNCTION(8, "TIM17_CH1N"),
+ STM32_FUNCTION(10, "TIM5_CH3"),
+ STM32_FUNCTION(11, "I2C7_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(116, "PH4"),
+ STM32_FUNCTION(0, "GPIOH4"),
+ STM32_FUNCTION(7, "UART7_TX"),
+ STM32_FUNCTION(8, "TIM17_BKIN"),
+ STM32_FUNCTION(10, "TIM5_CH2"),
+ STM32_FUNCTION(11, "LCD_R0"),
+ STM32_FUNCTION(12, "USB3DR_OVRCUR"),
+ STM32_FUNCTION(13, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(117, "PH5"),
+ STM32_FUNCTION(0, "GPIOH5"),
+ STM32_FUNCTION(5, "SAI2_FS_A"),
+ STM32_FUNCTION(8, "TIM2_CH1"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(11, "LCD_G1"),
+ STM32_FUNCTION(12, "USB3DR_VBUSEN"),
+ STM32_FUNCTION(13, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(118, "PH6"),
+ STM32_FUNCTION(0, "GPIOH6"),
+ STM32_FUNCTION(2, "LPTIM2_IN2"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(8, "TIM16_CH1N"),
+ STM32_FUNCTION(11, "I2C1_SMBA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(119, "PH7"),
+ STM32_FUNCTION(0, "GPIOH7"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(5, "UART4_TX"),
+ STM32_FUNCTION(7, "UART7_RTS UART7_DE"),
+ STM32_FUNCTION(8, "TIM17_CH1"),
+ STM32_FUNCTION(10, "TIM5_CH4"),
+ STM32_FUNCTION(11, "I2C7_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(120, "PH8"),
+ STM32_FUNCTION(0, "GPIOH8"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(5, "UART4_RX"),
+ STM32_FUNCTION(7, "UART7_CTS"),
+ STM32_FUNCTION(10, "TIM5_CH1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(121, "PH9"),
+ STM32_FUNCTION(0, "GPIOH9"),
+ STM32_FUNCTION(5, "SAI3_MCLK_A"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(11, "ETH1_RGMII_CLK125"),
+ STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(122, "PH10"),
+ STM32_FUNCTION(0, "GPIOH10"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(5, "SAI3_SCK_A"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(10, "ETH2_MDC"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(123, "PH11"),
+ STM32_FUNCTION(0, "GPIOH11"),
+ STM32_FUNCTION(5, "SAI3_FS_A"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(10, "ETH2_MDIO"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(124, "PH12"),
+ STM32_FUNCTION(0, "GPIOH12"),
+ STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(125, "PH13"),
+ STM32_FUNCTION(0, "GPIOH13"),
+ STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(128, "PI0"),
+ STM32_FUNCTION(0, "GPIOI0"),
+ STM32_FUNCTION(1, "TRACED14"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(4, "LPTIM1_IN1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(14, "LCD_B3"),
+ STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(129, "PI1"),
+ STM32_FUNCTION(0, "GPIOI1"),
+ STM32_FUNCTION(1, "TRACED15"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "I2C1_SDA"),
+ STM32_FUNCTION(11, "I3C1_SDA"),
+ STM32_FUNCTION(14, "LCD_B4"),
+ STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(130, "PI2"),
+ STM32_FUNCTION(0, "GPIOI2"),
+ STM32_FUNCTION(4, "LPTIM1_ETR"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(7, "USART1_RTS USART1_DE"),
+ STM32_FUNCTION(9, "TIM8_CH1"),
+ STM32_FUNCTION(14, "LCD_B5"),
+ STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(131, "PI3"),
+ STM32_FUNCTION(0, "GPIOI3"),
+ STM32_FUNCTION(4, "LPTIM1_IN2"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(7, "USART1_CTS USART1_NSS"),
+ STM32_FUNCTION(9, "TIM8_CH2"),
+ STM32_FUNCTION(14, "LCD_B6"),
+ STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(132, "PI4"),
+ STM32_FUNCTION(0, "GPIOI4"),
+ STM32_FUNCTION(4, "LPTIM1_CH1"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(14, "LCD_B7"),
+ STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(133, "PI5"),
+ STM32_FUNCTION(0, "GPIOI5"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(6, "UART5_CTS"),
+ STM32_FUNCTION(9, "TIM5_CH2"),
+ STM32_FUNCTION(14, "LCD_DE"),
+ STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(134, "PI6"),
+ STM32_FUNCTION(0, "GPIOI6"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(8, "TIM2_ETR"),
+ STM32_FUNCTION(9, "TIM3_CH1"),
+ STM32_FUNCTION(14, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(135, "PI7"),
+ STM32_FUNCTION(0, "GPIOI7"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(8, "TIM2_CH1"),
+ STM32_FUNCTION(9, "TIM3_CH2"),
+ STM32_FUNCTION(14, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(136, "PI8"),
+ STM32_FUNCTION(0, "GPIOI8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(137, "PI9"),
+ STM32_FUNCTION(0, "GPIOI9"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(5, "FDCAN2_TX"),
+ STM32_FUNCTION(9, "TIM16_BKIN"),
+ STM32_FUNCTION(10, "SDVSEL2"),
+ STM32_FUNCTION(11, "FMC_NWAIT"),
+ STM32_FUNCTION(13, "DSI_TE"),
+ STM32_FUNCTION(14, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(138, "PI10"),
+ STM32_FUNCTION(0, "GPIOI10"),
+ STM32_FUNCTION(2, "SAI1_SCK_A"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(5, "FDCAN2_RX"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(9, "TIM4_CH1"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
+ STM32_FUNCTION(14, "DSI_TE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(139, "PI11"),
+ STM32_FUNCTION(0, "GPIOI11"),
+ STM32_FUNCTION(3, "I2S2_MCK"),
+ STM32_FUNCTION(10, "TIM4_CH3"),
+ STM32_FUNCTION(11, "SDMMC3_D3"),
+ STM32_FUNCTION(12, "FMC_AD15 FMC_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static const struct stm32_desc_pin stm32mp235_z_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(400, "PZ0"),
+ STM32_FUNCTION(0, "GPIOZ0"),
+ STM32_FUNCTION(3, "LPTIM3_IN1"),
+ STM32_FUNCTION(4, "SPI8_MOSI"),
+ STM32_FUNCTION(5, "TIM8_CH1"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM5_OUT"),
+ STM32_FUNCTION(9, "I2C8_SDA"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(12, "I3C4_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(401, "PZ1"),
+ STM32_FUNCTION(0, "GPIOZ1"),
+ STM32_FUNCTION(3, "LPTIM3_CH1"),
+ STM32_FUNCTION(4, "SPI8_MISO"),
+ STM32_FUNCTION(5, "TIM8_CH2"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM5_ETR"),
+ STM32_FUNCTION(9, "I2C8_SCL"),
+ STM32_FUNCTION(10, "I2C8_SMBA"),
+ STM32_FUNCTION(12, "I3C4_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(402, "PZ2"),
+ STM32_FUNCTION(0, "GPIOZ2"),
+ STM32_FUNCTION(3, "LPTIM3_CH1"),
+ STM32_FUNCTION(4, "SPI8_SCK"),
+ STM32_FUNCTION(7, "LPUART1_RTS LPUART1_DE"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "I2C8_SCL"),
+ STM32_FUNCTION(12, "I3C4_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(403, "PZ3"),
+ STM32_FUNCTION(0, "GPIOZ3"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(3, "LPTIM3_ETR"),
+ STM32_FUNCTION(4, "SPI8_NSS"),
+ STM32_FUNCTION(7, "LPUART1_CTS"),
+ STM32_FUNCTION(8, "LPTIM4_IN1"),
+ STM32_FUNCTION(9, "I2C8_SDA"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(12, "I3C4_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(404, "PZ4"),
+ STM32_FUNCTION(0, "GPIOZ4"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(3, "MCO2"),
+ STM32_FUNCTION(4, "SPI8_RDY"),
+ STM32_FUNCTION(5, "MDF1_CCK1"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM4_CH1"),
+ STM32_FUNCTION(9, "I2C8_SCL"),
+ STM32_FUNCTION(12, "I3C4_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(405, "PZ5"),
+ STM32_FUNCTION(0, "GPIOZ5"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "LPTIM3_ETR"),
+ STM32_FUNCTION(4, "SPI8_SCK"),
+ STM32_FUNCTION(7, "LPUART1_RTS LPUART1_DE"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(406, "PZ6"),
+ STM32_FUNCTION(0, "GPIOZ6"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(4, "SPI8_NSS"),
+ STM32_FUNCTION(5, "TIM8_CH3"),
+ STM32_FUNCTION(7, "LPUART1_CTS"),
+ STM32_FUNCTION(8, "LPTIM5_OUT"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(407, "PZ7"),
+ STM32_FUNCTION(0, "GPIOZ7"),
+ STM32_FUNCTION(4, "SPI8_MOSI"),
+ STM32_FUNCTION(5, "MDF1_CCK1"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(408, "PZ8"),
+ STM32_FUNCTION(0, "GPIOZ8"),
+ STM32_FUNCTION(3, "LPTIM3_IN1"),
+ STM32_FUNCTION(4, "SPI8_MISO"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM4_CH1"),
+ STM32_FUNCTION(9, "I2C8_SMBA"),
+ STM32_FUNCTION(10, "LPTIM5_ETR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(409, "PZ9"),
+ STM32_FUNCTION(0, "GPIOZ9"),
+ STM32_FUNCTION(2, "MCO2"),
+ STM32_FUNCTION(4, "SPI8_RDY"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "I2C8_SDA"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(12, "I3C4_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static struct stm32_pinctrl_match_data stm32mp235_match_data = {
+ .pins = stm32mp235_pins,
+ .npins = ARRAY_SIZE(stm32mp235_pins),
+ .io_sync_control = true,
+ .secure_control = true,
+ .rif_control = true,
+};
+
+static struct stm32_pinctrl_match_data stm32mp235_z_match_data = {
+ .pins = stm32mp235_z_pins,
+ .npins = ARRAY_SIZE(stm32mp235_z_pins),
+ .io_sync_control = true,
+ .secure_control = true,
+ .rif_control = true,
+};
+
+static const struct of_device_id stm32mp235_pctrl_match[] = {
+ {
+ .compatible = "st,stm32mp235-pinctrl",
+ .data = &stm32mp235_match_data,
+ },
+ {
+ .compatible = "st,stm32mp235-z-pinctrl",
+ .data = &stm32mp235_z_match_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, stm32mp235_pctrl_match);
+
+static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(stm32_pinctrl_suspend, stm32_pinctrl_resume)
+};
+
+static struct platform_driver stm32mp235_pinctrl_driver = {
+ .probe = stm32_pctl_probe,
+ .driver = {
+ .name = "stm32mp235-pinctrl",
+ .of_match_table = stm32mp235_pctrl_match,
+ .pm = &stm32_pinctrl_dev_pm_ops,
+ },
+};
+module_platform_driver(stm32mp235_pinctrl_driver);
+
+MODULE_AUTHOR("Clément Le Goffic <clement.legoffic@foss.st.com>");
+MODULE_DESCRIPTION("STM32MP235 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 13/14] dt-bindings: pinctrl: stm32: add support for stm32mp235
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (11 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 12/14] pinctrl: stm32: Add stm32mp235 pinctrl support Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-23 8:52 ` Krzysztof Kozlowski
2024-10-22 15:56 ` [PATCH 14/14] pinctrl: stm32: Add new package to stm32mp257 pinctrl support Antonio Borneo
2024-10-24 22:20 ` [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Linus Walleij
14 siblings, 1 reply; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
Add the compatibles st,stm32mp235-pinctrl and st,stm32mp235-z-pinctrl.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index 0a2d644dbece3..d7ee43fc5167c 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -29,6 +29,8 @@ properties:
- st,stm32mp157-z-pinctrl
- st,stm32mp215-pinctrl
- st,stm32mp215-z-pinctrl
+ - st,stm32mp235-pinctrl
+ - st,stm32mp235-z-pinctrl
- st,stm32mp257-pinctrl
- st,stm32mp257-z-pinctrl
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 14/14] pinctrl: stm32: Add new package to stm32mp257 pinctrl support
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (12 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 13/14] dt-bindings: pinctrl: stm32: add support for stm32mp235 Antonio Borneo
@ 2024-10-22 15:56 ` Antonio Borneo
2024-10-24 22:20 ` [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Linus Walleij
14 siblings, 0 replies; 28+ messages in thread
From: Antonio Borneo @ 2024-10-22 15:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel
Cc: Antonio Borneo, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
From: Clément Le Goffic <clement.legoffic@foss.st.com>
Add the package 'AJ' to the list of supported SoC packages for
stm32mp257 pinctrl.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.h | 1 +
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 288 ++++++++++-----------
2 files changed, 145 insertions(+), 144 deletions(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 1d576aad029d1..52ade2244ec3e 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -26,6 +26,7 @@
#define STM32MP_PKG_AC BIT(2)
#define STM32MP_PKG_AD BIT(3)
#define STM32MP_PKG_AI BIT(8)
+#define STM32MP_PKG_AJ BIT(9)
#define STM32MP_PKG_AK BIT(10)
#define STM32MP_PKG_AL BIT(11)
#define STM32MP_PKG_AM BIT(12)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
index 6709bddd97186..8e332bb88737b 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
@@ -13,7 +13,7 @@
static const struct stm32_desc_pin stm32mp257_pins[] = {
STM32_PIN_PKG(
PINCTRL_PIN(0, "PA0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "LPTIM1_CH2"),
STM32_FUNCTION(3, "SPI5_RDY"),
@@ -31,7 +31,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(1, "PA1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(3, "SPI6_MISO"),
STM32_FUNCTION(5, "SAI3_SD_A"),
@@ -48,7 +48,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(2, "PA2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "LPTIM2_IN1"),
STM32_FUNCTION(3, "SPI7_MISO"),
@@ -64,7 +64,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(3, "PA3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "LPTIM2_ETR"),
STM32_FUNCTION(3, "SPI7_MOSI"),
@@ -81,7 +81,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(4, "PA4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(7, "USART2_TX"),
STM32_FUNCTION(8, "FDCAN2_TX"),
@@ -94,7 +94,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(5, "PA5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(4, "SPI4_MOSI"),
STM32_FUNCTION(5, "SAI2_MCLK_B"),
@@ -111,7 +111,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(6, "PA6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(4, "SPI4_SCK"),
STM32_FUNCTION(5, "SAI2_FS_B"),
@@ -128,7 +128,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(7, "PA7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(3, "AUDIOCLK"),
STM32_FUNCTION(4, "SPI6_RDY"),
@@ -148,7 +148,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(8, "PA8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(2, "LPTIM2_CH2"),
STM32_FUNCTION(3, "SPI7_NSS"),
@@ -163,7 +163,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(9, "PA9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(4, "SPI4_NSS"),
STM32_FUNCTION(5, "SAI2_SCK_B"),
@@ -179,7 +179,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(10, "PA10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(4, "SPI4_MISO"),
STM32_FUNCTION(5, "SAI2_SD_B"),
@@ -195,7 +195,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(11, "PA11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "SPI8_SCK"),
STM32_FUNCTION(3, "LPTIM2_CH1"),
@@ -207,7 +207,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(12, "PA12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(3, "SPI6_MOSI"),
STM32_FUNCTION(5, "SAI3_FS_A"),
@@ -220,7 +220,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(13, "PA13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(2, "SPI8_RDY"),
STM32_FUNCTION(3, "I2S3_MCK"),
@@ -234,7 +234,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(14, "PA14"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(2, "SPI8_NSS"),
STM32_FUNCTION(3, "LPTIM2_CH2"),
@@ -246,7 +246,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(15, "PA15"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(7, "USART2_RX"),
@@ -257,7 +257,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(16, "PB0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "USART1_CK"),
@@ -269,7 +269,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(17, "PB1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "TIM16_CH1N"),
@@ -281,7 +281,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(18, "PB2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(6, "MDF1_CKI3"),
@@ -294,7 +294,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(19, "PB3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(6, "MDF1_SDI3"),
@@ -306,7 +306,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(20, "PB4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(3, "SPI2_RDY"),
STM32_FUNCTION(4, "UART4_CTS"),
@@ -322,7 +322,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(21, "PB5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(3, "I2S2_MCK"),
STM32_FUNCTION(4, "UART4_RTS"),
@@ -339,7 +339,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(22, "PB6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(4, "UART4_RX"),
@@ -353,7 +353,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(23, "PB7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(4, "UART4_TX"),
@@ -368,7 +368,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(24, "PB8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(5, "PCIE_CLKREQN"),
@@ -382,7 +382,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(25, "PB9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(2, "SPI3_RDY"),
STM32_FUNCTION(7, "USART1_RTS"),
@@ -397,7 +397,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(26, "PB10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(7, "USART1_RX"),
@@ -409,7 +409,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(27, "PB11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "I2S3_MCK"),
STM32_FUNCTION(7, "USART1_CTS"),
@@ -425,7 +425,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(28, "PB12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(6, "UART8_CTS"),
STM32_FUNCTION(8, "TIM13_CH1"),
@@ -438,7 +438,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(29, "PB13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(3, "SPI7_SCK"),
STM32_FUNCTION(5, "SAI1_SD_B"),
@@ -451,7 +451,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(30, "PB14"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(6, "MDF1_CKI7"),
@@ -465,7 +465,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(31, "PB15"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(3, "SPI5_SCK"),
@@ -483,7 +483,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(32, "PC0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(2, "LPTIM1_CH1"),
STM32_FUNCTION(4, "SPI6_SCK"),
@@ -499,7 +499,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(33, "PC1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(7, "USART2_TX"),
@@ -510,7 +510,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(34, "PC2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(2, "SPI8_MOSI"),
STM32_FUNCTION(3, "LPTIM2_IN1"),
@@ -523,7 +523,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(35, "PC3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
@@ -539,7 +539,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(36, "PC4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(4, "SPI6_MISO"),
STM32_FUNCTION(5, "SAI3_FS_B"),
@@ -551,7 +551,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(37, "PC5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(3, "SPDIFRX1_IN1"),
STM32_FUNCTION(6, "MDF1_SDI1"),
@@ -567,7 +567,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(38, "PC6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(2, "RTC_REFIN"),
STM32_FUNCTION(3, "SPDIFRX1_IN0"),
@@ -584,7 +584,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(39, "PC7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(4, "SPI6_MOSI"),
STM32_FUNCTION(5, "SAI3_SD_B"),
@@ -598,7 +598,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(40, "PC8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(4, "SPI6_NSS"),
@@ -614,7 +614,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(41, "PC9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
@@ -632,7 +632,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(42, "PC10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(8, "LPTIM4_ETR"),
@@ -648,7 +648,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(43, "PC11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(2, "LPTIM1_CH1"),
STM32_FUNCTION(3, "SPI5_NSS"),
@@ -666,7 +666,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(44, "PC12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(2, "LPTIM1_CH2"),
STM32_FUNCTION(4, "I3C3_SCL"),
@@ -682,14 +682,14 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(45, "PC13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(48, "PD0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(2, "HDP0"),
@@ -706,7 +706,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(49, "PD1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(2, "HDP1"),
STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
@@ -725,7 +725,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(50, "PD2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(2, "HDP2"),
STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
@@ -743,7 +743,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(51, "PD3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(2, "SAI1_MCLK_A"),
STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
@@ -760,7 +760,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(52, "PD4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "SPI4_MISO"),
@@ -776,7 +776,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(53, "PD5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "SPI4_NSS"),
@@ -792,7 +792,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(54, "PD6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "SPI4_MOSI"),
@@ -808,7 +808,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(55, "PD7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "SPI4_SCK"),
@@ -824,7 +824,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(56, "PD8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "SPI4_RDY"),
@@ -843,7 +843,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(57, "PD9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(2, "HDP6"),
@@ -861,7 +861,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(58, "PD10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(2, "HDP7"),
@@ -880,7 +880,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(59, "PD11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
@@ -899,7 +899,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(60, "PD12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(2, "SPI7_MISO"),
STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
@@ -914,7 +914,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(61, "PD13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(6, "MDF1_SDI7"),
@@ -928,7 +928,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(62, "PD14"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "I2S1_MCK"),
STM32_FUNCTION(8, "FDCAN1_RX"),
@@ -942,7 +942,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(63, "PD15"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(2, "SPI1_RDY"),
STM32_FUNCTION(6, "DSI_TE"),
@@ -959,7 +959,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(64, "PE0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "LPTIM2_CH1"),
@@ -972,7 +972,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(65, "PE1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "LPTIM2_CH2"),
@@ -985,7 +985,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(66, "PE2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(2, "LPTIM2_ETR"),
STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
@@ -998,7 +998,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(67, "PE3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(3, "SPI1_RDY"),
@@ -1012,7 +1012,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(68, "PE4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "LPTIM2_IN1"),
@@ -1027,7 +1027,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(69, "PE5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "LPTIM2_IN2"),
@@ -1042,7 +1042,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(70, "PE6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(2, "SPI4_RDY"),
STM32_FUNCTION(5, "SPDIFRX1_IN2"),
@@ -1056,7 +1056,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(71, "PE7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(4, "SAI4_D4"),
STM32_FUNCTION(5, "SPDIFRX1_IN3"),
@@ -1071,7 +1071,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(72, "PE8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "SPI4_MOSI"),
STM32_FUNCTION(4, "SAI4_CK1"),
@@ -1085,7 +1085,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(73, "PE9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "SPI4_MISO"),
STM32_FUNCTION(4, "SAI4_D2"),
@@ -1100,7 +1100,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(74, "PE10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "SPI4_SCK"),
STM32_FUNCTION(4, "SAI4_D1"),
@@ -1116,7 +1116,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(75, "PE11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(3, "SPI7_SCK"),
STM32_FUNCTION(4, "SAI4_D3"),
@@ -1130,7 +1130,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(76, "PE12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "SPI4_NSS"),
STM32_FUNCTION(4, "SAI4_CK2"),
@@ -1146,7 +1146,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(77, "PE13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(3, "SPI7_MISO"),
STM32_FUNCTION(5, "SAI1_SD_A"),
@@ -1159,7 +1159,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(78, "PE14"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(3, "SPI7_NSS"),
STM32_FUNCTION(5, "SAI1_MCLK_A"),
@@ -1173,7 +1173,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(79, "PE15"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(3, "SPI7_MOSI"),
STM32_FUNCTION(5, "SAI1_SCK_A"),
@@ -1187,7 +1187,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(80, "PF0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "FDCAN2_RX"),
@@ -1201,7 +1201,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(81, "PF1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(2, "SPI8_MISO"),
STM32_FUNCTION(3, "LPTIM2_IN2"),
@@ -1214,7 +1214,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(82, "PF2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(3, "SPI3_RDY"),
STM32_FUNCTION(7, "I2C4_SMBA"),
@@ -1229,7 +1229,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(83, "PF3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(4, "UART8_RX"),
STM32_FUNCTION(5, "SAI2_SCK_B"),
@@ -1246,7 +1246,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(84, "PF4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(2, "RTC_OUT2"),
STM32_FUNCTION(3, "SPI6_NSS"),
@@ -1263,7 +1263,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(85, "PF5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(3, "SPI6_SCK"),
STM32_FUNCTION(5, "SAI3_MCLK_A"),
@@ -1279,7 +1279,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(86, "PF6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(2, "RTC_OUT2"),
STM32_FUNCTION(4, "SAI3_MCLK_B"),
@@ -1293,7 +1293,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(87, "PF7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(3, "SPDIFRX1_IN1"),
STM32_FUNCTION(4, "SPI6_SCK"),
@@ -1307,7 +1307,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(88, "PF8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(2, "RTC_REFIN"),
STM32_FUNCTION(4, "SAI3_SCK_B"),
@@ -1323,7 +1323,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(89, "PF9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(4, "SAI3_SD_B"),
STM32_FUNCTION(5, "SAI2_SD_A"),
@@ -1337,7 +1337,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(90, "PF10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(3, "SPI3_RDY"),
@@ -1351,7 +1351,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(91, "PF11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(3, "SPDIFRX1_IN0"),
@@ -1366,7 +1366,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(92, "PF12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(3, "SPI5_MISO"),
@@ -1380,7 +1380,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(93, "PF13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "HDP0"),
@@ -1397,7 +1397,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(94, "PF14"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "HDP1"),
@@ -1412,7 +1412,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(95, "PF15"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "HDP2"),
@@ -1429,7 +1429,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(96, "PG0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(4, "I3C3_SDA"),
@@ -1445,7 +1445,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(97, "PG1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(3, "I2S3_MCK"),
@@ -1465,7 +1465,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(98, "PG2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(2, "RTC_REFIN"),
STM32_FUNCTION(3, "I2S3_MCK"),
@@ -1483,7 +1483,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(99, "PG3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(3, "SPI5_MOSI"),
@@ -1501,7 +1501,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(100, "PG4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(3, "SPI5_MISO"),
STM32_FUNCTION(4, "SAI3_FS_B"),
@@ -1517,7 +1517,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(101, "PG5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "HDP3"),
@@ -1531,7 +1531,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(102, "PG6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "HDP4"),
@@ -1546,7 +1546,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(103, "PG7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(2, "HDP5"),
@@ -1561,7 +1561,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(104, "PG8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(2, "HDP6"),
@@ -1578,7 +1578,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(105, "PG9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(6, "UART5_TX"),
@@ -1590,7 +1590,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(106, "PG10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(1, "TRACED8"),
STM32_FUNCTION(2, "HDP0"),
@@ -1603,7 +1603,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(107, "PG11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(1, "TRACED9"),
STM32_FUNCTION(2, "HDP1"),
@@ -1617,7 +1617,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(108, "PG12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(1, "TRACED10"),
STM32_FUNCTION(2, "HDP2"),
@@ -1631,7 +1631,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(109, "PG13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED11"),
STM32_FUNCTION(2, "HDP3"),
@@ -1647,7 +1647,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(110, "PG14"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED12"),
STM32_FUNCTION(2, "HDP4"),
@@ -1662,7 +1662,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(111, "PG15"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(1, "TRACED13"),
STM32_FUNCTION(2, "HDP5"),
@@ -1677,7 +1677,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(114, "PH2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(2, "LPTIM2_CH1"),
STM32_FUNCTION(3, "SPI7_RDY"),
@@ -1693,7 +1693,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(115, "PH3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "UART7_RX"),
@@ -1706,7 +1706,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(116, "PH4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(7, "UART7_TX"),
STM32_FUNCTION(8, "TIM17_BKIN"),
@@ -1721,7 +1721,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(117, "PH5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "SAI2_FS_A"),
STM32_FUNCTION(7, "UART8_CTS"),
@@ -1736,7 +1736,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(118, "PH6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(2, "LPTIM2_IN2"),
STM32_FUNCTION(5, "SAI1_MCLK_B"),
@@ -1751,7 +1751,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(119, "PH7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(5, "UART4_TX"),
@@ -1765,7 +1765,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(120, "PH8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(4, "SPDIFRX1_IN3"),
@@ -1780,7 +1780,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(121, "PH9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(4, "SPI6_NSS"),
STM32_FUNCTION(5, "SAI3_MCLK_A"),
@@ -1793,7 +1793,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(122, "PH10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(4, "SPI6_MOSI"),
@@ -1806,7 +1806,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(123, "PH11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(4, "SPI6_MISO"),
STM32_FUNCTION(5, "SAI3_FS_A"),
@@ -1818,7 +1818,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(124, "PH12"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(4, "SPI6_MISO"),
@@ -1829,7 +1829,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(125, "PH13"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(4, "SPI6_MOSI"),
@@ -1841,7 +1841,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(128, "PI0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(1, "TRACED14"),
STM32_FUNCTION(2, "HDP6"),
@@ -1856,7 +1856,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(129, "PI1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(1, "TRACED15"),
STM32_FUNCTION(2, "HDP7"),
@@ -1872,7 +1872,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(130, "PI2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "LPTIM1_ETR"),
STM32_FUNCTION(5, "SAI4_SCK_B"),
@@ -1885,7 +1885,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(131, "PI3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "LPTIM1_IN2"),
STM32_FUNCTION(5, "SAI4_SD_B"),
@@ -1898,7 +1898,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(132, "PI4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "LPTIM1_CH1"),
STM32_FUNCTION(5, "SAI4_FS_B"),
@@ -1910,7 +1910,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(133, "PI5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(3, "SPI5_MOSI"),
STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"),
@@ -1924,7 +1924,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(134, "PI6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(7, "USART3_TX"),
@@ -1936,7 +1936,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(135, "PI7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(7, "USART3_RX"),
STM32_FUNCTION(8, "TIM2_CH1"),
@@ -1947,14 +1947,14 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(136, "PI8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(137, "PI9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(2, "SPI7_MOSI"),
STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
@@ -1970,7 +1970,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(138, "PI10"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(2, "SAI1_SCK_A"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
@@ -1986,7 +1986,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(139, "PI11"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(3, "I2S2_MCK"),
STM32_FUNCTION(6, "UART8_TX"),
@@ -2389,7 +2389,7 @@ static const struct stm32_desc_pin stm32mp257_pins[] = {
static const struct stm32_desc_pin stm32mp257_z_pins[] = {
STM32_PIN_PKG(
PINCTRL_PIN(400, "PZ0"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ0"),
STM32_FUNCTION(3, "LPTIM3_IN1"),
STM32_FUNCTION(4, "SPI8_MOSI"),
@@ -2404,7 +2404,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(401, "PZ1"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ1"),
STM32_FUNCTION(3, "LPTIM3_CH1"),
STM32_FUNCTION(4, "SPI8_MISO"),
@@ -2419,7 +2419,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(402, "PZ2"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ2"),
STM32_FUNCTION(3, "LPTIM3_CH1"),
STM32_FUNCTION(4, "SPI8_SCK"),
@@ -2433,7 +2433,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(403, "PZ3"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ3"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "DBTRGO"),
@@ -2451,7 +2451,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(404, "PZ4"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ4"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "DBTRGO"),
@@ -2468,7 +2468,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(405, "PZ5"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ5"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(3, "LPTIM3_ETR"),
@@ -2482,7 +2482,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(406, "PZ6"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ6"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "DBTRGO"),
@@ -2497,7 +2497,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(407, "PZ7"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ7"),
STM32_FUNCTION(4, "SPI8_MOSI"),
STM32_FUNCTION(5, "MDF1_CCK1"),
@@ -2510,7 +2510,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(408, "PZ8"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ8"),
STM32_FUNCTION(3, "LPTIM3_IN1"),
STM32_FUNCTION(4, "SPI8_MISO"),
@@ -2525,7 +2525,7 @@ static const struct stm32_desc_pin stm32mp257_z_pins[] = {
),
STM32_PIN_PKG(
PINCTRL_PIN(409, "PZ9"),
- STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32MP_PKG_AI | STM32MP_PKG_AJ | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ9"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(4, "SPI8_RDY"),
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function
2024-10-22 15:56 ` [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function Antonio Borneo
@ 2024-10-23 8:46 ` Krzysztof Kozlowski
2024-10-23 8:47 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:46 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Tue, Oct 22, 2024 at 05:56:48PM +0200, Antonio Borneo wrote:
> From: Fabien Dessenne <fabien.dessenne@foss.st.com>
>
> Document the RSVD (Reserved) mux function, used to reserve pins
> for a coprocessor not running Linux.
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> ---
> .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 8 ++++++++
> include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
> 2 files changed, 9 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function
2024-10-22 15:56 ` [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function Antonio Borneo
2024-10-23 8:46 ` Krzysztof Kozlowski
@ 2024-10-23 8:47 ` Krzysztof Kozlowski
2024-10-23 8:56 ` Antonio Borneo
1 sibling, 1 reply; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:47 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Tue, Oct 22, 2024 at 05:56:48PM +0200, Antonio Borneo wrote:
> From: Fabien Dessenne <fabien.dessenne@foss.st.com>
>
> Document the RSVD (Reserved) mux function, used to reserve pins
> for a coprocessor not running Linux.
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> ---
> .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 8 ++++++++
> include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
> 2 files changed, 9 insertions(+)
>
BTW, which *existing* SoCs use it? Aren't you adding it for the new
platform?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/14] dt-bindings: pinctrl: stm32: support IO synchronization parameters
2024-10-22 15:56 ` [PATCH 07/14] dt-bindings: pinctrl: stm32: support " Antonio Borneo
@ 2024-10-23 8:49 ` Krzysztof Kozlowski
2024-10-24 22:38 ` Linus Walleij
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:49 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Tue, Oct 22, 2024 at 05:56:51PM +0200, Antonio Borneo wrote:
> From: Fabien Dessenne <fabien.dessenne@foss.st.com>
>
> Support the following IO synchronization parameters:
> - Delay (in ns)
> - Delay path (input / output)
> - Clock edge (single / double edge)
> - Clock inversion
> - Retiming
Why? What is missing for existing hardware support?
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> ---
> .../bindings/pinctrl/st,stm32-pinctrl.yaml | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> index 5d17d6487ae9c..9a7ecfea6eb5b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> @@ -207,6 +207,54 @@ patternProperties:
> 3: High speed
> $ref: /schemas/types.yaml#/definitions/uint32
> enum: [0, 1, 2, 3]
> + st,io-delay-path:
> + description: |
> + IO synchronization delay path location
> + 0: Delay switched into the output path
> + 1: Delay switched into the input path
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
Why enum? Why not bool? What is the "synchronization delay"? Why this is
needed per board?
> + st,io-clk-edge:
> + description: |
> + IO synchronization clock edge
> + 0: Data single-edge (changing on rising or falling clock edge)
> + 1: Data double-edge (changing on both clock edges)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
All the same questions.
> + st,io-clk-type:
> + description: |
> + IO synchronization clock inversion
> + 0: IO clocks not inverted. Data retimed to rising clock edge
> + 1: IO clocks inverted. Data retimed to falling clock edge
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
OK, so if not bool why this cannot be a readable string?
> + st,io-retime:
> + description: |
> + IO synchronization data retime
> + 0: Data not synchronized or retimed on clock edges
> + 1: Data retimed to either rising or falling clock edge
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
Missing blank lines everywhere between properties.
> + st,io-delay:
Use proper unit suffix. Or is there no such?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages
2024-10-22 15:56 ` [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages Antonio Borneo
@ 2024-10-23 8:51 ` Krzysztof Kozlowski
2024-10-23 10:08 ` Antonio Borneo
0 siblings, 1 reply; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:51 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Tue, Oct 22, 2024 at 05:56:55PM +0200, Antonio Borneo wrote:
> From: Amelie Delaunay <amelie.delaunay@foss.st.com>
>
> Add support for st,stm32mp215-pinctrl and st,stm32mp215-z-pinctrl.
So all previous patches are for this? Then they are supposed to be here.
> Add packages AM, AN and AO (values : 0x1000, 0x2000 and 0x8000)
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> ---
> .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +++-
> include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> index 9a7ecfea6eb5b..0a2d644dbece3 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> @@ -27,6 +27,8 @@ properties:
> - st,stm32mp135-pinctrl
> - st,stm32mp157-pinctrl
> - st,stm32mp157-z-pinctrl
> + - st,stm32mp215-pinctrl
> + - st,stm32mp215-z-pinctrl
> - st,stm32mp257-pinctrl
> - st,stm32mp257-z-pinctrl
>
> @@ -59,7 +61,7 @@ properties:
> Indicates the SOC package used.
> More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
> $ref: /schemas/types.yaml#/definitions/uint32
> - enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
> + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800, 0x1000, 0x2000, 0x4000]
>
> patternProperties:
> '^gpio@[0-9a-f]*$':
> diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
> index af3fd388329a0..01bc8be78ef72 100644
> --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
> +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
> @@ -41,6 +41,9 @@
> #define STM32MP_PKG_AI 0x100
> #define STM32MP_PKG_AK 0x400
> #define STM32MP_PKG_AL 0x800
> +#define STM32MP_PKG_AM 0x1000
> +#define STM32MP_PKG_AN 0x2000
> +#define STM32MP_PKG_AO 0x4000
Why these are some random hex values but not for example 0x801, 0x802
and 0x803? That's an enum, so bitmask does not make sense here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 13/14] dt-bindings: pinctrl: stm32: add support for stm32mp235
2024-10-22 15:56 ` [PATCH 13/14] dt-bindings: pinctrl: stm32: add support for stm32mp235 Antonio Borneo
@ 2024-10-23 8:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:52 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Tue, Oct 22, 2024 at 05:56:57PM +0200, Antonio Borneo wrote:
> Add the compatibles st,stm32mp235-pinctrl and st,stm32mp235-z-pinctrl.
>
> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> ---
> Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function
2024-10-23 8:47 ` Krzysztof Kozlowski
@ 2024-10-23 8:56 ` Antonio Borneo
2024-10-24 13:22 ` Krzysztof Kozlowski
0 siblings, 1 reply; 28+ messages in thread
From: Antonio Borneo @ 2024-10-23 8:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Wed, 2024-10-23 at 10:47 +0200, Krzysztof Kozlowski wrote:
> On Tue, Oct 22, 2024 at 05:56:48PM +0200, Antonio Borneo wrote:
> > From: Fabien Dessenne <fabien.dessenne@foss.st.com>
> >
> > Document the RSVD (Reserved) mux function, used to reserve pins
> > for a coprocessor not running Linux.
> >
> > Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
> > Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> > ---
> > .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 8 ++++++++
> > include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
> > 2 files changed, 9 insertions(+)
> >
>
> BTW, which *existing* SoCs use it? Aren't you adding it for the new
> platform?
>
This is already used in ST downstream kernel for STM32MP15x
In this example
https://github.com/STMicroelectronics/linux/blob/v6.1-stm32mp/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts#L112
the GPIOs for LED and for PWM are assigned to the Cortex-M4 and Linux (on Cortex-A7) is not supposed to touch them.
Regards,
Antonio
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages
2024-10-23 8:51 ` Krzysztof Kozlowski
@ 2024-10-23 10:08 ` Antonio Borneo
2024-10-24 13:25 ` Krzysztof Kozlowski
0 siblings, 1 reply; 28+ messages in thread
From: Antonio Borneo @ 2024-10-23 10:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Wed, 2024-10-23 at 10:51 +0200, Krzysztof Kozlowski wrote:
> On Tue, Oct 22, 2024 at 05:56:55PM +0200, Antonio Borneo wrote:
> > From: Amelie Delaunay <amelie.delaunay@foss.st.com>
> >
> > Add support for st,stm32mp215-pinctrl and st,stm32mp215-z-pinctrl.
>
> So all previous patches are for this? Then they are supposed to be here.
Hi Krzysztof,
I'm not sure I fully get your point here.
The previous patches in this series add the new features to the already upstreamed STM32MP257.
The same features are also needed here by STM32MP215 and in next patches 12/14 and 13/14 by STM32MP235.
>
> > Add packages AM, AN and AO (values : 0x1000, 0x2000 and 0x8000)
> >
> > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
> > Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> > ---
> > .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +++-
> > include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +++
> > 2 files changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> > index 9a7ecfea6eb5b..0a2d644dbece3 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> > +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> > @@ -27,6 +27,8 @@ properties:
> > - st,stm32mp135-pinctrl
> > - st,stm32mp157-pinctrl
> > - st,stm32mp157-z-pinctrl
> > + - st,stm32mp215-pinctrl
> > + - st,stm32mp215-z-pinctrl
> > - st,stm32mp257-pinctrl
> > - st,stm32mp257-z-pinctrl
> >
> > @@ -59,7 +61,7 @@ properties:
> > Indicates the SOC package used.
> > More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
> > $ref: /schemas/types.yaml#/definitions/uint32
> > - enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
> > + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800, 0x1000, 0x2000, 0x4000]
> >
> > patternProperties:
> > '^gpio@[0-9a-f]*$':
> > diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
> > index af3fd388329a0..01bc8be78ef72 100644
> > --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
> > +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
> > @@ -41,6 +41,9 @@
> > #define STM32MP_PKG_AI 0x100
> > #define STM32MP_PKG_AK 0x400
> > #define STM32MP_PKG_AL 0x800
> > +#define STM32MP_PKG_AM 0x1000
> > +#define STM32MP_PKG_AN 0x2000
> > +#define STM32MP_PKG_AO 0x4000
>
> Why these are some random hex values but not for example 0x801, 0x802
> and 0x803? That's an enum, so bitmask does not make sense here.
The are bitmask. You can check in patch 14/14 that adds a new package to the existing code of STM32MP257.
Do you prefer I rewrite them all as, e.g.
#define STM32MP_PKG_AO (1 << 14)
?
Thanks for the review!
Regards,
Antonio
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function
2024-10-23 8:56 ` Antonio Borneo
@ 2024-10-24 13:22 ` Krzysztof Kozlowski
0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-24 13:22 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On 23/10/2024 10:56, Antonio Borneo wrote:
> On Wed, 2024-10-23 at 10:47 +0200, Krzysztof Kozlowski wrote:
>> On Tue, Oct 22, 2024 at 05:56:48PM +0200, Antonio Borneo wrote:
>>> From: Fabien Dessenne <fabien.dessenne@foss.st.com>
>>>
>>> Document the RSVD (Reserved) mux function, used to reserve pins
>>> for a coprocessor not running Linux.
>>>
>>> Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
>>> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
>>> ---
>>> .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 8 ++++++++
>>> include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
>>> 2 files changed, 9 insertions(+)
>>>
>>
>> BTW, which *existing* SoCs use it? Aren't you adding it for the new
>> platform?
>>
>
> This is already used in ST downstream kernel for STM32MP15x
> In this example
> https://github.com/STMicroelectronics/linux/blob/v6.1-stm32mp/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts#L112
>
> the GPIOs for LED and for PWM are assigned to the Cortex-M4 and Linux (on Cortex-A7) is not supposed to touch them.
I wasn't clear. Which upstream uses it? We really could not care less
about downstream vendor code.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages
2024-10-23 10:08 ` Antonio Borneo
@ 2024-10-24 13:25 ` Krzysztof Kozlowski
0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-24 13:25 UTC (permalink / raw)
To: Antonio Borneo
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon,
linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On 23/10/2024 12:08, Antonio Borneo wrote:
> On Wed, 2024-10-23 at 10:51 +0200, Krzysztof Kozlowski wrote:
>> On Tue, Oct 22, 2024 at 05:56:55PM +0200, Antonio Borneo wrote:
>>> From: Amelie Delaunay <amelie.delaunay@foss.st.com>
>>>
>>> Add support for st,stm32mp215-pinctrl and st,stm32mp215-z-pinctrl.
>>
>> So all previous patches are for this? Then they are supposed to be here.
>
> Hi Krzysztof,
>
> I'm not sure I fully get your point here.
> The previous patches in this series add the new features to the already upstreamed STM32MP257.
> The same features are also needed here by STM32MP215 and in next patches 12/14 and 13/14 by STM32MP235.
commit msgs could be improved here, sorry, I have no clue for what
devices are you bringing this for. Putting here new SoC clearly suggests
that it is for new Soc, so entire split is incorrect.
>
>>
>>> Add packages AM, AN and AO (values : 0x1000, 0x2000 and 0x8000)
>>>
>>> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
>>> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
>>> ---
>>> .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +++-
>>> include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +++
>>> 2 files changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
>>> index 9a7ecfea6eb5b..0a2d644dbece3 100644
>>> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
>>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
>>> @@ -27,6 +27,8 @@ properties:
>>> - st,stm32mp135-pinctrl
>>> - st,stm32mp157-pinctrl
>>> - st,stm32mp157-z-pinctrl
>>> + - st,stm32mp215-pinctrl
>>> + - st,stm32mp215-z-pinctrl
>>> - st,stm32mp257-pinctrl
>>> - st,stm32mp257-z-pinctrl
>>>
>>> @@ -59,7 +61,7 @@ properties:
>>> Indicates the SOC package used.
>>> More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
>>> $ref: /schemas/types.yaml#/definitions/uint32
>>> - enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
>>> + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800, 0x1000, 0x2000, 0x4000]
>>>
>>> patternProperties:
>>> '^gpio@[0-9a-f]*$':
>>> diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
>>> index af3fd388329a0..01bc8be78ef72 100644
>>> --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
>>> +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
>>> @@ -41,6 +41,9 @@
>>> #define STM32MP_PKG_AI 0x100
>>> #define STM32MP_PKG_AK 0x400
>>> #define STM32MP_PKG_AL 0x800
>>> +#define STM32MP_PKG_AM 0x1000
>>> +#define STM32MP_PKG_AN 0x2000
>>> +#define STM32MP_PKG_AO 0x4000
>>
>> Why these are some random hex values but not for example 0x801, 0x802
>> and 0x803? That's an enum, so bitmask does not make sense here.
>
> The are bitmask. You can check in patch 14/14 that adds a new package to the existing code of STM32MP257.
> Do you prefer I rewrite them all as, e.g.
> #define STM32MP_PKG_AO (1 << 14)
> ?
OK, so where is this bitmask used in DTS? These are bindings, not some
random defines for driver.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
` (13 preceding siblings ...)
2024-10-22 15:56 ` [PATCH 14/14] pinctrl: stm32: Add new package to stm32mp257 pinctrl support Antonio Borneo
@ 2024-10-24 22:20 ` Linus Walleij
14 siblings, 0 replies; 28+ messages in thread
From: Linus Walleij @ 2024-10-24 22:20 UTC (permalink / raw)
To: Antonio Borneo, Maxime Coquelin
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue,
Catalin Marinas, Will Deacon, linux-gpio, devicetree,
linux-arm-kernel, linux-kernel, Clément Le Goffic,
Stephane Danieau, Amelie Delaunay, Fabien Dessenne,
Valentin Caron, Gatien Chevallier, Cheick Traore, linux-stm32
On Tue, Oct 22, 2024 at 5:59 PM Antonio Borneo
<antonio.borneo@foss.st.com> wrote:
> This series introduces the support for the new SoC
> - STM32MP215,
> - STM32MP235,
>
> by adding the support for the new functionalities
> - irq affinity,
> - Resource Isolation Framework (RIF),
> - Reserved (RSVD) pinmux function,
> - IO synchronization parameters,
> - compile the driver as module.
>
> Some minor code reorganization is also introduced.
Overallt the code looks good to me (I see bindings are being discussed
and I might have some comment on that as well.)
I wonder if Maxime can look over the code as well? He's the only
STM32 maintainer who hasn't written any of the patches and I think
he knows the driver pretty well.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/14] dt-bindings: pinctrl: stm32: support IO synchronization parameters
2024-10-22 15:56 ` [PATCH 07/14] dt-bindings: pinctrl: stm32: support " Antonio Borneo
2024-10-23 8:49 ` Krzysztof Kozlowski
@ 2024-10-24 22:38 ` Linus Walleij
2024-10-31 13:42 ` Antonio Borneo
1 sibling, 1 reply; 28+ messages in thread
From: Linus Walleij @ 2024-10-24 22:38 UTC (permalink / raw)
To: Antonio Borneo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Catalin Marinas, Will Deacon, linux-gpio,
devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
Hi Antonio/Fabien,
thanks for your patch!
On Tue, Oct 22, 2024 at 5:59 PM Antonio Borneo
<antonio.borneo@foss.st.com> wrote:
> From: Fabien Dessenne <fabien.dessenne@foss.st.com>
>
> Support the following IO synchronization parameters:
> - Delay (in ns)
> - Delay path (input / output)
> - Clock edge (single / double edge)
> - Clock inversion
> - Retiming
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
(...)
I want to check if we already have some of these properties
and if we don't, if they could and should be made generic,
i.e. will we see more of them, also from other vendors?
> + st,io-delay-path:
> + description: |
> + IO synchronization delay path location
> + 0: Delay switched into the output path
> + 1: Delay switched into the input path
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
This looks related to the st,io-delay below so please keep those
properties together.
Is this path identification really needed in practice, isn't it
implicit from other pin config properties if the pin is used as
input or output, and in that case where the delay applies?
Do you really have - in practice - pins that change between
input and output and need different delays at runtime (i.e. not
at startup)?
Otherwise I would say that just checking if the line is in input
or output from other properties should be enough to configure
this? input-enable, output-enable to name the obvious.
> + st,io-clk-edge:
> + description: |
> + IO synchronization clock edge
> + 0: Data single-edge (changing on rising or falling clock edge)
> + 1: Data double-edge (changing on both clock edges)
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
This looks like it should be made into a generic property,
it seems to be about how the logic is used rather than something
electronic but arguable fits in pin config.
Isn't this usually called DDR (double data rate) in tech speak?
What about a generic property "double-data-rate"?
> + st,io-clk-type:
> + description: |
> + IO synchronization clock inversion
> + 0: IO clocks not inverted. Data retimed to rising clock edge
> + 1: IO clocks inverted. Data retimed to falling clock edge
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
Doesn't this require st,io-retime to be specified at the same time?
Then we should add some YAML magic (if we can) to make sure
that happens.
> + st,io-retime:
> + description: |
> + IO synchronization data retime
> + 0: Data not synchronized or retimed on clock edges
> + 1: Data retimed to either rising or falling clock edge
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
Can't these two be merged into one (generic) property:
io-retime
enum [0, 1, 2]
0=none
1=rising retime
2=falling retime
Retiming seems like a very generic concept so I think it should
be made into a generic property.
> + st,io-delay:
> + description: |
> + IO synchronization delay applied to the input or output path
> + 0: No delay
> + 1: Delay 0.30 ns
> + 2: Delay 0.50 ns
> + 3: Delay 0.75 ns
> + 4: Delay 1.00 ns
> + 5: Delay 1.25 ns
> + 6: Delay 1.50 ns
> + 7: Delay 1.75 ns
> + 8: Delay 2.00 ns
> + 9: Delay 2.25 ns
> + 10: Delay 2.50 ns
> + 11: Delay 2.75 ns
> + 12: Delay 3.00 ns
> + 13: Delay 3.25 ns
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 13
This looks very similar to the existing "skew-delay" property:
skew-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
this affects the expected clock skew on input pins
and the delay before latching a value to an output
pin. Typically indicates how many double-inverters are
used to delay the signal.
can't we just use that?
Feel free to edit the text for it in
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
if that is too clock-specific.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/14] dt-bindings: pinctrl: stm32: support IO synchronization parameters
2024-10-24 22:38 ` Linus Walleij
@ 2024-10-31 13:42 ` Antonio Borneo
2024-11-01 10:24 ` Linus Walleij
0 siblings, 1 reply; 28+ messages in thread
From: Antonio Borneo @ 2024-10-31 13:42 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Catalin Marinas, Will Deacon, linux-gpio,
devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
On Fri, 2024-10-25 at 00:38 +0200, Linus Walleij wrote:
> Hi Antonio/Fabien,
>
> thanks for your patch!
>
> On Tue, Oct 22, 2024 at 5:59 PM Antonio Borneo
> <antonio.borneo@foss.st.com> wrote:
>
> > From: Fabien Dessenne <fabien.dessenne@foss.st.com>
> >
> > Support the following IO synchronization parameters:
> > - Delay (in ns)
> > - Delay path (input / output)
> > - Clock edge (single / double edge)
> > - Clock inversion
> > - Retiming
> >
> > Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
> > Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
> (...)
>
> I want to check if we already have some of these properties
> and if we don't, if they could and should be made generic,
> i.e. will we see more of them, also from other vendors?
Hi Linus,
Thanks for your review.
Apart for the generic property 'skew-delay' that you mentioned below, I cannot find other I can re-use here.
I'm preparing a V2 taking care of the observation from Krzysztof and you.
I will surely take 'skew-delay' in place of 'st,io-delay'.
> > + st,io-delay-path:
> > + description: |
> > + IO synchronization delay path location
> > + 0: Delay switched into the output path
> > + 1: Delay switched into the input path
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1]
>
> This looks related to the st,io-delay below so please keep those
> properties together.
>
> Is this path identification really needed in practice, isn't it
> implicit from other pin config properties if the pin is used as
> input or output, and in that case where the delay applies?
>
> Do you really have - in practice - pins that change between
> input and output and need different delays at runtime (i.e. not
> at startup)?
>
> Otherwise I would say that just checking if the line is in input
> or output from other properties should be enough to configure
> this? input-enable, output-enable to name the obvious.
On STM32MP25x there is a 'skew-delay' HW block on each pin, but it's applied independently on each pin either only on the input direction OR only on the output direction.
There is no automatic way to switch it between input and output path. This property assigns the delay to one path.
The generic property 'skew-delay' does not considers this case.
While I could extend the pinctrl driver to include the info about direction, that is trivial for example for UART or SPI, it will fail for bidirectional pins like I2C's SDA; some use case could
require the skew-delay on SDA input path, other on the output path.
Also the idea of assigning the direction at startup (e.g. in the bootloader) is not feasible as the delay depends on the functionality that can change at runtime e.g. by loading modules.
I prefer having this "direction" path explicitly selected through a DT property.
The existing properties 'input-enable' and 'output-enable' are not specific for the skew-delay.
And I think it would be confusing having 'input-enable' or 'output-enable' associated with a bidirectional pins like I2C's SDA.
I propose to change it as, e.g.
st,skew-delay-on-input:
type: boolean
description: |
If this property is present, then skew-delay applies to input path only,
otherwise it applies to output patch only.
Or, it could be a new generic property (keeping backward compatibility), e.g.:
skew-delay-direction:
enum [0, 1, 2]
default: 0
description: |
0: skew-delay applies to both input and output path, or it switches automatically
between the two direction
1: skew-delay applies only to input path
2: skew-delay applies only to output path
> > + st,io-clk-edge:
> > + description: |
> > + IO synchronization clock edge
> > + 0: Data single-edge (changing on rising or falling clock edge)
> > + 1: Data double-edge (changing on both clock edges)
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1]
>
> This looks like it should be made into a generic property,
I believe it is too specific to ST implementation.
I see already some 'retime' mentioned in old ST bindings bindings/pinctrl/pinctrl-st.txt and bindings/net/sti-dwmac.txt, but the control looks quite different; I don't plan to reuse them.
I will fuse in V2 this property together with the next two in a more meaningful one, partially acknowledging your proposal below.
> it seems to be about how the logic is used rather than something
> electronic but arguable fits in pin config.
>
> Isn't this usually called DDR (double data rate) in tech speak?
>
> What about a generic property "double-data-rate"?
>
> > + st,io-clk-type:
> > + description: |
> > + IO synchronization clock inversion
> > + 0: IO clocks not inverted. Data retimed to rising clock edge
> > + 1: IO clocks inverted. Data retimed to falling clock edge
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1]
>
> Doesn't this require st,io-retime to be specified at the same time?
>
> Then we should add some YAML magic (if we can) to make sure
> that happens.
>
> > + st,io-retime:
> > + description: |
> > + IO synchronization data retime
> > + 0: Data not synchronized or retimed on clock edges
> > + 1: Data retimed to either rising or falling clock edge
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1]
>
> Can't these two be merged into one (generic) property:
>
> io-retime
>
> enum [0, 1, 2]
>
> 0=none
> 1=rising retime
> 2=falling retime
>
> Retiming seems like a very generic concept so I think it should
> be made into a generic property.
>
> > + st,io-delay:
> > + description: |
> > + IO synchronization delay applied to the input or output path
> > + 0: No delay
> > + 1: Delay 0.30 ns
> > + 2: Delay 0.50 ns
> > + 3: Delay 0.75 ns
> > + 4: Delay 1.00 ns
> > + 5: Delay 1.25 ns
> > + 6: Delay 1.50 ns
> > + 7: Delay 1.75 ns
> > + 8: Delay 2.00 ns
> > + 9: Delay 2.25 ns
> > + 10: Delay 2.50 ns
> > + 11: Delay 2.75 ns
> > + 12: Delay 3.00 ns
> > + 13: Delay 3.25 ns
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + minimum: 0
> > + maximum: 13
>
> This looks very similar to the existing "skew-delay" property:
>
> skew-delay:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
> this affects the expected clock skew on input pins
> and the delay before latching a value to an output
> pin. Typically indicates how many double-inverters are
> used to delay the signal.
>
> can't we just use that?
>
> Feel free to edit the text for it in
> Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
> if that is too clock-specific.
I find that text already accurate; I don't plan to change it.
But adding a generic 'skew-delay-direction' could eventually require a mention in the description of 'skew-delay'.
Best Regards,
Antonio
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/14] dt-bindings: pinctrl: stm32: support IO synchronization parameters
2024-10-31 13:42 ` Antonio Borneo
@ 2024-11-01 10:24 ` Linus Walleij
0 siblings, 0 replies; 28+ messages in thread
From: Linus Walleij @ 2024-11-01 10:24 UTC (permalink / raw)
To: Antonio Borneo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Catalin Marinas, Will Deacon, linux-gpio,
devicetree, linux-arm-kernel, linux-kernel,
Clément Le Goffic, Stephane Danieau, Amelie Delaunay,
Fabien Dessenne, Valentin Caron, Gatien Chevallier, Cheick Traore,
linux-stm32
Hi Antonio,
some responses below!
On Thu, Oct 31, 2024 at 2:44 PM Antonio Borneo
<antonio.borneo@foss.st.com> wrote:
> > Otherwise I would say that just checking if the line is in input
> > or output from other properties should be enough to configure
> > this? input-enable, output-enable to name the obvious.
>
> On STM32MP25x there is a 'skew-delay' HW block on each pin,
> but it's applied independently on each pin either only on the
> input direction OR only on the output direction.
> There is no automatic way to switch it between input and
> output path. This property assigns the delay to one path.
> The generic property 'skew-delay' does not considers this
> case.
>
> While I could extend the pinctrl driver to include the info about
> direction, that is trivial for example for UART or SPI, it will fail
> for bidirectional pins like I2C's SDA; some use case could
> require the skew-delay on SDA input path, other on the output path.
> Also the idea of assigning the direction at startup (e.g. in the
> bootloader) is not feasible as the delay depends on the
> functionality that can change at runtime e.g. by loading modules.
> I prefer having this "direction" path explicitly selected through
> a DT property.
>
> The existing properties 'input-enable' and 'output-enable' are
> not specific for the skew-delay.
> And I think it would be confusing having 'input-enable' or
> 'output-enable' associated with a bidirectional pins like I2C's SDA.
>
> I propose to change it as, e.g.
> st,skew-delay-on-input:
> type: boolean
> description: |
> If this property is present, then skew-delay applies to input path only,
> otherwise it applies to output patch only.
>
> Or, it could be a new generic property (keeping backward compatibility), e.g.:
> skew-delay-direction:
> enum [0, 1, 2]
> default: 0
> description: |
> 0: skew-delay applies to both input and output path, or it switches automatically
> between the two direction
> 1: skew-delay applies only to input path
> 2: skew-delay applies only to output path
I like this property the most. Can we go with the generic
skew-delay-direction?
Also state in the existing skew-delay property that if
skew-delay-direction is not
present then it is assumed that the property applies to all
directions of a pin.
> > > + st,io-clk-edge:
> > > + description: |
> > > + IO synchronization clock edge
> > > + 0: Data single-edge (changing on rising or falling clock edge)
> > > + 1: Data double-edge (changing on both clock edges)
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [0, 1]
> >
> > This looks like it should be made into a generic property,
>
> I believe it is too specific to ST implementation.
> I see already some 'retime' mentioned in old ST bindings
> bindings/pinctrl/pinctrl-st.txt and bindings/net/sti-dwmac.txt, but the control looks quite different; I don't plan to reuse them.
>
> I will fuse in V2 this property together with the next two in a more
> meaningful one, partially acknowledging your proposal below.
Hmmmm. Let's see. I know that e.g. MMC has similar properties
and if similar things appear in other bindings (not necessarily
pinctrl bindings) then that should also be taken into account.
And in MMC this is called DDR.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2024-11-01 10:25 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-22 15:56 [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Antonio Borneo
2024-10-22 15:56 ` [PATCH 01/14] pinctrl: stm32: Declare stm32_pmx_get_mode() as static Antonio Borneo
2024-10-22 15:56 ` [PATCH 02/14] pinctrl: stm32: Manage irq affinity settings Antonio Borneo
2024-10-22 15:56 ` [PATCH 03/14] pinctrl: stm32: Handle RSVD pin configuration Antonio Borneo
2024-10-22 15:56 ` [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function Antonio Borneo
2024-10-23 8:46 ` Krzysztof Kozlowski
2024-10-23 8:47 ` Krzysztof Kozlowski
2024-10-23 8:56 ` Antonio Borneo
2024-10-24 13:22 ` Krzysztof Kozlowski
2024-10-22 15:56 ` [PATCH 05/14] pinctrl: stm32: Rework stm32_pconf_parse_conf() Antonio Borneo
2024-10-22 15:56 ` [PATCH 06/14] pinctrl: stm32: Support IO synchronization parameters Antonio Borneo
2024-10-22 15:56 ` [PATCH 07/14] dt-bindings: pinctrl: stm32: support " Antonio Borneo
2024-10-23 8:49 ` Krzysztof Kozlowski
2024-10-24 22:38 ` Linus Walleij
2024-10-31 13:42 ` Antonio Borneo
2024-11-01 10:24 ` Linus Walleij
2024-10-22 15:56 ` [PATCH 08/14] pinctrl: stm32: Add RIF support for stm32mp257 Antonio Borneo
2024-10-22 15:56 ` [PATCH 09/14] pinctrl: stm32: Allow compile as module " Antonio Borneo
2024-10-22 15:56 ` [PATCH 10/14] pinctrl: stm32: Add stm32mp215 pinctrl support Antonio Borneo
2024-10-22 15:56 ` [PATCH 11/14] dt-bindings: pinctrl: stm32: support for stm32mp215 and additional packages Antonio Borneo
2024-10-23 8:51 ` Krzysztof Kozlowski
2024-10-23 10:08 ` Antonio Borneo
2024-10-24 13:25 ` Krzysztof Kozlowski
2024-10-22 15:56 ` [PATCH 12/14] pinctrl: stm32: Add stm32mp235 pinctrl support Antonio Borneo
2024-10-22 15:56 ` [PATCH 13/14] dt-bindings: pinctrl: stm32: add support for stm32mp235 Antonio Borneo
2024-10-23 8:52 ` Krzysztof Kozlowski
2024-10-22 15:56 ` [PATCH 14/14] pinctrl: stm32: Add new package to stm32mp257 pinctrl support Antonio Borneo
2024-10-24 22:20 ` [PATCH 00/14] pinctrl: stm32: Add new features and support for more SoC Linus Walleij
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).