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Date:   Mon, 08 May 2023 08:39:25 +0200
From:   Michael Walle <michael@walle.cc>
To:     "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com>
Cc:     gregkh@linuxfoundation.org, arnd@arndb.de,
        kumaravel.thiagarajan@microchip.com,
        tharunkumar.pasumarthi@microchip.com, linux-kernel@vger.kernel.org,
        linux-gpio@vger.kernel.org, UNGLinuxDriver@microchip.com
Subject: Re: [PATCH v11 char-misc-next 1/2] misc: microchip: pci1xxxx: Add
 support to read and write into PCI1XXXX OTP via NVMEM sysfs
In-Reply-To: <20230429120209.2232-2-vaibhaavram.tl@microchip.com>
References: <20230429120209.2232-1-vaibhaavram.tl@microchip.com>
 <20230429120209.2232-2-vaibhaavram.tl@microchip.com>
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Am 2023-04-29 14:02, schrieb Vaibhaav Ram T.L:
> From: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
> 
> Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
> industrial, and automotive applications. This switch integrates OTP
> and EEPROM to enable customization of the part in the field. This
> patch adds support to read and write into PCI1XXXX OTP via NVMEM sysfs.
> 
> Signed-off-by: Kumaravel Thiagarajan 
> <kumaravel.thiagarajan@microchip.com>
> Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
> Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
> Co-developed-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
> Signed-off-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>

I just had a quick look for obvious errors, couldn't spot any. It's
not a extensive review, though.

-michael