* [PATCH v2 3/5] pinctrl: exynos: add exynos5410 SoC specific data [not found] <1416687984-3546-1-git-send-email-afaerber@suse.de> @ 2014-11-22 20:26 ` Andreas Färber 2014-11-22 21:49 ` Andreas Färber 0 siblings, 1 reply; 7+ messages in thread From: Andreas Färber @ 2014-11-22 20:26 UTC (permalink / raw) To: linux-samsung-soc Cc: Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel, linux-kernel, Andreas Färber, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Tomasz Figa, Thomas Abraham, Linus Walleij, Kukjin Kim, open list:OPEN FIRMWARE AND..., open list:PIN CONTROL SUBSY... From: Hakjoo Kim <ruppi.kim@hardkernel.com> Add Samsung EXYNOS5410 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5410. Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> [AF: Rebased onto Exynos5260] Signed-off-by: Andreas Färber <afaerber@suse.de> --- v1 -> v2: * Filled in Sob from Hakjoo Kim * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/samsung/pinctrl-exynos.c | 126 +++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 130 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index e82aaf492517..b87a176e730e 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -17,6 +17,7 @@ Required Properties: - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. + - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index d7154ed0b0eb..ef0e2a0d26eb 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1084,6 +1084,132 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { }, }; +/* pin banks of exynos5410 pin-controller 0 */ +static struct samsung_pin_bank exynos5410_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), + EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), + EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), + EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), + EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), + EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), + EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5410 pin-controller 1 */ +static struct samsung_pin_bank exynos5410_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), + EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), +}; + +/* pin banks of exynos5410 pin-controller 2 */ +static struct samsung_pin_bank exynos5410_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5410 pin-controller 3 */ +static struct samsung_pin_bank exynos5410_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5410_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5410_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5410_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5410_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5410_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl3", + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static struct samsung_pin_bank exynos5420_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2d37c8f49f3c..42de732c542f 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1222,6 +1222,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos5250_pin_ctrl }, { .compatible = "samsung,exynos5260-pinctrl", .data = (void *)exynos5260_pin_ctrl }, + { .compatible = "samsung,exynos5410-pinctrl", + .data = (void *)exynos5410_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 5cedc9d26390..d19bbf4c7f24 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -241,6 +241,7 @@ extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5410_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; -- 2.1.2 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/5] pinctrl: exynos: add exynos5410 SoC specific data 2014-11-22 20:26 ` [PATCH v2 3/5] pinctrl: exynos: add exynos5410 SoC specific data Andreas Färber @ 2014-11-22 21:49 ` Andreas Färber 2014-11-22 22:26 ` [PATCH v3 " Andreas Färber 0 siblings, 1 reply; 7+ messages in thread From: Andreas Färber @ 2014-11-22 21:49 UTC (permalink / raw) To: linux-samsung-soc Cc: Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel, linux-kernel, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Tomasz Figa, Thomas Abraham, Linus Walleij, Kukjin Kim, open list:OPEN FIRMWARE AND..., open list:PIN CONTROL SUBSY... Am 22.11.2014 um 21:26 schrieb Andreas Färber: > From: Hakjoo Kim <ruppi.kim@hardkernel.com> > > Add Samsung EXYNOS5410 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5410. > > Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> > [AF: Rebased onto Exynos5260] > Signed-off-by: Andreas Färber <afaerber@suse.de> > --- > v1 -> v2: > * Filled in Sob from Hakjoo Kim > * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) Ugh, this patch is actually missing exactly this change! Stay tuned... Andreas -- SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/5] pinctrl: exynos: add exynos5410 SoC specific data 2014-11-22 21:49 ` Andreas Färber @ 2014-11-22 22:26 ` Andreas Färber 2014-11-28 11:59 ` Linus Walleij 2014-12-28 11:16 ` Tomasz Figa 0 siblings, 2 replies; 7+ messages in thread From: Andreas Färber @ 2014-11-22 22:26 UTC (permalink / raw) To: linux-samsung-soc Cc: Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel, linux-kernel, Andreas Färber, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Tomasz Figa, Thomas Abraham, Linus Walleij, Kukjin Kim, open list:OPEN FIRMWARE AND..., open list:PIN CONTROL SUBSY... From: Hakjoo Kim <ruppi.kim@hardkernel.com> Add Samsung EXYNOS5410 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5410. Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> [AF: Rebased onto Exynos5260 and irq_chip consolidation] Signed-off-by: Andreas Färber <afaerber@suse.de> --- v2 -> v3: * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) v1 -> v2: * Filled in Sob from Hakjoo Kim .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/samsung/pinctrl-exynos.c | 107 +++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index e82aaf492517..b87a176e730e 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -17,6 +17,7 @@ Required Properties: - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. + - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index d7154ed0b0eb..0580399a6587 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1084,6 +1084,113 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { }, }; +/* pin banks of exynos5410 pin-controller 0 */ +static struct samsung_pin_bank exynos5410_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), + EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), + EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), + EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), + EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), + EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), + EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5410 pin-controller 1 */ +static struct samsung_pin_bank exynos5410_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), + EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), +}; + +/* pin banks of exynos5410 pin-controller 2 */ +static struct samsung_pin_bank exynos5410_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5410 pin-controller 3 */ +static struct samsung_pin_bank exynos5410_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5410_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5410_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5410_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5410_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5410_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5410-gpio-ctrl3", + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static struct samsung_pin_bank exynos5420_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2d37c8f49f3c..42de732c542f 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1222,6 +1222,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos5250_pin_ctrl }, { .compatible = "samsung,exynos5260-pinctrl", .data = (void *)exynos5260_pin_ctrl }, + { .compatible = "samsung,exynos5410-pinctrl", + .data = (void *)exynos5410_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 5cedc9d26390..d19bbf4c7f24 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -241,6 +241,7 @@ extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5410_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; -- 2.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/5] pinctrl: exynos: add exynos5410 SoC specific data 2014-11-22 22:26 ` [PATCH v3 " Andreas Färber @ 2014-11-28 11:59 ` Linus Walleij 2014-11-28 12:07 ` Andreas Färber 2014-12-28 11:16 ` Tomasz Figa 1 sibling, 1 reply; 7+ messages in thread From: Linus Walleij @ 2014-11-28 11:59 UTC (permalink / raw) To: Andreas Färber, Tomasz Figa Cc: linux-samsung-soc, Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Thomas Abraham, Kukjin Kim, open list:OPEN FIRMWARE AND..., open list:PIN CONTROL SUBSY... On Sat, Nov 22, 2014 at 11:26 PM, Andreas Färber <afaerber@suse.de> wrote: > From: Hakjoo Kim <ruppi.kim@hardkernel.com> > > Add Samsung EXYNOS5410 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5410. > > Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> > [AF: Rebased onto Exynos5260 and irq_chip consolidation] > Signed-off-by: Andreas Färber <afaerber@suse.de> > --- > v2 -> v3: > * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) > > v1 -> v2: > * Filled in Sob from Hakjoo Kim Is this based on the pinctrl devel branch so I can apply it? I'd like Tomasz ACK on it first though. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/5] pinctrl: exynos: add exynos5410 SoC specific data 2014-11-28 11:59 ` Linus Walleij @ 2014-11-28 12:07 ` Andreas Färber 2014-11-30 12:13 ` Tomasz Figa 0 siblings, 1 reply; 7+ messages in thread From: Andreas Färber @ 2014-11-28 12:07 UTC (permalink / raw) To: Linus Walleij Cc: Tomasz Figa, linux-samsung-soc, Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Thomas Abraham, Kukjin Kim, OPEN FIRMWARE AND..., PIN CONTROL SUBSY... Am 28.11.2014 um 12:59 schrieb Linus Walleij: > On Sat, Nov 22, 2014 at 11:26 PM, Andreas Färber <afaerber@suse.de> wrote: > >> From: Hakjoo Kim <ruppi.kim@hardkernel.com> >> >> Add Samsung EXYNOS5410 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5410. >> >> Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> >> [AF: Rebased onto Exynos5260 and irq_chip consolidation] >> Signed-off-by: Andreas Färber <afaerber@suse.de> >> --- >> v2 -> v3: >> * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) >> >> v1 -> v2: >> * Filled in Sob from Hakjoo Kim > > Is this based on the pinctrl devel branch so I can apply it? It was based on the Samsung for-next tree. I can rebase if needed. > I'd like Tomasz ACK on it first though. Thanks, Andreas -- SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/5] pinctrl: exynos: add exynos5410 SoC specific data 2014-11-28 12:07 ` Andreas Färber @ 2014-11-30 12:13 ` Tomasz Figa 0 siblings, 0 replies; 7+ messages in thread From: Tomasz Figa @ 2014-11-30 12:13 UTC (permalink / raw) To: Andreas Färber Cc: Linus Walleij, linux-samsung-soc, Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Thomas Abraham, Kukjin Kim, OPEN FIRMWARE AND..., PIN CONTROL SUBSY... Hi Andreas, 2014-11-28 21:07 GMT+09:00 Andreas Färber <afaerber@suse.de>: > Am 28.11.2014 um 12:59 schrieb Linus Walleij: >> On Sat, Nov 22, 2014 at 11:26 PM, Andreas Färber <afaerber@suse.de> wrote: >> >>> From: Hakjoo Kim <ruppi.kim@hardkernel.com> >>> >>> Add Samsung EXYNOS5410 SoC specific data to enable pinctrl >>> support for all platforms based on EXYNOS5410. >>> >>> Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> >>> [AF: Rebased onto Exynos5260 and irq_chip consolidation] >>> Signed-off-by: Andreas Färber <afaerber@suse.de> >>> --- >>> v2 -> v3: >>> * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) >>> >>> v1 -> v2: >>> * Filled in Sob from Hakjoo Kim >> >> Is this based on the pinctrl devel branch so I can apply it? > > It was based on the Samsung for-next tree. I can rebase if needed. Yes, please rebase (and please make sure that all the structs are const, which became possible after recent changes). Otherwise the patch looks good. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/5] pinctrl: exynos: add exynos5410 SoC specific data 2014-11-22 22:26 ` [PATCH v3 " Andreas Färber 2014-11-28 11:59 ` Linus Walleij @ 2014-12-28 11:16 ` Tomasz Figa 1 sibling, 0 replies; 7+ messages in thread From: Tomasz Figa @ 2014-12-28 11:16 UTC (permalink / raw) To: Andreas Färber, linux-samsung-soc Cc: Kukjin Kim, 김학주, Humberto Naves, Jan Kiszka, Johann Pfefferl, linux-arm-kernel, linux-kernel, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Thomas Abraham, Linus Walleij, Kukjin Kim, open list:OPEN FIRMWARE AND..., open list:PIN CONTROL SUBSY... Hi Andreas, On 23.11.2014 07:26, Andreas Färber wrote: > From: Hakjoo Kim <ruppi.kim@hardkernel.com> > > Add Samsung EXYNOS5410 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5410. > > Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> > [AF: Rebased onto Exynos5260 and irq_chip consolidation] > Signed-off-by: Andreas Färber <afaerber@suse.de> > --- > v2 -> v3: > * Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped) > > v1 -> v2: > * Filled in Sob from Hakjoo Kim Any news on this patch? I'd like to ACK it, but apparently it is waiting for a rebase. Sorry for the delay, unfortunately things are a little bit busy on my side nowadays. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 7+ messages in thread
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2014-11-22 20:26 ` [PATCH v2 3/5] pinctrl: exynos: add exynos5410 SoC specific data Andreas Färber
2014-11-22 21:49 ` Andreas Färber
2014-11-22 22:26 ` [PATCH v3 " Andreas Färber
2014-11-28 11:59 ` Linus Walleij
2014-11-28 12:07 ` Andreas Färber
2014-11-30 12:13 ` Tomasz Figa
2014-12-28 11:16 ` Tomasz Figa
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