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AJvYcCXCbqw4xxVrDQ4AoyVrF6tWEVHvJjd+qPfTC+qg3yoINyL7sNfVGAtWBBtOHQ/istiMm7KQUghUJEcXnk358KIb+tIx2Ysqg1araA== X-Gm-Message-State: AOJu0Yx8bUooVo0OEma2WCCto1c2j3aLlnkeSGJTNW4JM4l2sKOWDy27 TqLvl5YWB6v+RVjrbs3oBlSUtGX5f0dn0nxgi2xcxhAO8srdG55FDTcgxjkbH6Y= X-Google-Smtp-Source: AGHT+IED0nGy3qbIPeoHBT0UXTPEa8PBvuPeW8v6yBecZqwOZZ3M+oI31X4uRqOMy8lVpuzoahiqVQ== X-Received: by 2002:adf:a457:0:b0:34a:4f1c:3269 with SMTP id e23-20020adfa457000000b0034a4f1c3269mr9488780wra.0.1714421491886; Mon, 29 Apr 2024 13:11:31 -0700 (PDT) Received: from draszik.lan ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id bf7-20020a0560001cc700b003439d2a5f99sm30300260wrb.55.2024.04.29.13.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 13:11:31 -0700 (PDT) Message-ID: <560140f9b402e86b4d0e54f0eaa96a5cb57cfa22.camel@linaro.org> Subject: Re: [PATCH v3 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Krzysztof Kozlowski , Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin Cc: Tudor Ambarus , Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 29 Apr 2024 21:11:28 +0100 In-Reply-To: <8309a9a8906d3b910f775c6d55d9f75681b03802.camel@linaro.org> References: <20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org> <171441172281.306662.17546797534297489946.b4-ty@linaro.org> <479aeb87-ddc1-421a-a451-d9e62893eef5@linaro.org> <8309a9a8906d3b910f775c6d55d9f75681b03802.camel@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3-1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-04-29 at 21:06 +0100, Andr=C3=A9 Draszik wrote: > Hi Krzysztof, >=20 > On Mon, 2024-04-29 at 19:45 +0200, Krzysztof Kozlowski wrote: > > On 29/04/2024 19:28, Krzysztof Kozlowski wrote: > > >=20 > > > On Fri, 26 Apr 2024 14:25:13 +0100, Andr=C3=A9 Draszik wrote: > > > > This series enables clock support on the Samsung Exynos pin control= ler > > > > driver. > > > >=20 > > > > This is required on Socs like Google Tensor gs101, which implement > > > > fine-grained clock control / gating, and as such a running bus cloc= k is > > > > required for register access to work. > > > >=20 > >=20 > > Where's the DTS? >=20 > Here: https://lore.kernel.org/r/20240429-samsung-pinctrl-busclock-dts-v1-= 0-5e935179f3ca@linaro.org >=20 > (I was waiting to see how the HSI2 patches pan out) ... and potential binding feedback of course :-)