* [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits
@ 2022-04-20 14:24 Luca Ceresoli
2022-04-20 14:24 ` [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries Luca Ceresoli
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Luca Ceresoli @ 2022-04-20 14:24 UTC (permalink / raw)
To: linux-gpio
Cc: Luca Ceresoli, Linus Walleij, Heiko Stuebner, Jianqun Xu,
linux-arm-kernel, linux-rockchip, linux-kernel
Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong,
pointing to non-existing registers.
Fix the entire table.
Also add a comment in front of each entry with the same string that appears
in the datasheet to make the table easier to compare with the docs.
This fix has been tested on real hardware for the gpio3b3_sel entry.
Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support")
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 45 ++++++++++++++++++++----------
1 file changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index a1b598b86aa9..65fa305b5f59 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -457,95 +457,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
{
+ /* gpio1b6_sel */
.num = 1,
.pin = 14,
.reg = 0x28,
.bit = 12,
.mask = 0xf
}, {
+ /* gpio1b7_sel */
.num = 1,
.pin = 15,
.reg = 0x2c,
.bit = 0,
.mask = 0x3
}, {
+ /* gpio1c2_sel */
.num = 1,
.pin = 18,
.reg = 0x30,
.bit = 4,
.mask = 0xf
}, {
+ /* gpio1c3_sel */
.num = 1,
.pin = 19,
.reg = 0x30,
.bit = 8,
.mask = 0xf
}, {
+ /* gpio1c4_sel */
.num = 1,
.pin = 20,
.reg = 0x30,
.bit = 12,
.mask = 0xf
}, {
+ /* gpio1c5_sel */
.num = 1,
.pin = 21,
.reg = 0x34,
.bit = 0,
.mask = 0xf
}, {
+ /* gpio1c6_sel */
.num = 1,
.pin = 22,
.reg = 0x34,
.bit = 4,
.mask = 0xf
}, {
+ /* gpio1c7_sel */
.num = 1,
.pin = 23,
.reg = 0x34,
.bit = 8,
.mask = 0xf
}, {
+ /* gpio3b4_sel */
.num = 3,
.pin = 12,
.reg = 0x68,
.bit = 8,
.mask = 0xf
}, {
+ /* gpio3b5_sel */
.num = 3,
.pin = 13,
.reg = 0x68,
.bit = 12,
.mask = 0xf
}, {
+ /* gpio2a2_sel */
.num = 2,
.pin = 2,
- .reg = 0x608,
- .bit = 0,
- .mask = 0x7
+ .reg = 0x40,
+ .bit = 4,
+ .mask = 0x3
}, {
+ /* gpio2a3_sel */
.num = 2,
.pin = 3,
- .reg = 0x608,
- .bit = 4,
- .mask = 0x7
+ .reg = 0x40,
+ .bit = 6,
+ .mask = 0x3
}, {
+ /* gpio2c0_sel */
.num = 2,
.pin = 16,
- .reg = 0x610,
- .bit = 8,
- .mask = 0x7
+ .reg = 0x50,
+ .bit = 0,
+ .mask = 0x3
}, {
+ /* gpio3b2_sel */
.num = 3,
.pin = 10,
- .reg = 0x610,
- .bit = 0,
- .mask = 0x7
+ .reg = 0x68,
+ .bit = 4,
+ .mask = 0x3
}, {
+ /* gpio3b3_sel */
.num = 3,
.pin = 11,
- .reg = 0x610,
- .bit = 4,
- .mask = 0x7
+ .reg = 0x68,
+ .bit = 6,
+ .mask = 0x3
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries
2022-04-20 14:24 [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Luca Ceresoli
@ 2022-04-20 14:24 ` Luca Ceresoli
2022-04-20 15:05 ` Heiko Stuebner
2022-04-20 15:04 ` [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Heiko Stuebner
2022-04-22 21:36 ` Linus Walleij
2 siblings, 1 reply; 5+ messages in thread
From: Luca Ceresoli @ 2022-04-20 14:24 UTC (permalink / raw)
To: linux-gpio
Cc: Luca Ceresoli, Linus Walleij, Heiko Stuebner, Jianqun Xu,
linux-arm-kernel, linux-rockchip, linux-kernel
All the entries are sorted according to num/pin except for two
entries. Sort them too.
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 65fa305b5f59..2cb79e649fcf 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -512,20 +512,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
.reg = 0x34,
.bit = 8,
.mask = 0xf
- }, {
- /* gpio3b4_sel */
- .num = 3,
- .pin = 12,
- .reg = 0x68,
- .bit = 8,
- .mask = 0xf
- }, {
- /* gpio3b5_sel */
- .num = 3,
- .pin = 13,
- .reg = 0x68,
- .bit = 12,
- .mask = 0xf
}, {
/* gpio2a2_sel */
.num = 2,
@@ -561,6 +547,20 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
.reg = 0x68,
.bit = 6,
.mask = 0x3
+ }, {
+ /* gpio3b4_sel */
+ .num = 3,
+ .pin = 12,
+ .reg = 0x68,
+ .bit = 8,
+ .mask = 0xf
+ }, {
+ /* gpio3b5_sel */
+ .num = 3,
+ .pin = 13,
+ .reg = 0x68,
+ .bit = 12,
+ .mask = 0xf
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits
2022-04-20 14:24 [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Luca Ceresoli
2022-04-20 14:24 ` [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries Luca Ceresoli
@ 2022-04-20 15:04 ` Heiko Stuebner
2022-04-22 21:36 ` Linus Walleij
2 siblings, 0 replies; 5+ messages in thread
From: Heiko Stuebner @ 2022-04-20 15:04 UTC (permalink / raw)
To: linux-gpio, Luca Ceresoli
Cc: Luca Ceresoli, Linus Walleij, Jianqun Xu, linux-arm-kernel,
linux-rockchip, linux-kernel
Am Mittwoch, 20. April 2022, 16:24:31 CEST schrieb Luca Ceresoli:
> Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong,
> pointing to non-existing registers.
>
> Fix the entire table.
>
> Also add a comment in front of each entry with the same string that appears
> in the datasheet to make the table easier to compare with the docs.
>
> This fix has been tested on real hardware for the gpio3b3_sel entry.
>
> Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support")
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Thanks for walking through the datasheet for the fixes :-)
> ---
> drivers/pinctrl/pinctrl-rockchip.c | 45 ++++++++++++++++++++----------
> 1 file changed, 30 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index a1b598b86aa9..65fa305b5f59 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -457,95 +457,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
>
> static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
> {
> + /* gpio1b6_sel */
> .num = 1,
> .pin = 14,
> .reg = 0x28,
> .bit = 12,
> .mask = 0xf
> }, {
> + /* gpio1b7_sel */
> .num = 1,
> .pin = 15,
> .reg = 0x2c,
> .bit = 0,
> .mask = 0x3
> }, {
> + /* gpio1c2_sel */
> .num = 1,
> .pin = 18,
> .reg = 0x30,
> .bit = 4,
> .mask = 0xf
> }, {
> + /* gpio1c3_sel */
> .num = 1,
> .pin = 19,
> .reg = 0x30,
> .bit = 8,
> .mask = 0xf
> }, {
> + /* gpio1c4_sel */
> .num = 1,
> .pin = 20,
> .reg = 0x30,
> .bit = 12,
> .mask = 0xf
> }, {
> + /* gpio1c5_sel */
> .num = 1,
> .pin = 21,
> .reg = 0x34,
> .bit = 0,
> .mask = 0xf
> }, {
> + /* gpio1c6_sel */
> .num = 1,
> .pin = 22,
> .reg = 0x34,
> .bit = 4,
> .mask = 0xf
> }, {
> + /* gpio1c7_sel */
> .num = 1,
> .pin = 23,
> .reg = 0x34,
> .bit = 8,
> .mask = 0xf
> }, {
> + /* gpio3b4_sel */
> .num = 3,
> .pin = 12,
> .reg = 0x68,
> .bit = 8,
> .mask = 0xf
> }, {
> + /* gpio3b5_sel */
> .num = 3,
> .pin = 13,
> .reg = 0x68,
> .bit = 12,
> .mask = 0xf
> }, {
> + /* gpio2a2_sel */
> .num = 2,
> .pin = 2,
> - .reg = 0x608,
> - .bit = 0,
> - .mask = 0x7
> + .reg = 0x40,
> + .bit = 4,
> + .mask = 0x3
> }, {
> + /* gpio2a3_sel */
> .num = 2,
> .pin = 3,
> - .reg = 0x608,
> - .bit = 4,
> - .mask = 0x7
> + .reg = 0x40,
> + .bit = 6,
> + .mask = 0x3
> }, {
> + /* gpio2c0_sel */
> .num = 2,
> .pin = 16,
> - .reg = 0x610,
> - .bit = 8,
> - .mask = 0x7
> + .reg = 0x50,
> + .bit = 0,
> + .mask = 0x3
> }, {
> + /* gpio3b2_sel */
> .num = 3,
> .pin = 10,
> - .reg = 0x610,
> - .bit = 0,
> - .mask = 0x7
> + .reg = 0x68,
> + .bit = 4,
> + .mask = 0x3
> }, {
> + /* gpio3b3_sel */
> .num = 3,
> .pin = 11,
> - .reg = 0x610,
> - .bit = 4,
> - .mask = 0x7
> + .reg = 0x68,
> + .bit = 6,
> + .mask = 0x3
> },
> };
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries
2022-04-20 14:24 ` [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries Luca Ceresoli
@ 2022-04-20 15:05 ` Heiko Stuebner
0 siblings, 0 replies; 5+ messages in thread
From: Heiko Stuebner @ 2022-04-20 15:05 UTC (permalink / raw)
To: linux-gpio, Luca Ceresoli
Cc: Luca Ceresoli, Linus Walleij, Jianqun Xu, linux-arm-kernel,
linux-rockchip, linux-kernel
Am Mittwoch, 20. April 2022, 16:24:32 CEST schrieb Luca Ceresoli:
> All the entries are sorted according to num/pin except for two
> entries. Sort them too.
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 65fa305b5f59..2cb79e649fcf 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -512,20 +512,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
> .reg = 0x34,
> .bit = 8,
> .mask = 0xf
> - }, {
> - /* gpio3b4_sel */
> - .num = 3,
> - .pin = 12,
> - .reg = 0x68,
> - .bit = 8,
> - .mask = 0xf
> - }, {
> - /* gpio3b5_sel */
> - .num = 3,
> - .pin = 13,
> - .reg = 0x68,
> - .bit = 12,
> - .mask = 0xf
> }, {
> /* gpio2a2_sel */
> .num = 2,
> @@ -561,6 +547,20 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
> .reg = 0x68,
> .bit = 6,
> .mask = 0x3
> + }, {
> + /* gpio3b4_sel */
> + .num = 3,
> + .pin = 12,
> + .reg = 0x68,
> + .bit = 8,
> + .mask = 0xf
> + }, {
> + /* gpio3b5_sel */
> + .num = 3,
> + .pin = 13,
> + .reg = 0x68,
> + .bit = 12,
> + .mask = 0xf
> },
> };
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits
2022-04-20 14:24 [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Luca Ceresoli
2022-04-20 14:24 ` [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries Luca Ceresoli
2022-04-20 15:04 ` [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Heiko Stuebner
@ 2022-04-22 21:36 ` Linus Walleij
2 siblings, 0 replies; 5+ messages in thread
From: Linus Walleij @ 2022-04-22 21:36 UTC (permalink / raw)
To: Luca Ceresoli
Cc: linux-gpio, Heiko Stuebner, Jianqun Xu, linux-arm-kernel,
linux-rockchip, linux-kernel
On Wed, Apr 20, 2022 at 4:24 PM Luca Ceresoli <luca.ceresoli@bootlin.com> wrote:
> Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong,
> pointing to non-existing registers.
>
> Fix the entire table.
Patches 1 + 2 applied for fixes!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-04-22 22:43 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2022-04-20 14:24 [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Luca Ceresoli
2022-04-20 14:24 ` [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries Luca Ceresoli
2022-04-20 15:05 ` Heiko Stuebner
2022-04-20 15:04 ` [PATCH 1/2] pinctrl: rockchip: fix RK3308 pinmux bits Heiko Stuebner
2022-04-22 21:36 ` Linus Walleij
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