From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Jon Hunter <jonathanh@nvidia.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
Stefan Agner <stefan@agner.ch>,
linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: Re: [PATCH v2 2/2] pinctrl: tegra: Add bitmask support for parked bits
Date: Mon, 24 Jun 2019 04:21:41 +0300 [thread overview]
Message-ID: <5f38ce80-dac5-5a1e-0569-27535a6f35fd@gmail.com> (raw)
In-Reply-To: <20190621151932.20662-2-thierry.reding@gmail.com>
21.06.2019 18:19, Thierry Reding пишет:
> From: Thierry Reding <treding@nvidia.com>
>
> Some pin groups have park bits for multiple pins in one register.
> Support this by turning the parked bit field into a parked bitmask
> field. If no parked bits are supported, the bitmask can be 0.
>
> Update the pingroup table on Tegra210, which is the only generation
> where this is supported, with the parked bitmask.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - write to mux_bank/mux_reg or drv_bank/drv_reg depending on pin
Looking great! Thank you!
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
For Tegra20/30
Tested-by: Dmitry Osipenko <digetx@gmail.com>
next prev parent reply other threads:[~2019-06-24 1:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-21 15:19 [PATCH v2 1/2] pinctrl: tegra: Set specific GPIO compatible string Thierry Reding
2019-06-21 15:19 ` [PATCH v2 2/2] pinctrl: tegra: Add bitmask support for parked bits Thierry Reding
2019-06-24 1:21 ` Dmitry Osipenko [this message]
2019-06-25 13:37 ` Linus Walleij
2019-06-24 1:20 ` [PATCH v2 1/2] pinctrl: tegra: Set specific GPIO compatible string Dmitry Osipenko
2019-06-25 13:35 ` Linus Walleij
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