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Thu, 06 Mar 2025 07:12:33 -0800 (PST) Message-ID: <5fe34e1193a167c24c7af900f5b7cf85140d66e0.camel@linaro.org> Subject: Re: [PATCH v2 3/4] pinctrl: samsung: add gs101 specific eint suspend/resume callbacks From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Peter Griffin , Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, kernel-team@android.com, jaewon02.kim@samsung.com, stable@vger.kernel.org Date: Thu, 06 Mar 2025 15:12:32 +0000 In-Reply-To: <20250301-pinctrl-fltcon-suspend-v2-3-a7eef9bb443b@linaro.org> References: <20250301-pinctrl-fltcon-suspend-v2-0-a7eef9bb443b@linaro.org> <20250301-pinctrl-fltcon-suspend-v2-3-a7eef9bb443b@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.53.2-1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sat, 2025-03-01 at 11:43 +0000, Peter Griffin wrote: > gs101 differs to other SoCs in that fltcon1 register doesn't > always exist. Additionally the offset of fltcon0 is not fixed > and needs to use the newly added eint_fltcon_offset variable. >=20 > Signed-off-by: Peter Griffin > Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configurati= on") > Cc: stable@vger.kernel.org > --- > =C2=A0drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 24 ++++----- > =C2=A0drivers/pinctrl/samsung/pinctrl-exynos.c=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 71 ++++++++++++++++++++++++++ > =C2=A0drivers/pinctrl/samsung/pinctrl-exynos.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0 2 + > =C2=A03 files changed, 85 insertions(+), 12 deletions(-) >=20 > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pin= ctrl/samsung/pinctrl-exynos-arm64.c > index 57c98d2451b5..fca447ebc5f5 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > @@ -1455,15 +1455,15 @@ static const struct samsung_pin_ctrl gs101_pin_ct= rl[] __initconst =3D { > =C2=A0 .pin_banks =3D gs101_pin_alive, > =C2=A0 .nr_banks =3D ARRAY_SIZE(gs101_pin_alive), > =C2=A0 .eint_wkup_init =3D exynos_eint_wkup_init, > - .suspend =3D exynos_pinctrl_suspend, > - .resume =3D exynos_pinctrl_resume, > + .suspend =3D gs101_pinctrl_suspend, > + .resume =3D gs101_pinctrl_resume, > =C2=A0 }, { > =C2=A0 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ > =C2=A0 .pin_banks =3D gs101_pin_far_alive, > =C2=A0 .nr_banks =3D ARRAY_SIZE(gs101_pin_far_alive), > =C2=A0 .eint_wkup_init =3D exynos_eint_wkup_init, > - .suspend =3D exynos_pinctrl_suspend, > - .resume =3D exynos_pinctrl_resume, > + .suspend =3D gs101_pinctrl_suspend, > + .resume =3D gs101_pinctrl_resume, > =C2=A0 }, { > =C2=A0 /* pin banks of gs101 pin-controller (GSACORE) */ > =C2=A0 .pin_banks =3D gs101_pin_gsacore, > @@ -1477,29 +1477,29 @@ static const struct samsung_pin_ctrl gs101_pin_ct= rl[] __initconst =3D { > =C2=A0 .pin_banks =3D gs101_pin_peric0, > =C2=A0 .nr_banks =3D ARRAY_SIZE(gs101_pin_peric0), > =C2=A0 .eint_gpio_init =3D exynos_eint_gpio_init, > - .suspend =3D exynos_pinctrl_suspend, > - .resume =3D exynos_pinctrl_resume, > + .suspend =3D gs101_pinctrl_suspend, > + .resume =3D gs101_pinctrl_resume, > =C2=A0 }, { > =C2=A0 /* pin banks of gs101 pin-controller (PERIC1) */ > =C2=A0 .pin_banks =3D gs101_pin_peric1, > =C2=A0 .nr_banks =3D ARRAY_SIZE(gs101_pin_peric1), > =C2=A0 .eint_gpio_init =3D exynos_eint_gpio_init, > - .suspend =3D exynos_pinctrl_suspend, > - .resume =3D exynos_pinctrl_resume, > + .suspend =3D gs101_pinctrl_suspend, > + .resume =3D gs101_pinctrl_resume, > =C2=A0 }, { > =C2=A0 /* pin banks of gs101 pin-controller (HSI1) */ > =C2=A0 .pin_banks =3D gs101_pin_hsi1, > =C2=A0 .nr_banks =3D ARRAY_SIZE(gs101_pin_hsi1), > =C2=A0 .eint_gpio_init =3D exynos_eint_gpio_init, > - .suspend =3D exynos_pinctrl_suspend, > - .resume =3D exynos_pinctrl_resume, > + .suspend =3D gs101_pinctrl_suspend, > + .resume =3D gs101_pinctrl_resume, > =C2=A0 }, { > =C2=A0 /* pin banks of gs101 pin-controller (HSI2) */ > =C2=A0 .pin_banks =3D gs101_pin_hsi2, > =C2=A0 .nr_banks =3D ARRAY_SIZE(gs101_pin_hsi2), > =C2=A0 .eint_gpio_init =3D exynos_eint_gpio_init, > - .suspend =3D exynos_pinctrl_suspend, > - .resume =3D exynos_pinctrl_resume, > + .suspend =3D gs101_pinctrl_suspend, > + .resume =3D gs101_pinctrl_resume, > =C2=A0 }, > =C2=A0}; > =C2=A0 > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/s= amsung/pinctrl-exynos.c > index d65a9fba0781..ddc7245ec2e5 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > @@ -801,6 +801,41 @@ void exynos_pinctrl_suspend(struct samsung_pin_bank = *bank) > =C2=A0 } > =C2=A0} > =C2=A0 > +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) > +{ > + struct exynos_eint_gpio_save *save =3D bank->soc_priv; > + const void __iomem *regs =3D bank->eint_base; > + > + exynos_set_wakeup(bank); As for patch 2, would be good to have this if / else, to make it more obvious that this is conditional, too. > + > + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { > + save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset); > + > + save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + > + =C2=A0=C2=A0 bank->eint_fltcon_offset); If there's another version, maybe align style where the '+' is placed (end of line vs start of line). It seems this file generally uses + at start of line. > + > + /* fltcon1 register only exists for pins 4-7 */ > + if (bank->nr_pins > 4) > + save->eint_fltcon1 =3D readl(regs + > + EXYNOS_GPIO_EFLTCON_OFFSET + > + bank->eint_fltcon_offset + 4); > + > + save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask > + + bank->eint_offset); > + > + pr_debug("%s: save=C2=A0=C2=A0=C2=A0=C2=A0 con %#010x\n", > + bank->name, save->eint_con); > + pr_debug("%s: save fltcon0 %#010x\n", > + bank->name, save->eint_fltcon0); > + if (bank->nr_pins > 4) > + pr_debug("%s: save fltcon1 %#010x\n", > + bank->name, save->eint_fltcon1); > + pr_debug("%s: save=C2=A0=C2=A0=C2=A0 mask %#010x\n", > + bank->name, save->eint_mask); > + } > +} > + > =C2=A0void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) > =C2=A0{ > =C2=A0 struct exynos_eint_gpio_save *save =3D bank->soc_priv; > @@ -820,6 +855,42 @@ void exynosautov920_pinctrl_suspend(struct samsung_p= in_bank *bank) > =C2=A0 } > =C2=A0} > =C2=A0 > +void gs101_pinctrl_resume(struct samsung_pin_bank *bank) > +{ > + struct exynos_eint_gpio_save *save =3D bank->soc_priv; > + > + void __iomem *regs =3D bank->eint_base; > + void __iomem *eint_fltcfg0 =3D regs + EXYNOS_GPIO_EFLTCON_OFFSET > + =C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_fltcon_offset; > + > + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { > + pr_debug("%s:=C2=A0=C2=A0=C2=A0=C2=A0 con %#010x =3D> %#010x\n", bank-= >name, > + readl(regs + EXYNOS_GPIO_ECON_OFFSET > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset), save->eint= _con); > + > + pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, > + readl(eint_fltcfg0), save->eint_fltcon0); > + > + /* fltcon1 register only exists for pins 4-7 */ > + if (bank->nr_pins > 4) { > + pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, > + readl(eint_fltcfg0 + 4), save->eint_fltcon1); > + } If there's another version, braces are not needed here. Cheers, Andre' > + pr_debug("%s:=C2=A0=C2=A0=C2=A0 mask %#010x =3D> %#010x\n", bank->name= , > + readl(regs + bank->irq_chip->eint_mask > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset), save->eint= _mask); > + > + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset); > + writel(save->eint_fltcon0, eint_fltcfg0); > + > + if (bank->nr_pins > 4) > + writel(save->eint_fltcon1, eint_fltcfg0 + 4); > + writel(save->eint_mask, regs + bank->irq_chip->eint_mask > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset); > + } > +} > + > =C2=A0void exynos_pinctrl_resume(struct samsung_pin_bank *bank) > =C2=A0{ > =C2=A0 struct exynos_eint_gpio_save *save =3D bank->soc_priv; > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/s= amsung/pinctrl-exynos.h > index 35c2bc4ea488..773f161a82a3 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > @@ -225,6 +225,8 @@ void exynosautov920_pinctrl_resume(struct samsung_pin= _bank *bank); > =C2=A0void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); > =C2=A0void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); > =C2=A0void exynos_pinctrl_resume(struct samsung_pin_bank *bank); > +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank); > +void gs101_pinctrl_resume(struct samsung_pin_bank *bank); > =C2=A0struct samsung_retention_ctrl * > =C2=A0exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const struct samsung_retention_dat= a *data); >=20