Re: [PATCH v2 4/5] soc: fsl: qe: Add support of IRQ in QE GPIO

[Christophe Leroy <christophe.leroy@csgroup.eu>]

Le 18/08/2025 à 19:03, Conor Dooley a écrit :
> On Mon, Aug 18, 2025 at 10:45:57AM +0200, Christophe Leroy wrote:
>> In the QE, a few GPIOs are IRQ capable. Similarly to
>> commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
>> GPIO"), add IRQ support to QE GPIO.
>>
>> Add property 'fsl,qe-gpio-irq-mask' similar to
>> 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.
>>
>> Here is an exemple for port B of mpc8323 which has IRQs for
>> GPIOs PB7, PB9, PB25 and PB27.
>>
>> 	qe_pio_b: gpio-controller@1418 {
>> 		#gpio-cells = <2>;
>> 		compatible = "fsl,mpc8323-qe-pario-bank";
>> 		reg = <0x1418 0x18>;
>> 		interrupts = <4 5 6 7>;
>> 		fsl,qe-gpio-irq-mask = <0x01400050>;
>> 		interrupt-parent = <&qepic>;
>> 		gpio-controller;
>> 	};
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>> ---
>> v2: Document fsl,qe-gpio-irq-mask
>> ---
>>   .../bindings/soc/fsl/cpm_qe/qe/par_io.txt     | 19 ++++++++++++++++++
>>   drivers/soc/fsl/qe/gpio.c                     | 20 +++++++++++++++++++
>>   2 files changed, 39 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
>> index 09b1b05fa677..9cd6e5ac2a7b 100644
>> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
>> @@ -32,6 +32,15 @@ Required properties:
>>     "fsl,mpc8323-qe-pario-bank".
>>   - reg : offset to the register set and its length.
>>   - gpio-controller : node to identify gpio controllers.
>> +Optional properties:
>> +- fsl,qe-gpio-irq-mask : For banks having interrupt capability this item tells
>> +  which ports have an associated interrupt (ports are listed in the same order
>> +  QE ports registers)
>> +- interrupts : This property provides the list of interrupt for each GPIO having
>> +  one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
>> +  many interrupts as number of ones in the mask property. The first interrupt in
>> +  the list corresponds to the most significant bit of the mask.
>> +- interrupt-parent : Parent for the above interrupt property.
>>   
>>   Example:
>>   	qe_pio_a: gpio-controller@1400 {
>> @@ -42,6 +51,16 @@ Example:
>>   		gpio-controller;
>>   	  };
>>   
>> +	qe_pio_b: gpio-controller@1418 {
>> +		#gpio-cells = <2>;
>> +		compatible = "fsl,mpc8323-qe-pario-bank";
>> +		reg = <0x1418 0x18>;
>> +		interrupts = <4 5 6 7>;
>> +		fsl,qe-gpio-irq-mask = <0x01400050>;
>> +		interrupt-parent = <&qepic>;
>> +		gpio-controller;
>> +	  };
>> +
>>   	qe_pio_e: gpio-controller@1460 {
>>   		#gpio-cells = <2>;
>>   		compatible = "fsl,mpc8360-qe-pario-bank",
> 
> Why is there a binding change hiding in here alongside a driver one?

I did the same way as commit 726bd223105c ("powerpc/8xx: Adding support 
of IRQ in MPC8xx GPIO")

Should it be done differently ?

Thanks
Christophe