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[213.161.3.76]) by smtp.gmail.com with ESMTPSA id b3-20020a50e783000000b0042617ba637fsm1252502edn.9.2022.05.26.13.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 13:49:44 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Chen-Yu Tsai , Samuel Holland Cc: Samuel Holland , Linus Walleij , Maxime Ripard , Vishnu Patekar , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH] pinctrl: sunxi: a83t: Fix NAND function name for some pins Date: Thu, 26 May 2022 22:49:43 +0200 Message-ID: <7383317.EvYhyI6sBW@kista> In-Reply-To: <20220526024956.49500-1-samuel@sholland.org> References: <20220526024956.49500-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Dne =C4=8Detrtek, 26. maj 2022 ob 04:49:56 CEST je Samuel Holland napisal(a= ): > The other NAND pins on Port C use the "nand0" function name. > "nand0" also matches all of the other Allwinner SoCs. >=20 > Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller=20 support") > Signed-off-by: Samuel Holland Acked-by: Jernej Skrabec Best regards, Jernej > --- >=20 > drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/ sunxi/pinctrl-sun8i-a83t.c > index 4ada80317a3b..b5c1a8f363f3 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c > @@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[= ] =3D=20 { > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > - SUNXI_FUNCTION(0x2, "nand"), /* DQ6=20 */ > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6=20 */ > SUNXI_FUNCTION(0x3, "mmc2")), /* D6=20 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > - SUNXI_FUNCTION(0x2, "nand"), /* DQ7=20 */ > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7=20 */ > SUNXI_FUNCTION(0x3, "mmc2")), /* D7=20 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > - SUNXI_FUNCTION(0x2, "nand"), /* DQS=20 */ > + SUNXI_FUNCTION(0x2, "nand0"), /* DQS=20 */ > SUNXI_FUNCTION(0x3, "mmc2")), /* RST=20 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > - SUNXI_FUNCTION(0x2, "nand")), /* CE2=20 */ > + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > - SUNXI_FUNCTION(0x2, "nand")), /* CE3=20 */ > + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ > /* Hole */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), > SUNXI_FUNCTION(0x0, "gpio_in"), > --=20 > 2.35.1 >=20 >=20