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From: Michael Walle <michael@walle.cc>
To: "Vaibhaav Ram T.L" <vaibhaavram.tl@microchip.com>
Cc: gregkh@linuxfoundation.org, arnd@arndb.de,
	kumaravel.thiagarajan@microchip.com,
	tharunkumar.pasumarthi@microchip.com,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	UNGLinuxDriver@microchip.com
Subject: Re: [PATCH v11 char-misc-next 2/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX EEPROM via NVMEM sysfs
Date: Mon, 08 May 2023 08:44:04 +0200	[thread overview]
Message-ID: <78faf23f4f746f332dc53f7f981ac0fe@walle.cc> (raw)
In-Reply-To: <20230429120209.2232-3-vaibhaavram.tl@microchip.com>

Hi,

> @@ -219,6 +348,22 @@ static int pci1xxxx_otp_eeprom_probe(struct
> auxiliary_device *aux_dev,
>  		return -ENOMEM;
> 
>  	priv->pdev = aux_dev;
> +	priv->nvmem_config_eeprom.type = NVMEM_TYPE_EEPROM;
> +	priv->nvmem_config_eeprom.name = EEPROM_NAME;
> +	priv->nvmem_config_eeprom.dev = &aux_dev->dev;
> +	priv->nvmem_config_eeprom.owner = THIS_MODULE;
> +	priv->nvmem_config_eeprom.reg_read = pci1xxxx_eeprom_read;
> +	priv->nvmem_config_eeprom.reg_write = pci1xxxx_eeprom_write;
> +	priv->nvmem_config_eeprom.priv = priv;
> +	priv->nvmem_config_eeprom.stride = 1;
> +	priv->nvmem_config_eeprom.word_size = 1;
> +	priv->nvmem_config_eeprom.size = EEPROM_SIZE_BYTES;
> +
> +	priv->nvmem_eeprom = devm_nvmem_register(&aux_dev->dev,
> +						 &priv->nvmem_config_eeprom);
> +	if (!priv->nvmem_eeprom)
> +		return -ENOMEM;
> +
>  	priv->nvmem_config_otp.type = NVMEM_TYPE_OTP;
>  	priv->nvmem_config_otp.name = OTP_NAME;
>  	priv->nvmem_config_otp.dev = &aux_dev->dev;
> @@ -258,6 +403,9 @@ static int pci1xxxx_otp_eeprom_probe(struct
> auxiliary_device *aux_dev,
> 
>  	dev_set_drvdata(&aux_dev->dev, priv);
> 
> +	if (is_eeprom_responsive(priv))
> +		priv->is_eeprom_present = true;

What's this? The eeprom isn't there (or in whatever state), then you
still register the nvmem device, but read and write doesn't do anything
useful. You shouldn't register the device in the first place if it
is not functional.

-michael

  parent reply	other threads:[~2023-05-08  6:44 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20230429120209.2232-1-vaibhaavram.tl@microchip.com>
     [not found] ` <20230429120209.2232-2-vaibhaavram.tl@microchip.com>
2023-05-08  6:39   ` [PATCH v11 char-misc-next 1/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX OTP via NVMEM sysfs Michael Walle
     [not found] ` <20230429120209.2232-3-vaibhaavram.tl@microchip.com>
2023-05-08  6:44   ` Michael Walle [this message]
2023-05-15 14:44     ` [PATCH v11 char-misc-next 2/2] misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX EEPROM " VaibhaavRam.TL

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