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[64.207.253.118]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-85b1d363390sm2618813a34.1.2026.10.28.13.30.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Oct 2026 13:30:39 -0700 (PDT) Message-ID: <7981f7c6-c949-42e6-ad53-15e6530588cb@gmail.com> Date: Wed, 28 Oct 2026 15:30:38 -0500 X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] pinctrl: mediatek: common-v1: Use a raw spinlock for the pinctrl regmap To: Sebastian Andrzej Siewior Cc: Chen-Yu Tsai , Mark Brown , Lee Jones , Arnd Bergmann , Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bartosz Golaszewski , Clark Williams , Steven Rostedt , Yingjoe Chen , Chaotian Jing , Hongzhou Yang , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rt-devel@lists.linux.dev, mfd@lists.linux.dev References: <20260929-rbrue-suez-upstreaming-mtk-pinctrl-raw-regmap-v1-1-db92943f42cb@gmail.com> <20260930080609.dnK1-Uta@linutronix.de> <20261020073236.dDVmd3BW@linutronix.de> Content-Language: en-US From: Ryan Brue In-Reply-To: <20261020073236.dDVmd3BW@linutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/20/26 2:32 AM, Sebastian Andrzej Siewior wrote: > bulk writes could be a concern. The 40us delay is within the lock > acquired? If so, could this be done without the lock? I assume this is > part of the init sequence so nothing should use the HW so the writes > should not be interrupted by other writes to the device. Yes, it's under the lock. regmap_multi_reg_write() holds the regmap lock for the whole sequence, and since an MMIO syscon's regmap can't sleep, the delays are udelay()s. The PLL's enable runs that sequence (13 writes, 40 us of delays) whenever the PLL goes from off to on, retrying up to 10 times until it locks. In practice it's init-time, though. The G12A USB3/PCIe PHY takes the PLL with devm_clk_get_enabled() at probe and keeps it on, so it runs only once. Nothing else writes the PLL then, but the lock is the HHI syscon's, so on RT the other clocks in that block would wait it out. Running it without the lock would mean changing how the meson PLL code writes its init sequence, which I wouldn't want to take on in a pinctrl fix (unless that were preferred). > So it would be safe for now… Yes, that's the trade-off with the second option, which relies on the DIN never being written in a multi-step sequence. Nothing enforces that though. I'd like to send a v2 after -rc1, but I don't know the best option for the fix. Still waiting on Lee, Arnd, and Mark to pitch in if they have a preference, or any option I've missed. Best regards, Ryan Brue