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Wed, 03 Dec 2025 03:55:33 -0800 (PST) Received: from [192.168.100.198] ([182.180.105.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34910e7af86sm2540786a91.9.2025.12.03.03.55.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Dec 2025 03:55:32 -0800 (PST) Message-ID: <7b7145a9-cf3a-4feb-b3ea-862b9e98ff3c@gmail.com> Date: Wed, 3 Dec 2025 16:55:24 +0500 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] pinctrl: starfive: use dynamic GPIO base allocation To: kernel@esmil.dk, hal.feng@starfivetech.com, linus.walleij@linaro.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Emil Renner Berthing References: <20251026114241.53248-1-alitariq45892@gmail.com> Content-Language: en-US From: Ali Tariq In-Reply-To: <20251026114241.53248-1-alitariq45892@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, Just checking on the status of this v3 patch: “pinctrl: starfive: use dynamic GPIO base allocation”. It removes the deprecated static GPIO base and aligns the driver with current GPIO core guidelines. I didn’t see it in the tree yet, so I wanted to ask if anything else is needed from my side. I’m happy to send a v4 if any adjustments are required. Thanks for your time, Ali On 10/26/25 4:42 PM, Ali Tariq wrote: > The JH7110 pinctrl driver currently sets a static GPIO base number from > platform data: > > sfp->gc.base = info->gc_base; > > Static base assignment is deprecated and results in the following warning: > > gpio gpiochip0: Static allocation of GPIO base is deprecated, > use dynamic allocation. > > Set `sfp->gc.base = -1` to let the GPIO core dynamically allocate > the base number. This removes the warning and aligns the driver > with current GPIO guidelines. > > Since the GPIO base is now allocated dynamically, remove `gc_base` field in > `struct jh7110_pinctrl_soc_info` and the associated `JH7110_SYS_GC_BASE` > and `JH7110_AON_GC_BASE` constants as they are no longer used anywhere > in the driver. > > Tested on VisionFive 2 (JH7110 SoC). > > Signed-off-by: Ali Tariq > Reviewed-by: Emil Renner Berthing > --- > Changes in v3: > - Add Reviewed-by: Emil Renner Berthing > - Clarify commit message wording for readability > > Changes in v2: > - Remove unused gc_base field from struct jh7110_pinctrl_soc_info > - Drop unused JH7110_SYS_GC_BASE and JH7110_AON_GC_BASE defines > - Remove .gc_base assignments from jh7110_sys_pinctrl_info and jh7110_aon_pinctrl_info > - No functional change otherwise > --- > drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c | 2 -- > drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c | 2 -- > drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c | 2 +- > drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h | 1 - > 4 files changed, 1 insertion(+), 6 deletions(-) > > diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c > index cf42e204cbf0..3433b3c91692 100644 > --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c > +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c > @@ -29,7 +29,6 @@ > #include "pinctrl-starfive-jh7110.h" > > #define JH7110_AON_NGPIO 4 > -#define JH7110_AON_GC_BASE 64 > > #define JH7110_AON_REGS_NUM 37 > > @@ -138,7 +137,6 @@ static const struct jh7110_pinctrl_soc_info jh7110_aon_pinctrl_info = { > .pins = jh7110_aon_pins, > .npins = ARRAY_SIZE(jh7110_aon_pins), > .ngpios = JH7110_AON_NGPIO, > - .gc_base = JH7110_AON_GC_BASE, > .dout_reg_base = JH7110_AON_DOUT, > .dout_mask = GENMASK(3, 0), > .doen_reg_base = JH7110_AON_DOEN, > diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c > index 03c2ad808d61..9b67063a0b0b 100644 > --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c > +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c > @@ -29,7 +29,6 @@ > #include "pinctrl-starfive-jh7110.h" > > #define JH7110_SYS_NGPIO 64 > -#define JH7110_SYS_GC_BASE 0 > > #define JH7110_SYS_REGS_NUM 174 > > @@ -410,7 +409,6 @@ static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = { > .pins = jh7110_sys_pins, > .npins = ARRAY_SIZE(jh7110_sys_pins), > .ngpios = JH7110_SYS_NGPIO, > - .gc_base = JH7110_SYS_GC_BASE, > .dout_reg_base = JH7110_SYS_DOUT, > .dout_mask = GENMASK(6, 0), > .doen_reg_base = JH7110_SYS_DOEN, > diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c > index 05e3af75b09f..eb5cf8c067d1 100644 > --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c > +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c > @@ -938,7 +938,7 @@ int jh7110_pinctrl_probe(struct platform_device *pdev) > sfp->gc.set = jh7110_gpio_set; > sfp->gc.set_config = jh7110_gpio_set_config; > sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges; > - sfp->gc.base = info->gc_base; > + sfp->gc.base = -1; > sfp->gc.ngpio = info->ngpios; > > jh7110_irq_chip.name = sfp->gc.label; > diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h > index a33d0d4e1382..2da2d6858008 100644 > --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h > +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h > @@ -38,7 +38,6 @@ struct jh7110_pinctrl_soc_info { > const struct pinctrl_pin_desc *pins; > unsigned int npins; > unsigned int ngpios; > - unsigned int gc_base; > > /* gpio dout/doen/din/gpioinput register */ > unsigned int dout_reg_base;