From: icenowy-h8G6r0blFSE@public.gmane.org
To: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver
Date: Mon, 29 May 2017 21:19:06 +0800 [thread overview]
Message-ID: <7dd239497298ccd8e946c08d1d2a679f@aosc.io> (raw)
In-Reply-To: <20170529131100.a56rv3e5z3kpcxuo-SLa5LZP+eSXNLxjTenLetw@public.gmane.org>
在 2017-05-29 21:11，Chen-Yu Tsai 写道：
> On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:
>> R40 is said to be an upgrade of A20, and its pin configuration is also
>> similar to A20 (and thus similar to A10).
>>
>> Add support for R40 to the A10 pinctrl driver.
>>
>> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
>> ---
>> drivers/pinctrl/sunxi/Kconfig | 2 +-
>> drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272
>> +++++++++++++++++++++---------
>> 2 files changed, 197 insertions(+), 77 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/Kconfig
>> b/drivers/pinctrl/sunxi/Kconfig
>> index 624d84e6c936..9d01da3b90bd 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -7,7 +7,7 @@ config PINCTRL_SUNXI
>> select GPIOLIB
>>
>> config PINCTRL_SUN4I_A10
>> - def_bool MACH_SUN4I || MACH_SUN7I
>> + def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
>> select PINCTRL_SUNXI
>>
>> config PINCTRL_SUN5I
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>> b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>> index 159580c04b14..0f6ca8391ea7 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
>
> [...]
>
>> @@ -162,14 +183,19 @@ static const struct sunxi_desc_pin
>> sun4i_a10_pins[] = {
>> SUNXI_FUNCTION(0x3, "can"), /* RX */
>> SUNXI_FUNCTION(0x4, "uart1"), /* RING */
>> SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
>> - PINCTRL_SUN7I_A20),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40),
>> SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
>> - PINCTRL_SUN7I_A20)),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40)),
>> /* Hole */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>> + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
>> + SUNXI_FUNCTION_VARIANT(0x3,
>> + "pll-lock-dbg",
>
> Can you stick to underscores to be consistent?
OK...
This is a so strange pin name and I just picked the datasheet
name.
I don't care how to name it as I don't even know what this is.
>
>> + PINCTRL_SUN8I_R40)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> @@ -177,11 +203,19 @@ static const struct sunxi_desc_pin
>> sun4i_a10_pins[] = {
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
>> + SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
>> + PINCTRL_SUN4I_A10 |
>> + PINCTRL_SUN7I_A20),
>> + SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
>> + PINCTRL_SUN8I_R40)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> - SUNXI_FUNCTION(0x2, "ir0"), /* TX */
>> + SUNXI_FUNCTION_VARIANT(0x2, "ir0", /* TX */
>> + PINCTRL_SUN4I_A10 |
>> + PINCTRL_SUN7I_A20),
>> + SUNXI_FUNCTION_VARIANT(0x3, "pwm0", /* PWM1 */
>
> The numbering is wrong. Just drop the number altogether, like all the
> other instances.
>
>> + PINCTRL_SUN8I_R40),
>> /*
>> * The SPDIF block is not referenced at all in the A10 user
>> * manual. However it is described in the code leaked and the
>> @@ -205,7 +239,8 @@ static const struct sunxi_desc_pin
>> sun4i_a10_pins[] = {
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */
>> PINCTRL_SUN4I_A10),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
>> - PINCTRL_SUN7I_A20),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40),
>
> Maybe we could use "i2s" instead, like on the A10. I don't know where
> i2s1 is used, but it certainly isn't routed outside the SoC, and i2s2
> looks like it's for dw-hdmi's audio path.
Nope, it's routed at PA bank, see pins start at PA14.
Changing this name will also break existing A20 device trees, if any of
them use I2S.
>
>> SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>
> [...]
>
>> @@ -237,31 +275,41 @@ static const struct sunxi_desc_pin
>> sun4i_a10_pins[] = {
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */
>> PINCTRL_SUN4I_A10),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */
>> - PINCTRL_SUN7I_A20)),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40),
>> + SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM6 */
>> + PINCTRL_SUN8I_R40)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */
>> PINCTRL_SUN4I_A10),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */
>> - PINCTRL_SUN7I_A20)),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40),
>> + SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM7 */
>> + PINCTRL_SUN8I_R40)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */
>> PINCTRL_SUN4I_A10),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */
>> - PINCTRL_SUN7I_A20)),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */
>> PINCTRL_SUN4I_A10),
>> SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */
>> - PINCTRL_SUN7I_A20),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40),
>> SUNXI_FUNCTION(0x3, "ac97"), /* DI */
>> /* Undocumented mux function on A10 - See SPDIF MCLK above */
>> - SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */
>> + SUNXI_FUNCTION_VARIANT(0x4, "spdif", /* SPDIF IN */
>> + PINCTRL_SUN4I_A10 |
>> + PINCTRL_SUN7I_A20)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> @@ -308,7 +356,9 @@ static const struct sunxi_desc_pin
>> sun4i_a10_pins[] = {
>
> You missed PWM4 and PWM5 on pins PB20 and PB21.
>
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "uart0"), /* TX */
>> - SUNXI_FUNCTION(0x3, "ir1")), /* TX */
>> + SUNXI_FUNCTION_VARIANT(0x3, "ir1", /* TX */
>> + PINCTRL_SUN4I_A10 |
>> + PINCTRL_SUN7I_A20)),
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>
> [...]
>
>> @@ -916,7 +1000,10 @@ static const struct sunxi_desc_pin
>> sun4i_a10_pins[] = {
>> SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */
>> PINCTRL_SUN4I_A10),
>> SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */
>> - PINCTRL_SUN7I_A20),
>> + PINCTRL_SUN7I_A20 |
>> + PINCTRL_SUN8I_R40),
>> + SUNXI_FUNCTION_VARIANT(0x5, "sim", /* DET */
>> + PINCTRL_SUN8I_R40),
>
> This is available on all 3 variants.
>
> Should we consider sending a fix for this first? The hardware backing
> this pin is not supported, but it would be less confusing to fix it
> first instead of introducing a function for all variants in a patch
> supposedly for just the R40.
OK.
But if we do so I think I should delay this patch until the A10-A20
driver merge is applied...
>
>> SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
>> SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
>> SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
>
> [...]
>
> Looks good otherwise.
>
>
> Regards
> ChenYu
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2017-05-29 13:19 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-27 10:22 [PATCH v3 00/10] Initial Allwinner R40 support Icenowy Zheng
2017-05-27 10:22 ` [PATCH v3 01/10] arm: sunxi: add support for R40 SoC Icenowy Zheng
2017-05-28 14:57 ` Chen-Yu Tsai
2017-05-31 19:42 ` Rob Herring
2017-05-27 10:23 ` [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs Icenowy Zheng
[not found] ` <20170527102308.1988-3-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-28 14:58 ` Chen-Yu Tsai
2017-05-29 16:33 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 03/10] pinctrl: sunxi: add A20 support to A10 driver Icenowy Zheng
[not found] ` <20170527102308.1988-4-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-28 15:06 ` Chen-Yu Tsai
2017-05-29 16:35 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 04/10] pinctrl: sunxi: drop dedicated A20 driver Icenowy Zheng
[not found] ` <20170527102308.1988-5-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-28 15:08 ` Chen-Yu Tsai
2017-05-29 16:39 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl Icenowy Zheng
2017-05-28 15:09 ` Chen-Yu Tsai
[not found] ` <20170527102308.1988-6-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-29 16:40 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver Icenowy Zheng
2017-05-29 13:11 ` Chen-Yu Tsai
[not found] ` <20170529131100.a56rv3e5z3kpcxuo-SLa5LZP+eSXNLxjTenLetw@public.gmane.org>
2017-05-29 13:19 ` icenowy-h8G6r0blFSE [this message]
2017-05-29 13:25 ` Chen-Yu Tsai
2017-05-29 16:43 ` Linus Walleij
[not found] ` <20170527102308.1988-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-27 10:23 ` [PATCH v3 07/10] dt-bindings: add compatible string for Allwinner R40 CCU Icenowy Zheng
2017-05-28 15:09 ` Chen-Yu Tsai
2017-08-19 8:17 ` Chen-Yu Tsai
2017-05-27 10:23 ` [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC Icenowy Zheng
2017-05-29 7:34 ` Chen-Yu Tsai
2017-07-22 3:00 ` icenowy
2017-08-12 4:04 ` Chen-Yu Tsai
2017-08-12 4:51 ` icenowy
2017-08-12 5:16 ` Chen-Yu Tsai
2017-08-12 4:04 ` icenowy
2017-08-12 4:05 ` Chen-Yu Tsai
2017-05-27 10:23 ` [PATCH v3 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 Icenowy Zheng
[not found] ` <20170527102308.1988-10-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-29 8:15 ` Chen-Yu Tsai
2017-05-27 10:23 ` [PATCH v3 10/10] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng
2017-05-29 8:59 ` Chen-Yu Tsai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7dd239497298ccd8e946c08d1d2a679f@aosc.io \
--to=icenowy-h8g6r0blfse@public.gmane.org \
--cc=devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org \
--cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
--cc=linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org \
--cc=robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \
--cc=wens-jdAy2FN1RRM@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).