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Sun, 11 Jan 2026 06:42:41 -0800 (PST) Message-ID: <858ca139-61c5-45e3-a2c9-d0af414e3592@tuxon.dev> Date: Sun, 11 Jan 2026 16:42:36 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: claudiu beznea Subject: Re: [PATCH v4 15/15] arm64: dts: microchip: add EV23X71A board To: Robert Marko , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, herbert@gondor.apana.org.au, davem@davemloft.net, vkoul@kernel.org, andi.shyti@kernel.org, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, linusw@kernel.org, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, olivia@selenic.com, radu_nicolae.pirea@upb.ro, richard.genoud@bootlin.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, broonie@kernel.org, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org Cc: luka.perkov@sartura.hr References: <20251229184004.571837-1-robert.marko@sartura.hr> <20251229184004.571837-16-robert.marko@sartura.hr> Content-Language: en-US In-Reply-To: <20251229184004.571837-16-robert.marko@sartura.hr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, Robert, On 12/29/25 20:37, Robert Marko wrote: > Microchip EV23X71A is an LAN9696 based evaluation board. > > Signed-off-by: Robert Marko > --- > Changes in v2: > * Split from SoC DTSI commit > * Apply DTS coding style > * Enclose array in i2c-mux > * Alphanumericaly sort nodes > * Change management port mode to RGMII-ID > > arch/arm64/boot/dts/microchip/Makefile | 1 + > .../boot/dts/microchip/lan9696-ev23x71a.dts | 757 ++++++++++++++++++ > 2 files changed, 758 insertions(+) > create mode 100644 arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts > > diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile > index c6e0313eea0f..09d16fc1ce9a 100644 > --- a/arch/arm64/boot/dts/microchip/Makefile > +++ b/arch/arm64/boot/dts/microchip/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_LAN969X) += lan9696-ev23x71a.dtb > dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb > dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb > dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb > diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts > new file mode 100644 > index 000000000000..435df455b078 > --- /dev/null > +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts [ ...] > +&gpio { > + emmc_sd_pins: emmc-sd-pins { > + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ > + pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", > + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", > + "GPIO_22", "GPIO_23", "GPIO_24"; > + function = "emmc_sd"; > + }; > + > + fan_pins: fan-pins { > + pins = "GPIO_25", "GPIO_26"; > + function = "fan"; > + }; > + > + fc0_pins: fc0-pins { > + pins = "GPIO_3", "GPIO_4"; > + function = "fc"; > + }; > + > + fc2_pins: fc2-pins { > + pins = "GPIO_64", "GPIO_65", "GPIO_66"; > + function = "fc"; > + }; > + > + fc3_pins: fc3-pins { > + pins = "GPIO_55", "GPIO_56"; > + function = "fc"; > + }; > + > + mdio_pins: mdio-pins { > + pins = "GPIO_9", "GPIO_10"; > + function = "miim"; > + }; > + > + mdio_irq_pins: mdio-irq-pins { > + pins = "GPIO_11"; > + function = "miim_irq"; > + }; > + > + sgpio_pins: sgpio-pins { > + /* SCK, D0, D1, LD */ > + pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; > + function = "sgpio_a"; > + }; > + > + usb_ulpi_pins: usb-ulpi-pins { > + pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", > + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", > + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; > + function = "usb_ulpi"; > + }; > + > + usb_rst_pins: usb-rst-pins { > + pins = "GPIO_12"; > + function = "usb2phy_rst"; > + }; > + > + usb_over_pins: usb-over-pins { > + pins = "GPIO_13"; > + function = "usb_over_detect"; > + }; > + > + usb_power_pins: usb-power-pins { > + pins = "GPIO_1"; > + function = "usb_power"; > + }; > + > + ptp_out_pins: ptp-out-pins { > + pins = "GPIO_58"; > + function = "ptpsync_4"; > + }; Could you please move this one upper to have all the entries in the gpio container alphanumerically sorted? > + > + ptp_ext_pins: ptp-ext-pins { > + pins = "GPIO_59"; > + function = "ptpsync_5"; > + }; Same here. [ ...] > + port29: port@29 { > + reg = <29>; > + phys = <&serdes 11>; > + phy-handle = <&phy3>; > + phy-mode = "rgmii-id"; > + microchip,bandwidth = <1000>; There are some questions around this node from Andrew in v1 of this series, which I don't see an answer for in any of the following versions. Could you please clarify? The rest looks good to me. Thank you, Claudiu