From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A03D5C433EF for ; Mon, 25 Jul 2022 06:55:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232690AbiGYGzL (ORCPT ); Mon, 25 Jul 2022 02:55:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232177AbiGYGyx (ORCPT ); Mon, 25 Jul 2022 02:54:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B87C912AF2 for ; Sun, 24 Jul 2022 23:54:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 493836114D for ; Mon, 25 Jul 2022 06:54:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9944DC341CE; Mon, 25 Jul 2022 06:54:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658732047; bh=UFtD3GoQGq4MGujQq6IORpJ28F7R/QEABkIyQdIBtzU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=UORK/F0krQDDSTfI4x6pm4yEpAkvCfDV2iPN8gWcNyA9poqQBiYH9dDdcZ2RUuU1p pS5fF7CMmTHrtm/oS/BzaL96WBrhn2JXJdHdKsiElWm/+5FZT0pLH7O3sj8up4TOg2 P2IdbZaVHiBPnMbPY+R7j54nmKD1/FYuV+2UneP6pgncYKxXvk+k9Zzc/gbxSVh15q lp73n72FqT36vsctZFffDGIiSJqECl59Ai/r+amvzhlb/E32504BDFrNWz6tyZEOAk 2MW02p5m5YXJekCPn5PRiw70LqDNa+sAZQzsUqMboVS3OcRTF4qaGW6A5qnWqeB4Cj U/swKnWbyeMWQ== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oFryf-009mAx-AP; Mon, 25 Jul 2022 07:54:05 +0100 Date: Mon, 25 Jul 2022 07:53:59 +0100 Message-ID: <871qu9d6ns.wl-maz@kernel.org> From: Marc Zyngier To: Marek Vasut Cc: linux-gpio@vger.kernel.org, Bartosz Golaszewski , Linus Walleij , Loic Poulain , NXP Linux Team , Peng Fan , Shawn Guo Subject: Re: [PATCH v3 1/2] gpio: mxc: Protect GPIO irqchip RMW with bgpio spinlock In-Reply-To: References: <20220724171057.18549-1-marex@denx.de> <87fsiqxuvd.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: marex@denx.de, linux-gpio@vger.kernel.org, bgolaszewski@baylibre.com, linus.walleij@linaro.org, loic.poulain@linaro.org, linux-imx@nxp.com, peng.fan@nxp.com, shawnguo@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Sun, 24 Jul 2022 19:15:26 +0100, Marek Vasut wrote: > > On 7/24/22 19:50, Marc Zyngier wrote: > > [...] > > >> +++ b/drivers/gpio/gpio-mxc.c > >> @@ -147,6 +147,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > >> { > >> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); > >> struct mxc_gpio_port *port = gc->private; > >> + unsigned long flags; > >> u32 bit, val; > >> u32 gpio_idx = d->hwirq; > >> int edge; > >> @@ -185,6 +186,8 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > >> return -EINVAL; > >> } > >> + spin_lock_irqsave(&port->gc.bgpio_lock, flags); > > > > In my tree, bgpio is a raw spinlock, and has been since 3c938cc5cebcb. > > > > Now, looking a bit closer at this code, I have to withdraw my earlier > > comment about the lack of mutual exclusion in the existing code. All > > writes are of the form: > > > > writel(single_bit_mask, some_addr + MXS_{SET,CLR}); > > > > which indicates that the write side can be accessed with a hot-bit > > pattern, avoiding a RWM pattern and thus the need for a lock. > > Only for the ISR/IMR, not for the GDIR register, that's why the locks > are added only around the RMW which don't have these "hot bits". Only your patch adds any GDIR access. > > Your second patch, however requires the lock. I'm not sure it is safe > > to do after the interrupt type has been configured though. You may > > want to refer to the TRM for this. > > There is in fact another unprotected RMW in gpio_set_irq_type() , look > for GPIO_EDGE_SEL, so the locks should be valid as they are now, right > ? I seem to be confused with gpio-mxs.c, and gpio-mxc indeed needs the lock. However, you have totally ignored my earlier comments in your v4: - This doesn't compile, as bgpio_lock has been changed to a *raw* spinlock. You obviously haven't even bothered testing your patch. - I asked for a cover letter for any series with multiple patch. That's not exactly a new requirement. So we got 4 versions in just over 24 hours, none of which actually work. Do you see the overarching problem? M. -- Without deviation from the norm, progress is not possible.