From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA4ACC433DB for ; Sun, 24 Jan 2021 06:18:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC6F4206F9 for ; Sun, 24 Jan 2021 06:18:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726038AbhAXGRy (ORCPT ); Sun, 24 Jan 2021 01:17:54 -0500 Received: from guitar.tcltek.co.il ([192.115.133.116]:57288 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725803AbhAXGRx (ORCPT ); Sun, 24 Jan 2021 01:17:53 -0500 Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 29867440205; Sun, 24 Jan 2021 08:17:07 +0200 (IST) References: User-agent: mu4e 1.4.14; emacs 27.1 From: Baruch Siach To: Bartosz Golaszewski Cc: Thierry Reding , Uwe =?utf-8?Q?Kleine-K?= =?utf-8?Q?=C3=B6nig?= , Lee Jones , Linus Walleij , Rob Herring , Andrew Lunn , Gregory Clement , Russell King , Sebastian Hesselbarth , Thomas Petazzoni , Chris Packham , Sascha Hauer , Ralph Sennhauser , linux-pwm@vger.kernel.org, linux-gpio , arm-soc , linux-devicetree Subject: Re: [PATCH v7 1/3] gpio: mvebu: add pwm support for Armada 8K/7K In-reply-to: Date: Sun, 24 Jan 2021 08:17:06 +0200 Message-ID: <87a6syeu59.fsf@tarshish> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Bartosz, Thanks for you review. On Fri, Jan 22 2021, Bartosz Golaszewski wrote: > On Mon, Jan 11, 2021 at 12:47 PM Baruch Siach wrote: >> Use the marvell,pwm-offset DT property to store the location of PWM >> signal duration registers. >> >> Since we have more than two GPIO chips per system, we can't use the >> alias id to differentiate between them. Use the offset value for that. >> >> Signed-off-by: Baruch Siach [...] >> + regmap_write(mvchip->regs, >> + GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); > > Can you confirm that this line is on purpose and that it should be > executed even for chips that use a separate regmap for PWM? Yes. The blink counter selection register is at the same offset is all chips that support the GPIO blink feature. Only the on/off registers offset is different. baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -