From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AB57C43334 for ; Sun, 24 Jul 2022 17:50:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229552AbiGXRuw (ORCPT ); Sun, 24 Jul 2022 13:50:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229542AbiGXRuu (ORCPT ); Sun, 24 Jul 2022 13:50:50 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 047E87679 for ; Sun, 24 Jul 2022 10:50:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9D5986117C for ; Sun, 24 Jul 2022 17:50:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5D48C3411E; Sun, 24 Jul 2022 17:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658685049; bh=iOtPCQTdQv0sAgzAPG97sT73/mczhENGL6zxUOdVa8M=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=D0cQNroQ2AA1c4y1ouqb5Fu2QHbC4upuvklfiN8XQYanm785ZghmyN7AII60Pp48t zrDSqKg08UKnMkUF27M1u4GMikfoHicUtyVqRMLauZTMO9YJmQGnuj311QMMufO7lt 36EtJHF9oCYorIyCwUHh6RLIIpbY+CivBC/arfyUeuSWsbmCwjmPw9m+LvPOJBNYfg 6/Gr8aqikMsa/TAwJp/1f1u6hpuUfGKLA6/iyCA74SPR2PuP/X+4vGSAoIFVAp88dF WWqLXXiyY6VxVgha/G3rEKPMJbS0iyCMoJWr8CdrcToKKcHY7bT7uEN/YI55dzGp9w JL0QlPp6NW7yw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oFfkc-009hyk-Ir; Sun, 24 Jul 2022 18:50:46 +0100 Date: Sun, 24 Jul 2022 18:50:46 +0100 Message-ID: <87fsiqxuvd.wl-maz@kernel.org> From: Marc Zyngier To: Marek Vasut Cc: linux-gpio@vger.kernel.org, Bartosz Golaszewski , Linus Walleij , Loic Poulain , NXP Linux Team , Peng Fan , Shawn Guo Subject: Re: [PATCH v3 1/2] gpio: mxc: Protect GPIO irqchip RMW with bgpio spinlock In-Reply-To: <20220724171057.18549-1-marex@denx.de> References: <20220724171057.18549-1-marex@denx.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: marex@denx.de, linux-gpio@vger.kernel.org, bgolaszewski@baylibre.com, linus.walleij@linaro.org, loic.poulain@linaro.org, linux-imx@nxp.com, peng.fan@nxp.com, shawnguo@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Where is the cover letter? If sending more than a single patch, please include one. On Sun, 24 Jul 2022 18:10:56 +0100, Marek Vasut wrote: > > The driver currently performs register read-modify-write without locking > in its irqchip part, this could lead to a race condition when configuring > interrupt mode setting. Add the missing bgpio spinlock lock/unlock around > the register read-modify-write. > > Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") > Signed-off-by: Marek Vasut > Cc: Bartosz Golaszewski > Cc: Linus Walleij > Cc: Loic Poulain > Cc: Marc Zyngier > Cc: NXP Linux Team > Cc: Peng Fan > Cc: Shawn Guo > --- > V3: New patch > --- > drivers/gpio/gpio-mxc.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c > index c871602fc5ba9..74a50139c9202 100644 > --- a/drivers/gpio/gpio-mxc.c > +++ b/drivers/gpio/gpio-mxc.c > @@ -147,6 +147,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > { > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); > struct mxc_gpio_port *port = gc->private; > + unsigned long flags; > u32 bit, val; > u32 gpio_idx = d->hwirq; > int edge; > @@ -185,6 +186,8 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > return -EINVAL; > } > > + spin_lock_irqsave(&port->gc.bgpio_lock, flags); In my tree, bgpio is a raw spinlock, and has been since 3c938cc5cebcb. Now, looking a bit closer at this code, I have to withdraw my earlier comment about the lack of mutual exclusion in the existing code. All writes are of the form: writel(single_bit_mask, some_addr + MXS_{SET,CLR}); which indicates that the write side can be accessed with a hot-bit pattern, avoiding a RWM pattern and thus the need for a lock. Your second patch, however requires the lock. I'm not sure it is safe to do after the interrupt type has been configured though. You may want to refer to the TRM for this. M. -- Without deviation from the norm, progress is not possible.