From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 142C7C433EF for ; Wed, 6 Jul 2022 07:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231180AbiGFHCq (ORCPT ); Wed, 6 Jul 2022 03:02:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231389AbiGFHCb (ORCPT ); Wed, 6 Jul 2022 03:02:31 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1BBB20191; Wed, 6 Jul 2022 00:02:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3EDF861DA8; Wed, 6 Jul 2022 07:02:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A80EC3411C; Wed, 6 Jul 2022 07:02:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657090949; bh=dHnpslg4D2Iqrhe64MOAwfZyhz2n2bJgiGLBsNy4Y7o=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=NOsD6YvfXM++X57BkQDilD3MF0Hr3witgXGzJLsBZ7l6udoCZolC6LAQL2EBfymqd RIssw+c+OIYU2FN7oTs0bT65o7FsmuO1qaG6S/5uVLKXD4KioVLDwHbCVBiOu+Nv3d Zxgv1aiaFlvw62DixlBfW7+O5C0/RsTIO6Q5cUcxBgLe8CyZQcmB5N2YiRHnNpg7HJ gzBUkonkjNzmgNLKdyzC2h456YFa7WXSqwjBJg9JY2bGkn3A22JApf3cDFulNQqzoh gL4/Y1MY69hyiYyFjc7lXHynRqqXL90DE2F3r7PPtonJoWMNQqf8QlYWN56BQeH/Uh A7oaekjR0dEGA== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o8z3L-005YCw-4A; Wed, 06 Jul 2022 08:02:27 +0100 Date: Wed, 06 Jul 2022 08:02:20 +0100 Message-ID: <87h73un2pv.wl-maz@kernel.org> From: Marc Zyngier To: Lad Prabhakar Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Subject: Re: [PATCH v7 0/5] Renesas RZ/G2L IRQC support In-Reply-To: <20220703194020.78701-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220703194020.78701-1-prabhakar.mahadev-lad.rj@bp.renesas.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: prabhakar.csengg@gmail.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, geert+renesas@glider.be, linus.walleij@linaro.org, brgl@bgdev.pl, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Sun, 03 Jul 2022 20:40:15 +0100, Lad Prabhakar wrote: > > Hi All, > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > Renesas RZ/G2L SoC's with below pins: > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI > interrupts > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > - NMI edge select. > > _____________ > | GIC | > | ________ | > ____________ | | | | > NMI --------------------------------->| | SPI0-479 | | GIC-600| | > _______ | |------------>| | | > | | | | PPI16-31 | | | | > | | IRQ0-IRQ7 | IRQC |------------>| | | > P0_P48_4 --->| GPIO |---------------->| | | |________| | > | |GPIOINT0-122 | | | | > | |---------------->| TINT0-31 | | | > |______| |__________| |____________| > > The proposed patches add hierarchical IRQ domain, one in IRQC driver and > another in pinctrl driver. Upon interrupt requests map the interrupt to > GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is > handled by the pinctrl and IRQC driver. > > Cheers, > Prabhakar > > v6->v7: > * Used devm_reset_control_get_exclusive() instead of > devm_reset_control_get_exclusive_by_index() > * Included RB tag from Linus for patch 5/5 > * Switched to newer version of populate_parent_alloc_arg() (patch depends > on https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/ > patch/?id=178b7e21459e9a7e2a2c369711ef0cc9b1cfbcd7) Please add this patch as part of the series. M. -- Without deviation from the norm, progress is not possible.