[PATCH 0/4] Add support for nuvoton ma35d1 pin control

[PATCH 0/4] Add support for nuvoton ma35d1 pin control

[Jacky Huang]

From: Jacky Huang <ychuang3@nuvoton.com>

This patch series adds the pin control and GPIO driver for the nuvoton ma35d1
ARMv8 SoC. It includes DT binding documentation, the ma35d1 pin control driver,
and device tree updates.

This pin control driver has been tested on the ma35d1 som board with Linux 6.6.

Jacky Huang (4):
  dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management
    node
  dt-bindings: pinctrl: Document nuvoton ma35d1 pin control
  arm64: dts: nuvoton: Add pinctrl support for ma35d1
  pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver

 .../pinctrl/nuvoton,ma35d1-pinctrl.yaml       |  180 ++
 .../bindings/reset/nuvoton,ma35d1-reset.yaml  |    3 +-
 .../boot/dts/nuvoton/ma35d1-iot-512m.dts      |   83 +-
 .../boot/dts/nuvoton/ma35d1-som-256m.dts      |   86 +-
 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi       |  175 +-
 drivers/pinctrl/nuvoton/Kconfig               |   22 +
 drivers/pinctrl/nuvoton/Makefile              |    2 +
 drivers/pinctrl/nuvoton/pinctrl-ma35.c        | 1239 ++++++++++++
 drivers/pinctrl/nuvoton/pinctrl-ma35.h        |   50 +
 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c      | 1797 +++++++++++++++++
 include/dt-bindings/pinctrl/ma35d1-pinfunc.h  |   38 +
 11 files changed, 3665 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.c
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.h
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
 create mode 100644 include/dt-bindings/pinctrl/ma35d1-pinfunc.h

-- 
2.34.1

[PATCH 1/4] dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node

[Jacky Huang]

From: Jacky Huang <ychuang3@nuvoton.com>

Add compatible 'syscon' to the system-management node.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 .../devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml        | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
index 34c5c1c08ec1..3ce7dcecd87a 100644
--- a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
@@ -18,6 +18,7 @@ properties:
   compatible:
     items:
       - const: nuvoton,ma35d1-reset
+      - const: syscon
 
   reg:
     maxItems: 1
@@ -37,7 +38,7 @@ examples:
   - |
 
     system-management@40460000 {
-        compatible = "nuvoton,ma35d1-reset";
+        compatible = "nuvoton,ma35d1-reset", "syscon";
         reg = <0x40460000 0x200>;
         #reset-cells = <1>;
     };
-- 
2.34.1

Re: [PATCH 1/4] dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node

[Krzysztof Kozlowski]

On 11/10/2023 11:05, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@nuvoton.com>
> 
> Add compatible 'syscon' to the system-management node.

Why? Commit msg should answer to this.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node

[Jacky Huang]

Dear Krzysztof,

Thank you for the review.


On 2023/10/13 上午 03:30, Krzysztof Kozlowski wrote:
> On 11/10/2023 11:05, Jacky Huang wrote:
>> From: Jacky Huang <ychuang3@nuvoton.com>
>>
>> Add compatible 'syscon' to the system-management node.
> Why? Commit msg should answer to this.
>
> Best regards,
> Krzysztof
>

I added 'syscon' because system control registers are mapped by this driver.
The pinctrl driver needs to access the system control registers through 
'regmap'
with a phandle referring to this node.
I will update the commit message to provide a more detailed explanation
of its purpose.

Best Regards,
Jacky Huang

Re: [PATCH 1/4] dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node

[Rob Herring]

On Wed, Oct 11, 2023 at 09:05:07AM +0000, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@nuvoton.com>
> 
> Add compatible 'syscon' to the system-management node.
> 
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> ---
>  .../devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml        | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
> index 34c5c1c08ec1..3ce7dcecd87a 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
> @@ -18,6 +18,7 @@ properties:
>    compatible:
>      items:
>        - const: nuvoton,ma35d1-reset
> +      - const: syscon

Presumably you already have a driver for nuvoton,ma35d1-reset, so just 
make it create a regmap. I assume this is the reason you want to add 
'syscon'?

Rob

Re: [PATCH 1/4] dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node

[Jacky Huang]

Dear Rob,

Thank you for the review.

On 2023/10/13 上午 04:39, Rob Herring wrote:
> On Wed, Oct 11, 2023 at 09:05:07AM +0000, Jacky Huang wrote:
>> From: Jacky Huang <ychuang3@nuvoton.com>
>>
>> Add compatible 'syscon' to the system-management node.
>>
>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>> ---
>>   .../devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml        | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
>> index 34c5c1c08ec1..3ce7dcecd87a 100644
>> --- a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
>> +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
>> @@ -18,6 +18,7 @@ properties:
>>     compatible:
>>       items:
>>         - const: nuvoton,ma35d1-reset
>> +      - const: syscon
> Presumably you already have a driver for nuvoton,ma35d1-reset, so just
> make it create a regmap. I assume this is the reason you want to add
> 'syscon'?
>
> Rob

Yes, we have a driver for 'nuvoton,ma35d1-reset' with a register space 
mapped to
the system control registers. The other ma35d1 drivers may also require 
access
to the system control registers. I added 'syscon' to this node so that 
other drivers
can utilize 'regmap' via the phandle of this node.

Best Regards,
Jacky Huang

[PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Jacky Huang]

From: Jacky Huang <ychuang3@nuvoton.com>

Add the dt-bindings header for nuvoton ma35d1 pinctrl, that gets shared
between the pin control driver and pin configuration in the dts.

Add documentation to describe nuvoton ma35d1 pin control and GPIO.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 .../pinctrl/nuvoton,ma35d1-pinctrl.yaml       | 180 ++++++++++++++++++
 include/dt-bindings/pinctrl/ma35d1-pinfunc.h  |  38 ++++
 2 files changed, 218 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
 create mode 100644 include/dt-bindings/pinctrl/ma35d1-pinfunc.h

diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
new file mode 100644
index 000000000000..0ddedbad4b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 pin control and GPIO
+
+maintainers:
+  - Shan-Chun Hung <schung@nuvoton.com>
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,ma35d1-pinctrl
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  nuvoton,sys:
+    description:
+      phandle to the syscon node
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      maxItems: 1
+
+  ranges: true
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+patternProperties:
+  "gpio[a-n]@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+    properties:
+
+      gpio-controller: true
+
+      '#gpio-cells':
+        const: 2
+
+      reg:
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      interrupt-controller: true
+
+      '#interrupt-cells':
+        const: 2
+
+      interrupts:
+        description:
+          The interrupt outputs to sysirq.
+        maxItems: 1
+
+    required:
+      - reg
+      - interrupts
+      - interrupt-controller
+      - '#interrupt-cells'
+      - gpio-controller
+      - '#gpio-cells'
+
+  "pcfg-[a-z0-9-.]+$":
+    type: object
+    description:
+      A pinctrl node should contain at least one subnodes representing the
+      pinctrl groups available on the machine. Each subnode will list the
+      pins it needs, and how they should be configured, with regard to muxer
+      configuration, pullups, drive strength, input enable/disable and input
+      schmitt.
+
+    allOf:
+      - $ref: pincfg-node.yaml#
+
+    properties:
+      bias-disable: true
+
+      bias-pull-down: true
+
+      bias-pull-up: true
+
+      drive-strength:
+        minimum: 0
+        maximum: 7
+
+      input-enable: true
+
+      input-schmitt-enable: true
+
+      power-source:
+        description:
+          I/O voltage in millivolt.
+        enum: [ 1800, 3300 ]
+
+additionalProperties:
+  type: object
+  additionalProperties:
+    type: object
+    properties:
+      nuvoton,pin:
+        description:
+          Each entry consists of 4 parameters and represents the mux and config
+          setting for one pin.
+        $ref: /schemas/types.yaml#/definitions/uint32-matrix
+        minItems: 1
+        items:
+          items:
+            - minimum: 0x80
+              maximum: 0xec
+              description:
+                The pinctrl register offset in syscon registers.
+            - minimum: 0
+              maximum: 30
+              description:
+                The bit offset in the pinctrl register.
+            - minimum: 0
+              maximum: 15
+              description:
+                The multi-function pin value.
+            - description:
+                The phandle of a node contains the generic pinconfig options
+                to use as described in pinctrl-bindings.txt.
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+    #include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
+
+    pinctrl@40040000 {
+        compatible = "nuvoton,ma35d1-pinctrl";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        nuvoton,sys = <&sys>;
+        ranges = <0 0x40040000 0xc00>;
+
+        gpioa@40040000 {
+                reg = <0x0 0x40>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk GPA_GATE>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        pcfg_default: pcfg-default {
+                slew-rate = <0>;
+                input-schmitt-disable;
+                bias-disable;
+                power-source = <3300>;
+                drive-strength = <0>;
+        };
+    };
+
+    pinctrl {
+        uart13 {
+                pinctrl_uart13: uart13grp {
+                        nuvoton,pins =
+                                <MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
+                                <MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
+                };
+        };
+    };
+
+    serial@407d0000 {
+        compatible = "nuvoton,ma35d1-uart";
+        reg = <0x407d0000 0x100>;
+        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk UART13_GATE>;
+        pinctrl-0 = <&pinctrl_uart13>;
+    };
diff --git a/include/dt-bindings/pinctrl/ma35d1-pinfunc.h b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
new file mode 100644
index 000000000000..a2609d466dc9
--- /dev/null
+++ b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Nuvoton Technologies.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
+#define __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
+
+#define MA35_SYS_REG_GPA_L	0x80
+#define MA35_SYS_REG_GPA_H	0x84
+#define MA35_SYS_REG_GPB_L	0x88
+#define MA35_SYS_REG_GPB_H	0x8c
+#define MA35_SYS_REG_GPC_L	0x90
+#define MA35_SYS_REG_GPC_H	0x94
+#define MA35_SYS_REG_GPD_L	0x98
+#define MA35_SYS_REG_GPD_H	0x9c
+#define MA35_SYS_REG_GPE_L	0xa0
+#define MA35_SYS_REG_GPE_H	0xa4
+#define MA35_SYS_REG_GPF_L	0xa8
+#define MA35_SYS_REG_GPF_H	0xac
+#define MA35_SYS_REG_GPG_L	0xb0
+#define MA35_SYS_REG_GPG_H	0xb4
+#define MA35_SYS_REG_GPH_L	0xb8
+#define MA35_SYS_REG_GPH_H	0xbc
+#define MA35_SYS_REG_GPI_L	0xc0
+#define MA35_SYS_REG_GPI_H	0xc4
+#define MA35_SYS_REG_GPJ_L	0xc8
+#define MA35_SYS_REG_GPJ_H	0xcc
+#define MA35_SYS_REG_GPK_L	0xd0
+#define MA35_SYS_REG_GPK_H	0xd4
+#define MA35_SYS_REG_GPL_L	0xd8
+#define MA35_SYS_REG_GPL_H	0xdc
+#define MA35_SYS_REG_GPM_L	0xe0
+#define MA35_SYS_REG_GPM_H	0xe4
+#define MA35_SYS_REG_GPN_L	0xe8
+#define MA35_SYS_REG_GPN_H	0xec
+
+#endif /* __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H */
-- 
2.34.1

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Krzysztof Kozlowski]

On 11/10/2023 11:05, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@nuvoton.com>
> 
> Add the dt-bindings header for nuvoton ma35d1 pinctrl, that gets shared
> between the pin control driver and pin configuration in the dts.
> 
> Add documentation to describe nuvoton ma35d1 pin control and GPIO.
> 
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> ---
>  .../pinctrl/nuvoton,ma35d1-pinctrl.yaml       | 180 ++++++++++++++++++
>  include/dt-bindings/pinctrl/ma35d1-pinfunc.h  |  38 ++++
>  2 files changed, 218 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
>  create mode 100644 include/dt-bindings/pinctrl/ma35d1-pinfunc.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
> new file mode 100644
> index 000000000000..0ddedbad4b78
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
> @@ -0,0 +1,180 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton MA35D1 pin control and GPIO
> +
> +maintainers:
> +  - Shan-Chun Hung <schung@nuvoton.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - nuvoton,ma35d1-pinctrl
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  nuvoton,sys:
> +    description:
> +      phandle to the syscon node

sys is quite generic. Description explains nothing except duplicating
known information. Drop duplicated info and instead explain to what this
phandle points and how it is going to be used.


> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      maxItems: 1

So just phandle, not phandle-array, unless it is defined like this in
some other binding.

> +
> +  ranges: true
> +
> +allOf:
> +  - $ref: pinctrl.yaml#

allOf: goes after required: block.

> +
> +patternProperties:
> +  "gpio[a-n]@[0-9a-f]+$":

^gpio@[0-9a-f]+$":


> +    type: object
> +    additionalProperties: false
> +    properties:
> +

Drop blank line

> +      gpio-controller: true
> +
> +      '#gpio-cells':
> +        const: 2
> +
> +      reg:
> +        maxItems: 1
> +
> +      clocks:
> +        maxItems: 1
> +
> +      interrupt-controller: true
> +
> +      '#interrupt-cells':
> +        const: 2
> +
> +      interrupts:
> +        description:
> +          The interrupt outputs to sysirq.
> +        maxItems: 1
> +
> +    required:
> +      - reg
> +      - interrupts
> +      - interrupt-controller
> +      - '#interrupt-cells'
> +      - gpio-controller
> +      - '#gpio-cells'

Keep the same order as in list of properties.

> +
> +  "pcfg-[a-z0-9-.]+$":

Why using different naming than other Nuvoton SoCs? You also accept
"foobarpcfg-1", which does not look intentional.


> +    type: object
> +    description:
> +      A pinctrl node should contain at least one subnodes representing the
> +      pinctrl groups available on the machine. Each subnode will list the
> +      pins it needs, and how they should be configured, with regard to muxer
> +      configuration, pullups, drive strength, input enable/disable and input
> +      schmitt.
> +
> +    allOf:
> +      - $ref: pincfg-node.yaml#

missing additional/unevaluatedProperties: false.

> +
> +    properties:
> +      bias-disable: true

Why do you need this and other ones?

> +
> +      bias-pull-down: true
> +
> +      bias-pull-up: true
> +
> +      drive-strength:
> +        minimum: 0

0 mA? Is it really valid? Are you sure you used correct property?


> +        maximum: 7
> +
> +      input-enable: true
> +
> +      input-schmitt-enable: true
> +
> +      power-source:
> +        description:
> +          I/O voltage in millivolt.
> +        enum: [ 1800, 3300 ]

Missing units in property name. power-source also does not really
describe the property.

> +
> +additionalProperties:
> +  type: object
> +  additionalProperties:
> +    type: object

Wait, what? What are you describing here?

> +    properties:
> +      nuvoton,pin:
> +        description:
> +          Each entry consists of 4 parameters and represents the mux and config
> +          setting for one pin.
> +        $ref: /schemas/types.yaml#/definitions/uint32-matrix
> +        minItems: 1
> +        items:
> +          items:
> +            - minimum: 0x80
> +              maximum: 0xec
> +              description:
> +                The pinctrl register offset in syscon registers.
> +            - minimum: 0
> +              maximum: 30
> +              description:
> +                The bit offset in the pinctrl register.
> +            - minimum: 0
> +              maximum: 15
> +              description:
> +                The multi-function pin value.
> +            - description:
> +                The phandle of a node contains the generic pinconfig options
> +                to use as described in pinctrl-bindings.txt.
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/gpio/gpio.h>
> +    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> +    #include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
> +
> +    pinctrl@40040000 {
> +        compatible = "nuvoton,ma35d1-pinctrl";
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        nuvoton,sys = <&sys>;
> +        ranges = <0 0x40040000 0xc00>;
> +
> +        gpioa@40040000 {
> +                reg = <0x0 0x40>;
> +                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +                clocks = <&clk GPA_GATE>;
> +                gpio-controller;
> +                #gpio-cells = <2>;
> +                interrupt-controller;
> +                #interrupt-cells = <2>;
> +        };
> +
> +        pcfg_default: pcfg-default {
> +                slew-rate = <0>;
> +                input-schmitt-disable;
> +                bias-disable;
> +                power-source = <3300>;
> +                drive-strength = <0>;

Really 0 mA?

Why this is so incomplete?

> +        };
> +    };
> +
> +    pinctrl {> +        uart13 {
> +                pinctrl_uart13: uart13grp {

According to your bindings this does not belong here.

> +                        nuvoton,pins =
> +                                <MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
> +                                <MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
> +                };
> +        };
> +    };
> +
> +    serial@407d0000 {

Drop node, not related at all.

> +        compatible = "nuvoton,ma35d1-uart";
> +        reg = <0x407d0000 0x100>;
> +        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clk UART13_GATE>;
> +        pinctrl-0 = <&pinctrl_uart13>;
> +    };
> diff --git a/include/dt-bindings/pinctrl/ma35d1-pinfunc.h b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
> new file mode 100644
> index 000000000000..a2609d466dc9
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h

Filename matching bindings. The same name.

> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Nuvoton Technologies.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
> +#define __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
> +
> +#define MA35_SYS_REG_GPA_L	0x80

Registry addresses are not suitable for bindings. There is also no need
to have REG address in the binding. Drop entire file.

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Jacky Huang]

Dear Krzysztof,

Thank you for the review.


On 2023/10/13 上午 03:41, Krzysztof Kozlowski wrote:
> On 11/10/2023 11:05, Jacky Huang wrote:
>> From: Jacky Huang<ychuang3@nuvoton.com>
>>
>> Add the dt-bindings header for nuvoton ma35d1 pinctrl, that gets shared
>> between the pin control driver and pin configuration in the dts.
>>
>> Add documentation to describe nuvoton ma35d1 pin control and GPIO.
>>
>> Signed-off-by: Jacky Huang<ychuang3@nuvoton.com>
>> ---
>>   .../pinctrl/nuvoton,ma35d1-pinctrl.yaml       | 180 ++++++++++++++++++
>>   include/dt-bindings/pinctrl/ma35d1-pinfunc.h  |  38 ++++
>>   2 files changed, 218 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
>>   create mode 100644 include/dt-bindings/pinctrl/ma35d1-pinfunc.h
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..0ddedbad4b78
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
>> @@ -0,0 +1,180 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
>> +$schema:http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Nuvoton MA35D1 pin control and GPIO
>> +
>> +maintainers:
>> +  - Shan-Chun Hung<schung@nuvoton.com>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - nuvoton,ma35d1-pinctrl
>> +
>> +  '#address-cells':
>> +    const: 1
>> +
>> +  '#size-cells':
>> +    const: 1
>> +
>> +  nuvoton,sys:
>> +    description:
>> +      phandle to the syscon node
> sys is quite generic. Description explains nothing except duplicating
> known information. Drop duplicated info and instead explain to what this
> phandle points and how it is going to be used.
>
>
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      maxItems: 1
> So just phandle, not phandle-array, unless it is defined like this in
> some other binding.

I would like to update this as:

   nuvoton,sys:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
       Help pinctrl driver to access system registers by means of regmap.



>> +
>> +  ranges: true
>> +
>> +allOf:
>> +  - $ref: pinctrl.yaml#
> allOf: goes after required: block.

I will fix it.

>> +
>> +patternProperties:
>> +  "gpio[a-n]@[0-9a-f]+$":
> ^gpio@[0-9a-f]+$":

I will fix this, and also fix the dtsi.

>> +    type: object
>> +    additionalProperties: false
>> +    properties:
>> +
> Drop blank line

I will fix it.

>> +      gpio-controller: true
>> +
>> +      '#gpio-cells':
>> +        const: 2
>> +
>> +      reg:
>> +        maxItems: 1
>> +
>> +      clocks:
>> +        maxItems: 1
>> +
>> +      interrupt-controller: true
>> +
>> +      '#interrupt-cells':
>> +        const: 2
>> +
>> +      interrupts:
>> +        description:
>> +          The interrupt outputs to sysirq.
>> +        maxItems: 1
>> +
>> +    required:
>> +      - reg
>> +      - interrupts
>> +      - interrupt-controller
>> +      - '#interrupt-cells'
>> +      - gpio-controller
>> +      - '#gpio-cells'
> Keep the same order as in list of properties.

I will fix the order.

>> +
>> +  "pcfg-[a-z0-9-.]+$":
> Why using different naming than other Nuvoton SoCs? You also accept
> "foobarpcfg-1", which does not look intentional.
>

I will use '"^pin-[a-z0-9-.]+$" instead.


>> +    type: object
>> +    description:
>> +      A pinctrl node should contain at least one subnodes representing the
>> +      pinctrl groups available on the machine. Each subnode will list the
>> +      pins it needs, and how they should be configured, with regard to muxer
>> +      configuration, pullups, drive strength, input enable/disable and input
>> +      schmitt.
>> +
>> +    allOf:
>> +      - $ref: pincfg-node.yaml#
> missing additional/unevaluatedProperties: false.

I will add unevaluatedProperties: false.

>> +
>> +    properties:
>> +      bias-disable: true
> Why do you need this and other ones?

We expect the pin configuration to select one of ==>
bias-disable;
bias-pull-down;
bias-pull-up;

This is the same as rockchip,pinctrl.yaml and renesas,rzv2m-pinctrl.yaml.

>> +
>> +      bias-pull-down: true
>> +
>> +      bias-pull-up: true
>> +
>> +      drive-strength:
>> +        minimum: 0
> 0 mA? Is it really valid? Are you sure you used correct property?

We treat this value as the value to be written to the control register, 
not as
a current value in mA. I will correct this mistake.

>> +        maximum: 7
>> +
>> +      input-enable: true
>> +
>> +      input-schmitt-enable: true
>> +
>> +      power-source:
>> +        description:
>> +          I/O voltage in millivolt.
>> +        enum: [ 1800, 3300 ]
> Missing units in property name. power-source also does not really
> describe the property.


The output voltage level of GPIO can be configured as 1.8V or 3.3V,
but I cannot find any suitable output properties in 'pincfg-node.yaml.'
I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
'power source' to specify the output voltage.  Should I follow their
approach or define a vendor-specific one?


>> +
>> +additionalProperties:
>> +  type: object
>> +  additionalProperties:
>> +    type: object
> Wait, what? What are you describing here?

I will fix it as:

   "-grp[0-9]$":
     type: object
     description:
       Pinctrl node's client devices use subnodes for desired pin 
configuration.
       Client device subnodes use below standard properties.
     properties:
       nuvoton,pins:
       ....

and fix the example dts also.

>> +    properties:
>> +      nuvoton,pin:
>> +        description:
>> +          Each entry consists of 4 parameters and represents the mux and config
>> +          setting for one pin.
>> +        $ref: /schemas/types.yaml#/definitions/uint32-matrix
>> +        minItems: 1
>> +        items:
>> +          items:
>> +            - minimum: 0x80
>> +              maximum: 0xec
>> +              description:
>> +                The pinctrl register offset in syscon registers.
>> +            - minimum: 0
>> +              maximum: 30
>> +              description:
>> +                The bit offset in the pinctrl register.
>> +            - minimum: 0
>> +              maximum: 15
>> +              description:
>> +                The multi-function pin value.
>> +            - description:
>> +                The phandle of a node contains the generic pinconfig options
>> +                to use as described in pinctrl-bindings.txt.
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/gpio/gpio.h>
>> +    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>> +    #include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
>> +
>> +    pinctrl@40040000 {
>> +        compatible = "nuvoton,ma35d1-pinctrl";
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        nuvoton,sys = <&sys>;
>> +        ranges = <0 0x40040000 0xc00>;
>> +
>> +        gpioa@40040000 {
>> +                reg = <0x0 0x40>;
>> +                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +                clocks = <&clk GPA_GATE>;
>> +                gpio-controller;
>> +                #gpio-cells = <2>;
>> +                interrupt-controller;
>> +                #interrupt-cells = <2>;
>> +        };
>> +
>> +        pcfg_default: pcfg-default {
>> +                slew-rate = <0>;
>> +                input-schmitt-disable;
>> +                bias-disable;
>> +                power-source = <3300>;
>> +                drive-strength = <0>;
> Really 0 mA?
>
> Why this is so incomplete?

We treat this value as the value to be written to the control register, 
not as
a current value in mA. I will correct this mistake.

>> +        };
>> +    };
>> +
>> +    pinctrl {> +        uart13 {
>> +                pinctrl_uart13: uart13grp {
> According to your bindings this does not belong here.

I will fix.

>> +                        nuvoton,pins =
>> +                                <MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
>> +                                <MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
>> +                };
>> +        };
>> +    };
>> +
>> +    serial@407d0000 {
> Drop node, not related at all.

Okay, I will drop this node.

>> +        compatible = "nuvoton,ma35d1-uart";
>> +        reg = <0x407d0000 0x100>;
>> +        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>> +        clocks = <&clk UART13_GATE>;
>> +        pinctrl-0 = <&pinctrl_uart13>;
>> +    };
>> diff --git a/include/dt-bindings/pinctrl/ma35d1-pinfunc.h b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
>> new file mode 100644
>> index 000000000000..a2609d466dc9
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
> Filename matching bindings. The same name.
>
>> @@ -0,0 +1,38 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
>> +/*
>> + * Copyright (C) 2023 Nuvoton Technologies.
>> + */
>> +
>> +#ifndef __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
>> +#define __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
>> +
>> +#define MA35_SYS_REG_GPA_L	0x80
> Registry addresses are not suitable for bindings. There is also no need
> to have REG address in the binding. Drop entire file.
>
> Best regards,
> Krzysztof
>

I will remove 'ma35d1-pinfunc.h' as it will be useless after the 
'nuvoton,pin' definition changed. Best Regards, Jacky Huang

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Krzysztof Kozlowski]

On 16/10/2023 06:32, Jacky Huang wrote:
>>> +  '#size-cells':
>>> +    const: 1
>>> +
>>> +  nuvoton,sys:
>>> +    description:
>>> +      phandle to the syscon node
>> sys is quite generic. Description explains nothing except duplicating
>> known information. Drop duplicated info and instead explain to what this
>> phandle points and how it is going to be used.

Read comments carefully.

>>
>>
>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>> +    items:
>>> +      maxItems: 1
>> So just phandle, not phandle-array, unless it is defined like this in
>> some other binding.
> 
> I would like to update this as:
> 
>    nuvoton,sys:

Nothing improved.

>      $ref: /schemas/types.yaml#/definitions/phandle
>      description:
>        Help pinctrl driver to access system registers by means of regmap.

Driver is not relevant here. Say which part of syscon are necessary for
pinctrl operation.


> 
> 
> 
>>> +
>>> +  ranges: true
>>> +
>>> +allOf:
>>> +  - $ref: pinctrl.yaml#
>> allOf: goes after required: block.
> 
> I will fix it.
> 
>>> +
>>> +patternProperties:
>>> +  "gpio[a-n]@[0-9a-f]+$":
>> ^gpio@[0-9a-f]+$":
> 
> I will fix this, and also fix the dtsi.
> 
>>> +    type: object
>>> +    additionalProperties: false
>>> +    properties:
>>> +
>> Drop blank line
> 
> I will fix it.
> 
>>> +      gpio-controller: true
>>> +
>>> +      '#gpio-cells':
>>> +        const: 2
>>> +
>>> +      reg:
>>> +        maxItems: 1
>>> +
>>> +      clocks:
>>> +        maxItems: 1
>>> +
>>> +      interrupt-controller: true
>>> +
>>> +      '#interrupt-cells':
>>> +        const: 2
>>> +
>>> +      interrupts:
>>> +        description:
>>> +          The interrupt outputs to sysirq.
>>> +        maxItems: 1
>>> +
>>> +    required:
>>> +      - reg
>>> +      - interrupts
>>> +      - interrupt-controller
>>> +      - '#interrupt-cells'
>>> +      - gpio-controller
>>> +      - '#gpio-cells'
>> Keep the same order as in list of properties.
> 
> I will fix the order.
> 
>>> +
>>> +  "pcfg-[a-z0-9-.]+$":
>> Why using different naming than other Nuvoton SoCs? You also accept
>> "foobarpcfg-1", which does not look intentional.
>>
> 
> I will use '"^pin-[a-z0-9-.]+$" instead.

[.] is redundant... What exactly do you want to match?

> 
> 
>>> +    type: object
>>> +    description:
>>> +      A pinctrl node should contain at least one subnodes representing the
>>> +      pinctrl groups available on the machine. Each subnode will list the
>>> +      pins it needs, and how they should be configured, with regard to muxer
>>> +      configuration, pullups, drive strength, input enable/disable and input
>>> +      schmitt.
>>> +
>>> +    allOf:
>>> +      - $ref: pincfg-node.yaml#
>> missing additional/unevaluatedProperties: false.
> 
> I will add unevaluatedProperties: false.
> 
>>> +
>>> +    properties:
>>> +      bias-disable: true
>> Why do you need this and other ones?
> 
> We expect the pin configuration to select one of ==>
> bias-disable;
> bias-pull-down;
> bias-pull-up;
> 
> This is the same as rockchip,pinctrl.yaml and renesas,rzv2m-pinctrl.yaml.

OK, then go with nuvoton approach. List the properties (:true) and use
additionalProperties: false.

> 
>>> +
>>> +      bias-pull-down: true
>>> +
>>> +      bias-pull-up: true
>>> +
>>> +      drive-strength:
>>> +        minimum: 0
>> 0 mA? Is it really valid? Are you sure you used correct property?
> 
> We treat this value as the value to be written to the control register, 
> not as
> a current value in mA. I will correct this mistake.

Instead treat it as mA. Is this possible?

> 
>>> +        maximum: 7
>>> +
>>> +      input-enable: true
>>> +
>>> +      input-schmitt-enable: true
>>> +
>>> +      power-source:
>>> +        description:
>>> +          I/O voltage in millivolt.
>>> +        enum: [ 1800, 3300 ]
>> Missing units in property name. power-source also does not really
>> describe the property.
> 
> 
> The output voltage level of GPIO can be configured as 1.8V or 3.3V,
> but I cannot find any suitable output properties in 'pincfg-node.yaml.'

There is actually power-source, but treated as actual choice of power
supplies.

> I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
> 'power source' to specify the output voltage.  Should I follow their
> approach or define a vendor-specific one?

Maybe Rob or Linus have here some recommendation, but I would suggest to
go either with rtd1319d-pinctrl.yaml approach or add a generic property
to pincfg-node expressed in real units like "io-microvolt".

Rob, Linus, any ideas for generic property replacing register-specific
power-source?


Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Jacky Huang]

Dear Krzysztof,

Thank you for the review.


On 2023/10/17 上午 03:52, Krzysztof Kozlowski wrote:
> On 16/10/2023 06:32, Jacky Huang wrote:
>>>> +  '#size-cells':
>>>> +    const: 1
>>>> +
>>>> +  nuvoton,sys:
>>>> +    description:
>>>> +      phandle to the syscon node
>>> sys is quite generic. Description explains nothing except duplicating
>>> known information. Drop duplicated info and instead explain to what this
>>> phandle points and how it is going to be used.
> Read comments carefully.


I will update the description of 'nuvoton,sys'.

>
>>>
>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>> +    items:
>>>> +      maxItems: 1
>>> So just phandle, not phandle-array, unless it is defined like this in
>>> some other binding.
>> I would like to update this as:
>>
>>     nuvoton,sys:
> Nothing improved.

Here just fix  the 'phandle-array' to 'phandle' and remove 'maxItems'.

>>       $ref: /schemas/types.yaml#/definitions/phandle
>>       description:
>>         Help pinctrl driver to access system registers by means of regmap.
> Driver is not relevant here. Say which part of syscon are necessary for
> pinctrl operation.
>

I will update description as:

   nuvoton,sys:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
       The pin function control registers are located in the system
       control register space. This phandle provides pinctrl the
       ability to access the pin function control registers through
       the use of regmap.


>>
>>
>>>> +
>>>> +  ranges: true
>>>> +
>>>> +allOf:
>>>> +  - $ref: pinctrl.yaml#
>>> allOf: goes after required: block.
>> I will fix it.
>>
>>>> +
>>>> +patternProperties:
>>>> +  "gpio[a-n]@[0-9a-f]+$":
>>> ^gpio@[0-9a-f]+$":
>> I will fix this, and also fix the dtsi.
>>
>>>> +    type: object
>>>> +    additionalProperties: false
>>>> +    properties:
>>>> +
>>> Drop blank line
>> I will fix it.
>>
>>>> +      gpio-controller: true
>>>> +
>>>> +      '#gpio-cells':
>>>> +        const: 2
>>>> +
>>>> +      reg:
>>>> +        maxItems: 1
>>>> +
>>>> +      clocks:
>>>> +        maxItems: 1
>>>> +
>>>> +      interrupt-controller: true
>>>> +
>>>> +      '#interrupt-cells':
>>>> +        const: 2
>>>> +
>>>> +      interrupts:
>>>> +        description:
>>>> +          The interrupt outputs to sysirq.
>>>> +        maxItems: 1
>>>> +
>>>> +    required:
>>>> +      - reg
>>>> +      - interrupts
>>>> +      - interrupt-controller
>>>> +      - '#interrupt-cells'
>>>> +      - gpio-controller
>>>> +      - '#gpio-cells'
>>> Keep the same order as in list of properties.
>> I will fix the order.
>>
>>>> +
>>>> +  "pcfg-[a-z0-9-.]+$":
>>> Why using different naming than other Nuvoton SoCs? You also accept
>>> "foobarpcfg-1", which does not look intentional.
>>>
>> I will use '"^pin-[a-z0-9-.]+$" instead.
> [.] is redundant... What exactly do you want to match?

I want to match the name like "-1.8v" or "-3.3v".
However, this should be specified in the property, so I will drop the "-.".


>>
>>>> +    type: object
>>>> +    description:
>>>> +      A pinctrl node should contain at least one subnodes representing the
>>>> +      pinctrl groups available on the machine. Each subnode will list the
>>>> +      pins it needs, and how they should be configured, with regard to muxer
>>>> +      configuration, pullups, drive strength, input enable/disable and input
>>>> +      schmitt.
>>>> +
>>>> +    allOf:
>>>> +      - $ref: pincfg-node.yaml#
>>> missing additional/unevaluatedProperties: false.
>> I will add unevaluatedProperties: false.
>>
>>>> +
>>>> +    properties:
>>>> +      bias-disable: true
>>> Why do you need this and other ones?
>> We expect the pin configuration to select one of ==>
>> bias-disable;
>> bias-pull-down;
>> bias-pull-up;
>>
>> This is the same as rockchip,pinctrl.yaml and renesas,rzv2m-pinctrl.yaml.
> OK, then go with nuvoton approach. List the properties (:true) and use
> additionalProperties: false.

I got it.

>>>> +
>>>> +      bias-pull-down: true
>>>> +
>>>> +      bias-pull-up: true
>>>> +
>>>> +      drive-strength:
>>>> +        minimum: 0
>>> 0 mA? Is it really valid? Are you sure you used correct property?
>> We treat this value as the value to be written to the control register,
>> not as
>> a current value in mA. I will correct this mistake.
> Instead treat it as mA. Is this possible?

I will update it as:

       drive-strength-microamp:
         oneOf:
           - enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ]
             description: 1.8V I/O driving strength
           - enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 
82000 ]
             description: 3.3V I/O driving strength

And use a lookup table in the pinctrl driver to translate it into 
register value.


>>>> +        maximum: 7
>>>> +
>>>> +      input-enable: true
>>>> +
>>>> +      input-schmitt-enable: true
>>>> +
>>>> +      power-source:
>>>> +        description:
>>>> +          I/O voltage in millivolt.
>>>> +        enum: [ 1800, 3300 ]
>>> Missing units in property name. power-source also does not really
>>> describe the property.
>>
>> The output voltage level of GPIO can be configured as 1.8V or 3.3V,
>> but I cannot find any suitable output properties in 'pincfg-node.yaml.'
> There is actually power-source, but treated as actual choice of power
> supplies.
>
>> I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
>> 'power source' to specify the output voltage.  Should I follow their
>> approach or define a vendor-specific one?
> Maybe Rob or Linus have here some recommendation, but I would suggest to
> go either with rtd1319d-pinctrl.yaml approach or add a generic property
> to pincfg-node expressed in real units like "io-microvolt".

OK, I will update it as:

       power-source:
         description: |
           Valid arguments are described as below:
           0: power supply of 1.8V
           1: power supply of 3.3V
         enum: [0, 1]


> Rob, Linus, any ideas for generic property replacing register-specific
> power-source?
>
>
> Best regards,
> Krzysztof
>

Best Regards,
Jacky Huang

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Krzysztof Kozlowski]

On 18/10/2023 05:26, Jacky Huang wrote:
> Dear Krzysztof,
> 
> Thank you for the review.
> 
> 
> On 2023/10/17 上午 03:52, Krzysztof Kozlowski wrote:
>> On 16/10/2023 06:32, Jacky Huang wrote:
>>>>> +  '#size-cells':
>>>>> +    const: 1
>>>>> +
>>>>> +  nuvoton,sys:
>>>>> +    description:
>>>>> +      phandle to the syscon node
>>>> sys is quite generic. Description explains nothing except duplicating
>>>> known information. Drop duplicated info and instead explain to what this
>>>> phandle points and how it is going to be used.
>> Read comments carefully.
> 
> 
> I will update the description of 'nuvoton,sys'.

What is the full name of destination block?

> 
>>
>>>>
>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>> +    items:
>>>>> +      maxItems: 1
>>>> So just phandle, not phandle-array, unless it is defined like this in
>>>> some other binding.
>>> I would like to update this as:
>>>
>>>     nuvoton,sys:
>> Nothing improved.
> 
> Here just fix  the 'phandle-array' to 'phandle' and remove 'maxItems'.
> 
>>>       $ref: /schemas/types.yaml#/definitions/phandle
>>>       description:
>>>         Help pinctrl driver to access system registers by means of regmap.
>> Driver is not relevant here. Say which part of syscon are necessary for
>> pinctrl operation.
>>
> 
> I will update description as:
> 
>    nuvoton,sys:
>      $ref: /schemas/types.yaml#/definitions/phandle
>      description:
>        The pin function control registers are located in the system
>        control register space. This phandle provides pinctrl the
>        ability to access the pin function control registers through
>        the use of regmap.

regmap is unrelated to the bindings.

> 
>>>>> +        maximum: 7
>>>>> +
>>>>> +      input-enable: true
>>>>> +
>>>>> +      input-schmitt-enable: true
>>>>> +
>>>>> +      power-source:
>>>>> +        description:
>>>>> +          I/O voltage in millivolt.
>>>>> +        enum: [ 1800, 3300 ]
>>>> Missing units in property name. power-source also does not really
>>>> describe the property.
>>>
>>> The output voltage level of GPIO can be configured as 1.8V or 3.3V,
>>> but I cannot find any suitable output properties in 'pincfg-node.yaml.'
>> There is actually power-source, but treated as actual choice of power
>> supplies.
>>
>>> I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
>>> 'power source' to specify the output voltage.  Should I follow their
>>> approach or define a vendor-specific one?
>> Maybe Rob or Linus have here some recommendation, but I would suggest to
>> go either with rtd1319d-pinctrl.yaml approach or add a generic property
>> to pincfg-node expressed in real units like "io-microvolt".
> 
> OK, I will update it as:
> 
>        power-source:
>          description: |
>            Valid arguments are described as below:
>            0: power supply of 1.8V
>            1: power supply of 3.3V
>          enum: [0, 1]
> 
> 
>> Rob, Linus, any ideas for generic property replacing register-specific
>> power-source?

I proposed io-microvolt

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Jacky Huang]

Dear Krzysztof,

Thank you for the review.


On 2023/10/18 下午 01:58, Krzysztof Kozlowski wrote:
> On 18/10/2023 05:26, Jacky Huang wrote:
>> Dear Krzysztof,
>>
>> Thank you for the review.
>>
>>
>> On 2023/10/17 上午 03:52, Krzysztof Kozlowski wrote:
>>> On 16/10/2023 06:32, Jacky Huang wrote:
>>>>>> +  '#size-cells':
>>>>>> +    const: 1
>>>>>> +
>>>>>> +  nuvoton,sys:
>>>>>> +    description:
>>>>>> +      phandle to the syscon node
>>>>> sys is quite generic. Description explains nothing except duplicating
>>>>> known information. Drop duplicated info and instead explain to what this
>>>>> phandle points and how it is going to be used.
>>> Read comments carefully.
>>
>> I will update the description of 'nuvoton,sys'.
> What is the full name of destination block?


The full name is 'system-management'. From:

         sys: system-management@40460000 {
             compatible = "nuvoton,ma35d1-reset", "syscon";
             reg = <0x0 0x40460000 0x0 0x200>;
             #reset-cells = <1>;
         };


>>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>>> +    items:
>>>>>> +      maxItems: 1
>>>>> So just phandle, not phandle-array, unless it is defined like this in
>>>>> some other binding.
>>>> I would like to update this as:
>>>>
>>>>      nuvoton,sys:
>>> Nothing improved.
>> Here just fix  the 'phandle-array' to 'phandle' and remove 'maxItems'.
>>
>>>>        $ref: /schemas/types.yaml#/definitions/phandle
>>>>        description:
>>>>          Help pinctrl driver to access system registers by means of regmap.
>>> Driver is not relevant here. Say which part of syscon are necessary for
>>> pinctrl operation.
>>>
>> I will update description as:
>>
>>     nuvoton,sys:
>>       $ref: /schemas/types.yaml#/definitions/phandle
>>       description:
>>         The pin function control registers are located in the system
>>         control register space. This phandle provides pinctrl the
>>         ability to access the pin function control registers through
>>         the use of regmap.
> regmap is unrelated to the bindings.

So, I will just update the description as:

phandle of the system-management node.


>>>>>> +        maximum: 7
>>>>>> +
>>>>>> +      input-enable: true
>>>>>> +
>>>>>> +      input-schmitt-enable: true
>>>>>> +
>>>>>> +      power-source:
>>>>>> +        description:
>>>>>> +          I/O voltage in millivolt.
>>>>>> +        enum: [ 1800, 3300 ]
>>>>> Missing units in property name. power-source also does not really
>>>>> describe the property.
>>>> The output voltage level of GPIO can be configured as 1.8V or 3.3V,
>>>> but I cannot find any suitable output properties in 'pincfg-node.yaml.'
>>> There is actually power-source, but treated as actual choice of power
>>> supplies.
>>>
>>>> I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
>>>> 'power source' to specify the output voltage.  Should I follow their
>>>> approach or define a vendor-specific one?
>>> Maybe Rob or Linus have here some recommendation, but I would suggest to
>>> go either with rtd1319d-pinctrl.yaml approach or add a generic property
>>> to pincfg-node expressed in real units like "io-microvolt".
>> OK, I will update it as:
>>
>>         power-source:
>>           description: |
>>             Valid arguments are described as below:
>>             0: power supply of 1.8V
>>             1: power supply of 3.3V
>>           enum: [0, 1]
>>
>>
>>> Rob, Linus, any ideas for generic property replacing register-specific
>>> power-source?
> I proposed io-microvolt
>
> Best regards,
> Krzysztof
>

I will use 'io-microvolt' once it is available.



Best Regards,
Jacky Huang

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Linus Walleij]

On Mon, Oct 16, 2023 at 9:52 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:

> > I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
> > 'power source' to specify the output voltage.  Should I follow their
> > approach or define a vendor-specific one?
>
> Maybe Rob or Linus have here some recommendation, but I would suggest to
> go either with rtd1319d-pinctrl.yaml approach or add a generic property
> to pincfg-node expressed in real units like "io-microvolt".
>
> Rob, Linus, any ideas for generic property replacing register-specific
> power-source?

The existing power-source is generally used to select between (usually
two) different chip-internal power rails, such as 1.8V and 3.3V.
The format is a driver-specific enumerator.

We *could* just patch the documentation for power-source to
say that microvolts is the preferred format but legacy users may
be using a custom enumerator.

io-microvolt seems like a more long-term viable option if a wider
range of voltages are to be supported so I'm happy with that if the
DT folks think it's nicer. However notice that the power-source
property is already being hard-coded into things such as SCMI
and ACPI so it's not like it will ever be replaced by io-microvolt
and phased out as far as Linux is concerned. Not the next 50
years at least.

Yours,
Linus Walleij

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Krzysztof Kozlowski]

On 18/10/2023 10:18, Linus Walleij wrote:
> On Mon, Oct 16, 2023 at 9:52 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> 
>>> I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
>>> 'power source' to specify the output voltage.  Should I follow their
>>> approach or define a vendor-specific one?
>>
>> Maybe Rob or Linus have here some recommendation, but I would suggest to
>> go either with rtd1319d-pinctrl.yaml approach or add a generic property
>> to pincfg-node expressed in real units like "io-microvolt".
>>
>> Rob, Linus, any ideas for generic property replacing register-specific
>> power-source?
> 
> The existing power-source is generally used to select between (usually
> two) different chip-internal power rails, such as 1.8V and 3.3V.
> The format is a driver-specific enumerator.
> 
> We *could* just patch the documentation for power-source to
> say that microvolts is the preferred format but legacy users may
> be using a custom enumerator.
> 
> io-microvolt seems like a more long-term viable option if a wider
> range of voltages are to be supported so I'm happy with that if the
> DT folks think it's nicer. However notice that the power-source
> property is already being hard-coded into things such as SCMI
> and ACPI so it's not like it will ever be replaced by io-microvolt
> and phased out as far as Linux is concerned. Not the next 50
> years at least.

This I understand.

I think It is better in general if generic properties use units (e.g.
drive-strength-microamp, output-impedance-ohms), so it could be here
"io-microvolt". At least for the new bindings.

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control

[Linus Walleij]

On Wed, Oct 18, 2023 at 11:53 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 18/10/2023 10:18, Linus Walleij wrote:
> > On Mon, Oct 16, 2023 at 9:52 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >
> >>> I noticed that 'xlnx,zynq-pinctrl.yaml' and 'xlnx,zynq-pinctrl.yaml' use
> >>> 'power source' to specify the output voltage.  Should I follow their
> >>> approach or define a vendor-specific one?
> >>
> >> Maybe Rob or Linus have here some recommendation, but I would suggest to
> >> go either with rtd1319d-pinctrl.yaml approach or add a generic property
> >> to pincfg-node expressed in real units like "io-microvolt".
> >>
> >> Rob, Linus, any ideas for generic property replacing register-specific
> >> power-source?
> >
> > The existing power-source is generally used to select between (usually
> > two) different chip-internal power rails, such as 1.8V and 3.3V.
> > The format is a driver-specific enumerator.
> >
> > We *could* just patch the documentation for power-source to
> > say that microvolts is the preferred format but legacy users may
> > be using a custom enumerator.
> >
> > io-microvolt seems like a more long-term viable option if a wider
> > range of voltages are to be supported so I'm happy with that if the
> > DT folks think it's nicer. However notice that the power-source
> > property is already being hard-coded into things such as SCMI
> > and ACPI so it's not like it will ever be replaced by io-microvolt
> > and phased out as far as Linux is concerned. Not the next 50
> > years at least.
>
> This I understand.
>
> I think It is better in general if generic properties use units (e.g.
> drive-strength-microamp, output-impedance-ohms), so it could be here
> "io-microvolt". At least for the new bindings.

I agree. Even io-voltage-microvolt perhaps.

Yours,
Linus Walleij

[PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1

[Jacky Huang]

From: Jacky Huang <ychuang3@nuvoton.com>

Add 'pinctrl' node and 'gpioa' ~ 'gpion' nodes to the dtsi of ma35d1
SoC and describe default pin configurations.

Enable all UART nodes presented on som and iot boards, and add pinctrl
function settings to these nodes.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 .../boot/dts/nuvoton/ma35d1-iot-512m.dts      |  83 ++++++++-
 .../boot/dts/nuvoton/ma35d1-som-256m.dts      |  86 ++++++++-
 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi       | 175 +++++++++++++++++-
 3 files changed, 335 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
index b89e2be6abae..ff0d2bf8f5bf 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
@@ -14,6 +14,10 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		serial10 = &uart10;
+		serial12 = &uart12;
+		serial13 = &uart13;
+		serial14 = &uart14;
 	};
 
 	chosen {
@@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
 	};
 };
 
-&uart0 {
-	status = "okay";
-};
-
 &clk {
 	assigned-clocks = <&clk CAPLL>,
 			  <&clk DDRPLL>,
@@ -54,3 +54,78 @@ &clk {
 			   "integer",
 			   "integer";
 };
+
+&pinctrl {
+	uart0 {
+		pinctrl_uart0: uart0grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
+				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
+		};
+	};
+
+	uart10 {
+		pinctrl_uart10: uart10grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPH_L 16 2 &pcfg_default>,
+				<MA35_SYS_REG_GPH_L 20 2 &pcfg_default>,
+				<MA35_SYS_REG_GPH_L 24 2 &pcfg_default>,
+				<MA35_SYS_REG_GPH_L 28 2 &pcfg_default>;
+		};
+	};
+
+	uart12 {
+		pinctrl_uart12: uart12grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPC_H 20 2 &pcfg_default>,
+				<MA35_SYS_REG_GPC_H 24 2 &pcfg_default>,
+				<MA35_SYS_REG_GPC_H 28 2 &pcfg_default>;
+		};
+	};
+
+	uart13 {
+		pinctrl_uart13: uart13grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPH_H 16 3 &pcfg_default>,
+				<MA35_SYS_REG_GPH_H 20 3 &pcfg_default>;
+		};
+	};
+
+	uart14 {
+		pinctrl_uart14: uart14grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
+				<MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
+	status = "okay";
+};
+
+&uart10 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart10>;
+	status = "okay";
+};
+
+&uart12 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart12>;
+	status = "okay";
+};
+
+&uart13 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart13>;
+	status = "okay";
+};
+
+&uart14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart14>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
index a1ebddecb7f8..c8c26f37116b 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
@@ -14,6 +14,10 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		serial11 = &uart11;
+		serial12 = &uart12;
+		serial14 = &uart14;
+		serial16 = &uart16;
 	};
 
 	chosen {
@@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
 	};
 };
 
-&uart0 {
-	status = "okay";
-};
-
 &clk {
 	assigned-clocks = <&clk CAPLL>,
 			  <&clk DDRPLL>,
@@ -54,3 +54,81 @@ &clk {
 			   "integer",
 			   "integer";
 };
+
+&pinctrl {
+	uart0 {
+		pinctrl_uart0: uart0grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
+				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
+		};
+	};
+
+	uart11 {
+		pinctrl_uart11: uart11grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPL_L 0 2 &pcfg_default>,
+				<MA35_SYS_REG_GPL_L 4 2 &pcfg_default>,
+				<MA35_SYS_REG_GPL_L 8 2 &pcfg_default>,
+				<MA35_SYS_REG_GPL_L 12 2 &pcfg_default>;
+		};
+	};
+
+	uart12 {
+		pinctrl_uart12: uart12grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPI_L 4 2 &pcfg_default>,
+				<MA35_SYS_REG_GPI_L 8 2 &pcfg_default>,
+				<MA35_SYS_REG_GPI_L 12 2 &pcfg_default>;
+		};
+	};
+
+	uart14 {
+		pinctrl_uart14: uart14grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPI_L 20 2 &pcfg_default>,
+				<MA35_SYS_REG_GPI_L 24 2 &pcfg_default>,
+				<MA35_SYS_REG_GPI_L 28 2 &pcfg_default>;
+		};
+	};
+
+	uart16 {
+		pinctrl_uart16: uart16grp {
+			nuvoton,pins =
+				<MA35_SYS_REG_GPK_L 0 2 &pcfg_default>,
+				<MA35_SYS_REG_GPK_L 4 2 &pcfg_default>,
+				<MA35_SYS_REG_GPK_L 8 2 &pcfg_default>,
+				<MA35_SYS_REG_GPK_L 12 2 &pcfg_default>;
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
+	status = "okay";
+};
+
+&uart11 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart11>;
+	status = "okay";
+};
+
+&uart12 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart12>;
+	status = "okay";
+};
+
+&uart14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart14>;
+	status = "okay";
+};
+
+&uart16 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart16>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
index 781cdae566a0..85431a074ab2 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
+#include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
 
 / {
 	compatible = "nuvoton,ma35d1";
@@ -83,7 +84,7 @@ soc {
 		ranges;
 
 		sys: system-management@40460000 {
-			compatible = "nuvoton,ma35d1-reset";
+			compatible = "nuvoton,ma35d1-reset", "syscon";
 			reg = <0x0 0x40460000 0x0 0x200>;
 			#reset-cells = <1>;
 		};
@@ -95,6 +96,178 @@ clk: clock-controller@40460200 {
 			clocks = <&clk_hxt>;
 		};
 
+		pinctrl: pinctrl@40040000 {
+			compatible = "nuvoton,ma35d1-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			nuvoton,sys = <&sys>;
+			ranges = <0x0 0x0 0x40040000 0xc00>;
+
+			gpioa: gpioa@40040000 {
+				reg = <0x0 0x40>;
+				interrupts = <GIC_SPI  14 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPA_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiob: gpiob@40040040 {
+				reg = <0x40 0x40>;
+				interrupts = <GIC_SPI  15 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPB_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioc: gpioc@40040080 {
+				reg = <0x80 0x40>;
+				interrupts = <GIC_SPI  16 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPC_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiod: gpiod@400400c0 {
+				reg = <0xc0 0x40>;
+				interrupts = <GIC_SPI  17 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPD_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioe: gpioe@40040100 {
+				reg = <0x100 0x40>;
+				interrupts = <GIC_SPI  73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPE_GATE>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiof: gpiof@40040140 {
+				reg = <0x140 0x40>;
+				interrupts = <GIC_SPI  74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPF_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiog: gpiog@40040180 {
+				reg = <0x180 0x40>;
+				interrupts = <GIC_SPI  75 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPG_GATE>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioh: gpioh@400401c0 {
+				reg = <0x1c0 0x40>;
+				interrupts = <GIC_SPI  76 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPH_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioi: gpioi@40040200 {
+				reg = <0x200 0x40>;
+				interrupts = <GIC_SPI  77 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPI_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioj: gpioj@40040240 {
+				reg = <0x240 0x40>;
+				interrupts = <GIC_SPI  78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPJ_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiok: gpiok@40040280 {
+				reg = <0x280 0x40>;
+				interrupts = <GIC_SPI  102 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPK_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiol: gpiol@400402c0 {
+				reg = <0x2c0 0x40>;
+				interrupts = <GIC_SPI  103 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPL_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiom: gpiom@40040300 {
+				reg = <0x300 0x40>;
+				interrupts = <GIC_SPI  104 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPM_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpion: gpion@40040340 {
+				reg = <0x340 0x40>;
+				interrupts = <GIC_SPI  105 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk GPN_GATE>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			pcfg_default: pcfg-default {
+				slew-rate = <0>;
+				input-schmitt-disable;
+				bias-disable;
+				power-source = <3300>;
+				drive-strength = <0>;
+			};
+
+			pcfg_emac_3_3v: pcfg-emac-3.3v {
+				slew-rate = <0>;
+				input-schmitt-enable;
+				bias-disable;
+				power-source = <3300>;
+				drive-strength = <1>;
+			};
+
+			pcfg_emac_1_8v: pcfg-emac-1.8v {
+				slew-rate = <0>;
+				input-schmitt-enable;
+				bias-disable;
+				power-source = <1800>;
+				drive-strength = <1>;
+			};
+		};
+
 		uart0: serial@40700000 {
 			compatible = "nuvoton,ma35d1-uart";
 			reg = <0x0 0x40700000 0x0 0x100>;
-- 
2.34.1

Re: [PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1

[Krzysztof Kozlowski]

On 11/10/2023 11:05, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@nuvoton.com>
> 
> Add 'pinctrl' node and 'gpioa' ~ 'gpion' nodes to the dtsi of ma35d1
> SoC and describe default pin configurations.
> 
> Enable all UART nodes presented on som and iot boards, and add pinctrl
> function settings to these nodes.
> 
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> ---
>  .../boot/dts/nuvoton/ma35d1-iot-512m.dts      |  83 ++++++++-
>  .../boot/dts/nuvoton/ma35d1-som-256m.dts      |  86 ++++++++-
>  arch/arm64/boot/dts/nuvoton/ma35d1.dtsi       | 175 +++++++++++++++++-
>  3 files changed, 335 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> index b89e2be6abae..ff0d2bf8f5bf 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> @@ -14,6 +14,10 @@ / {
>  
>  	aliases {
>  		serial0 = &uart0;
> +		serial10 = &uart10;
> +		serial12 = &uart12;
> +		serial13 = &uart13;
> +		serial14 = &uart14;
>  	};
>  
>  	chosen {
> @@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
>  	};
>  };
>  
> -&uart0 {
> -	status = "okay";
> -};
> -
>  &clk {
>  	assigned-clocks = <&clk CAPLL>,
>  			  <&clk DDRPLL>,
> @@ -54,3 +54,78 @@ &clk {
>  			   "integer",
>  			   "integer";
>  };
> +
> +&pinctrl {
> +	uart0 {
> +		pinctrl_uart0: uart0grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
> +		};
> +	};
> +
> +	uart10 {
> +		pinctrl_uart10: uart10grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPH_L 16 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPH_L 20 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPH_L 24 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPH_L 28 2 &pcfg_default>;
> +		};
> +	};
> +
> +	uart12 {
> +		pinctrl_uart12: uart12grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPC_H 20 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPC_H 24 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPC_H 28 2 &pcfg_default>;
> +		};
> +	};
> +
> +	uart13 {
> +		pinctrl_uart13: uart13grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPH_H 16 3 &pcfg_default>,
> +				<MA35_SYS_REG_GPH_H 20 3 &pcfg_default>;
> +		};
> +	};
> +
> +	uart14 {
> +		pinctrl_uart14: uart14grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
> +		};
> +	};
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart0>;
> +	status = "okay";
> +};
> +
> +&uart10 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart10>;
> +	status = "okay";
> +};
> +
> +&uart12 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart12>;
> +	status = "okay";
> +};
> +
> +&uart13 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart13>;
> +	status = "okay";
> +};
> +
> +&uart14 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart14>;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> index a1ebddecb7f8..c8c26f37116b 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> @@ -14,6 +14,10 @@ / {
>  
>  	aliases {
>  		serial0 = &uart0;
> +		serial11 = &uart11;
> +		serial12 = &uart12;
> +		serial14 = &uart14;
> +		serial16 = &uart16;
>  	};
>  
>  	chosen {
> @@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
>  	};
>  };
>  
> -&uart0 {
> -	status = "okay";
> -};
> -
>  &clk {
>  	assigned-clocks = <&clk CAPLL>,
>  			  <&clk DDRPLL>,
> @@ -54,3 +54,81 @@ &clk {
>  			   "integer",
>  			   "integer";
>  };
> +
> +&pinctrl {
> +	uart0 {
> +		pinctrl_uart0: uart0grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;

This does not look like generic pinctrl bindings. Looks
over-complicated. From where did you get it? Which recent bindings and
drivers where used as an example? Register addresses should be in the
driver. Bit offsets as well. "multi-pin-function-value" confuses me. All
this is not really suitable for DTS.

> +		};
> +	};
> +
> +	uart11 {
> +		pinctrl_uart11: uart11grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPL_L 0 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPL_L 4 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPL_L 8 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPL_L 12 2 &pcfg_default>;
> +		};
> +	};
> +
> +	uart12 {
> +		pinctrl_uart12: uart12grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPI_L 4 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPI_L 8 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPI_L 12 2 &pcfg_default>;
> +		};
> +	};
> +
> +	uart14 {
> +		pinctrl_uart14: uart14grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPI_L 20 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPI_L 24 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPI_L 28 2 &pcfg_default>;
> +		};
> +	};
> +
> +	uart16 {
> +		pinctrl_uart16: uart16grp {
> +			nuvoton,pins =
> +				<MA35_SYS_REG_GPK_L 0 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPK_L 4 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPK_L 8 2 &pcfg_default>,
> +				<MA35_SYS_REG_GPK_L 12 2 &pcfg_default>;
> +		};
> +	};
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart0>;
> +	status = "okay";
> +};
> +
> +&uart11 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart11>;
> +	status = "okay";
> +};
> +
> +&uart12 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart12>;
> +	status = "okay";
> +};
> +
> +&uart14 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart14>;
> +	status = "okay";
> +};
> +
> +&uart16 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart16>;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> index 781cdae566a0..85431a074ab2 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>  #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
> +#include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
>  
>  / {
>  	compatible = "nuvoton,ma35d1";
> @@ -83,7 +84,7 @@ soc {
>  		ranges;
>  
>  		sys: system-management@40460000 {
> -			compatible = "nuvoton,ma35d1-reset";
> +			compatible = "nuvoton,ma35d1-reset", "syscon";
>  			reg = <0x0 0x40460000 0x0 0x200>;
>  			#reset-cells = <1>;
>  		};
> @@ -95,6 +96,178 @@ clk: clock-controller@40460200 {
>  			clocks = <&clk_hxt>;
>  		};
>  
> +		pinctrl: pinctrl@40040000 {
> +			compatible = "nuvoton,ma35d1-pinctrl";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			nuvoton,sys = <&sys>;
> +			ranges = <0x0 0x0 0x40040000 0xc00>;
> +
> +			gpioa: gpioa@40040000 {
> +				reg = <0x0 0x40>;
> +				interrupts = <GIC_SPI  14 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPA_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiob: gpiob@40040040 {
> +				reg = <0x40 0x40>;
> +				interrupts = <GIC_SPI  15 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPB_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioc: gpioc@40040080 {
> +				reg = <0x80 0x40>;
> +				interrupts = <GIC_SPI  16 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPC_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiod: gpiod@400400c0 {
> +				reg = <0xc0 0x40>;
> +				interrupts = <GIC_SPI  17 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPD_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioe: gpioe@40040100 {
> +				reg = <0x100 0x40>;
> +				interrupts = <GIC_SPI  73 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPE_GATE>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiof: gpiof@40040140 {
> +				reg = <0x140 0x40>;
> +				interrupts = <GIC_SPI  74 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPF_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiog: gpiog@40040180 {
> +				reg = <0x180 0x40>;
> +				interrupts = <GIC_SPI  75 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPG_GATE>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioh: gpioh@400401c0 {
> +				reg = <0x1c0 0x40>;
> +				interrupts = <GIC_SPI  76 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPH_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioi: gpioi@40040200 {
> +				reg = <0x200 0x40>;
> +				interrupts = <GIC_SPI  77 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPI_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioj: gpioj@40040240 {
> +				reg = <0x240 0x40>;
> +				interrupts = <GIC_SPI  78 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPJ_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiok: gpiok@40040280 {
> +				reg = <0x280 0x40>;
> +				interrupts = <GIC_SPI  102 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPK_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiol: gpiol@400402c0 {
> +				reg = <0x2c0 0x40>;
> +				interrupts = <GIC_SPI  103 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPL_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiom: gpiom@40040300 {
> +				reg = <0x300 0x40>;
> +				interrupts = <GIC_SPI  104 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPM_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpion: gpion@40040340 {
> +				reg = <0x340 0x40>;
> +				interrupts = <GIC_SPI  105 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk GPN_GATE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			pcfg_default: pcfg-default {
> +				slew-rate = <0>;
> +				input-schmitt-disable;
> +				bias-disable;
> +				power-source = <3300>;
> +				drive-strength = <0>;
> +			};
> +
> +			pcfg_emac_3_3v: pcfg-emac-3.3v {

Drop, unused.

> +				slew-rate = <0>;
> +				input-schmitt-enable;
> +				bias-disable;
> +				power-source = <3300>;
> +				drive-strength = <1>;
> +			};
> +
> +			pcfg_emac_1_8v: pcfg-emac-1.8v {

Drop, unused.

> +				slew-rate = <0>;
> +				input-schmitt-enable;
> +				bias-disable;
> +				power-source = <1800>;
> +				drive-strength = <1>;
> +			};
> +		};
> +
>  		uart0: serial@40700000 {
>  			compatible = "nuvoton,ma35d1-uart";
>  			reg = <0x0 0x40700000 0x0 0x100>;

Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1

[Jacky Huang]

Dear Krzysztof,


Thank you for the review.


On 2023/10/13 上午 03:46, Krzysztof Kozlowski wrote:
> On 11/10/2023 11:05, Jacky Huang wrote:
>> From: Jacky Huang <ychuang3@nuvoton.com>
>>
>> Add 'pinctrl' node and 'gpioa' ~ 'gpion' nodes to the dtsi of ma35d1
>> SoC and describe default pin configurations.
>>
>> Enable all UART nodes presented on som and iot boards, and add pinctrl
>> function settings to these nodes.
>>
>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>> ---
>>   .../boot/dts/nuvoton/ma35d1-iot-512m.dts      |  83 ++++++++-
>>   .../boot/dts/nuvoton/ma35d1-som-256m.dts      |  86 ++++++++-
>>   arch/arm64/boot/dts/nuvoton/ma35d1.dtsi       | 175 +++++++++++++++++-
>>   3 files changed, 335 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
>> index b89e2be6abae..ff0d2bf8f5bf 100644
>> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
>> @@ -14,6 +14,10 @@ / {
>>   
>>   	aliases {
>>   		serial0 = &uart0;
>> +		serial10 = &uart10;
>> +		serial12 = &uart12;
>> +		serial13 = &uart13;
>> +		serial14 = &uart14;
>>   	};
>>   
>>   	chosen {
>> @@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
>>   	};
>>   };
>>   
>> -&uart0 {
>> -	status = "okay";
>> -};
>> -
>>   &clk {
>>   	assigned-clocks = <&clk CAPLL>,
>>   			  <&clk DDRPLL>,
>> @@ -54,3 +54,78 @@ &clk {
>>   			   "integer",
>>   			   "integer";
>>   };
>> +
>> +&pinctrl {
>> +	uart0 {
>> +		pinctrl_uart0: uart0grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
>> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart10 {
>> +		pinctrl_uart10: uart10grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPH_L 16 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPH_L 20 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPH_L 24 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPH_L 28 2 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart12 {
>> +		pinctrl_uart12: uart12grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPC_H 20 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPC_H 24 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPC_H 28 2 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart13 {
>> +		pinctrl_uart13: uart13grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPH_H 16 3 &pcfg_default>,
>> +				<MA35_SYS_REG_GPH_H 20 3 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart14 {
>> +		pinctrl_uart14: uart14grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
>> +		};
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart0>;
>> +	status = "okay";
>> +};
>> +
>> +&uart10 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart10>;
>> +	status = "okay";
>> +};
>> +
>> +&uart12 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart12>;
>> +	status = "okay";
>> +};
>> +
>> +&uart13 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart13>;
>> +	status = "okay";
>> +};
>> +
>> +&uart14 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart14>;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
>> index a1ebddecb7f8..c8c26f37116b 100644
>> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
>> @@ -14,6 +14,10 @@ / {
>>   
>>   	aliases {
>>   		serial0 = &uart0;
>> +		serial11 = &uart11;
>> +		serial12 = &uart12;
>> +		serial14 = &uart14;
>> +		serial16 = &uart16;
>>   	};
>>   
>>   	chosen {
>> @@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
>>   	};
>>   };
>>   
>> -&uart0 {
>> -	status = "okay";
>> -};
>> -
>>   &clk {
>>   	assigned-clocks = <&clk CAPLL>,
>>   			  <&clk DDRPLL>,
>> @@ -54,3 +54,81 @@ &clk {
>>   			   "integer",
>>   			   "integer";
>>   };
>> +
>> +&pinctrl {
>> +	uart0 {
>> +		pinctrl_uart0: uart0grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
>> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
> This does not look like generic pinctrl bindings. Looks
> over-complicated. From where did you get it? Which recent bindings and
> drivers where used as an example? Register addresses should be in the
> driver. Bit offsets as well. "multi-pin-function-value" confuses me. All
> this is not really suitable for DTS.

Okay, I will update the first and second items to 'pin bank' and 'pin 
bank index,
just as others have done, and leave the driver to handle the conversion into
registers and offsets.

The term "multi-pin-function-value" is used to specify the device function.
I will use the name "device function" instead of "multi-pin-function-value.

>> +		};
>> +	};
>> +
>> +	uart11 {
>> +		pinctrl_uart11: uart11grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPL_L 0 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPL_L 4 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPL_L 8 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPL_L 12 2 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart12 {
>> +		pinctrl_uart12: uart12grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPI_L 4 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPI_L 8 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPI_L 12 2 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart14 {
>> +		pinctrl_uart14: uart14grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPI_L 20 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPI_L 24 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPI_L 28 2 &pcfg_default>;
>> +		};
>> +	};
>> +
>> +	uart16 {
>> +		pinctrl_uart16: uart16grp {
>> +			nuvoton,pins =
>> +				<MA35_SYS_REG_GPK_L 0 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPK_L 4 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPK_L 8 2 &pcfg_default>,
>> +				<MA35_SYS_REG_GPK_L 12 2 &pcfg_default>;
>> +		};
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart0>;
>> +	status = "okay";
>> +};
>> +
>> +&uart11 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart11>;
>> +	status = "okay";
>> +};
>> +
>> +&uart12 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart12>;
>> +	status = "okay";
>> +};
>> +
>> +&uart14 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart14>;
>> +	status = "okay";
>> +};
>> +
>> +&uart16 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_uart16>;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> index 781cdae566a0..85431a074ab2 100644
>> --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> @@ -10,6 +10,7 @@
>>   #include <dt-bindings/gpio/gpio.h>
>>   #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>>   #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
>> +#include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
>>   
>>   / {
>>   	compatible = "nuvoton,ma35d1";
>> @@ -83,7 +84,7 @@ soc {
>>   		ranges;
>>   
>>   		sys: system-management@40460000 {
>> -			compatible = "nuvoton,ma35d1-reset";
>> +			compatible = "nuvoton,ma35d1-reset", "syscon";
>>   			reg = <0x0 0x40460000 0x0 0x200>;
>>   			#reset-cells = <1>;
>>   		};
>> @@ -95,6 +96,178 @@ clk: clock-controller@40460200 {
>>   			clocks = <&clk_hxt>;
>>   		};
>>   
>> +		pinctrl: pinctrl@40040000 {
>> +			compatible = "nuvoton,ma35d1-pinctrl";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			nuvoton,sys = <&sys>;
>> +			ranges = <0x0 0x0 0x40040000 0xc00>;
>> +
>> +			gpioa: gpioa@40040000 {
>> +				reg = <0x0 0x40>;
>> +				interrupts = <GIC_SPI  14 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPA_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiob: gpiob@40040040 {
>> +				reg = <0x40 0x40>;
>> +				interrupts = <GIC_SPI  15 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPB_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpioc: gpioc@40040080 {
>> +				reg = <0x80 0x40>;
>> +				interrupts = <GIC_SPI  16 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPC_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiod: gpiod@400400c0 {
>> +				reg = <0xc0 0x40>;
>> +				interrupts = <GIC_SPI  17 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPD_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpioe: gpioe@40040100 {
>> +				reg = <0x100 0x40>;
>> +				interrupts = <GIC_SPI  73 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPE_GATE>;
>> +				#gpio-cells = <2>;
>> +				gpio-controller;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiof: gpiof@40040140 {
>> +				reg = <0x140 0x40>;
>> +				interrupts = <GIC_SPI  74 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPF_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiog: gpiog@40040180 {
>> +				reg = <0x180 0x40>;
>> +				interrupts = <GIC_SPI  75 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPG_GATE>;
>> +				#gpio-cells = <2>;
>> +				gpio-controller;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpioh: gpioh@400401c0 {
>> +				reg = <0x1c0 0x40>;
>> +				interrupts = <GIC_SPI  76 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPH_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpioi: gpioi@40040200 {
>> +				reg = <0x200 0x40>;
>> +				interrupts = <GIC_SPI  77 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPI_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpioj: gpioj@40040240 {
>> +				reg = <0x240 0x40>;
>> +				interrupts = <GIC_SPI  78 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPJ_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiok: gpiok@40040280 {
>> +				reg = <0x280 0x40>;
>> +				interrupts = <GIC_SPI  102 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPK_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiol: gpiol@400402c0 {
>> +				reg = <0x2c0 0x40>;
>> +				interrupts = <GIC_SPI  103 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPL_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpiom: gpiom@40040300 {
>> +				reg = <0x300 0x40>;
>> +				interrupts = <GIC_SPI  104 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPM_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			gpion: gpion@40040340 {
>> +				reg = <0x340 0x40>;
>> +				interrupts = <GIC_SPI  105 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&clk GPN_GATE>;
>> +				gpio-controller;
>> +				#gpio-cells = <2>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +			};
>> +
>> +			pcfg_default: pcfg-default {
>> +				slew-rate = <0>;
>> +				input-schmitt-disable;
>> +				bias-disable;
>> +				power-source = <3300>;
>> +				drive-strength = <0>;
>> +			};
>> +
>> +			pcfg_emac_3_3v: pcfg-emac-3.3v {
> Drop, unused.
>
>> +				slew-rate = <0>;
>> +				input-schmitt-enable;
>> +				bias-disable;
>> +				power-source = <3300>;
>> +				drive-strength = <1>;
>> +			};
>> +
>> +			pcfg_emac_1_8v: pcfg-emac-1.8v {
> Drop, unused.

Sure, I will drop these two nodes.

>> +				slew-rate = <0>;
>> +				input-schmitt-enable;
>> +				bias-disable;
>> +				power-source = <1800>;
>> +				drive-strength = <1>;
>> +			};
>> +		};
>> +
>>   		uart0: serial@40700000 {
>>   			compatible = "nuvoton,ma35d1-uart";
>>   			reg = <0x0 0x40700000 0x0 0x100>;
> Best regards,
> Krzysztof
>

Best Regards,
Jacky Huang

Re: [PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1

[Krzysztof Kozlowski]

On 13/10/2023 08:52, Jacky Huang wrote:
>>> +
>>> +&pinctrl {
>>> +	uart0 {
>>> +		pinctrl_uart0: uart0grp {
>>> +			nuvoton,pins =
>>> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
>>> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
>> This does not look like generic pinctrl bindings. Looks
>> over-complicated. From where did you get it? Which recent bindings and
>> drivers where used as an example? Register addresses should be in the
>> driver. Bit offsets as well. "multi-pin-function-value" confuses me. All
>> this is not really suitable for DTS.
> 
> Okay, I will update the first and second items to 'pin bank' and 'pin 
> bank index,
> just as others have done, and leave the driver to handle the conversion into
> registers and offsets.

Instead use existing common properties, like "pins" and "groups" (or
pinmux).

> 
> The term "multi-pin-function-value" is used to specify the device function.
> I will use the name "device function" instead of "multi-pin-function-value.

Use existing common properties, like "function". Do not reinvent the
bindings.



Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1

[Jacky Huang]

On 2023/10/13 下午 03:06, Krzysztof Kozlowski wrote:
> On 13/10/2023 08:52, Jacky Huang wrote:
>>>> +
>>>> +&pinctrl {
>>>> +	uart0 {
>>>> +		pinctrl_uart0: uart0grp {
>>>> +			nuvoton,pins =
>>>> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
>>>> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
>>> This does not look like generic pinctrl bindings. Looks
>>> over-complicated. From where did you get it? Which recent bindings and
>>> drivers where used as an example? Register addresses should be in the
>>> driver. Bit offsets as well. "multi-pin-function-value" confuses me. All
>>> this is not really suitable for DTS.
>> Okay, I will update the first and second items to 'pin bank' and 'pin
>> bank index,
>> just as others have done, and leave the driver to handle the conversion into
>> registers and offsets.
> Instead use existing common properties, like "pins" and "groups" (or
> pinmux).

I will reference how others have done it to make the changes.

>> The term "multi-pin-function-value" is used to specify the device function.
>> I will use the name "device function" instead of "multi-pin-function-value.
> Use existing common properties, like "function". Do not reinvent the
> bindings.
>

Okay, I got it. Thank you.

>
> Best regards,
> Krzysztof
>


Best Regards,
Jacky Huang

[PATCH 4/4] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver

[Jacky Huang]

From: Jacky Huang <ychuang3@nuvoton.com>

Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and
add support for ma35d1 pinctrl.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 drivers/pinctrl/nuvoton/Kconfig          |   22 +
 drivers/pinctrl/nuvoton/Makefile         |    2 +
 drivers/pinctrl/nuvoton/pinctrl-ma35.c   | 1239 +++++++++++++++
 drivers/pinctrl/nuvoton/pinctrl-ma35.h   |   50 +
 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c | 1797 ++++++++++++++++++++++
 5 files changed, 3110 insertions(+)
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.c
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.h
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c

diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
index 8fe61b348181..1b87f4e414ee 100644
--- a/drivers/pinctrl/nuvoton/Kconfig
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -32,3 +32,25 @@ config PINCTRL_NPCM7XX
 	help
 	  Say Y here to enable pin controller and GPIO support
 	  for Nuvoton NPCM750/730/715/705 SoCs.
+
+if ARCH_MA35 || COMPILE_TEST
+
+config PINCTRL_MA35
+	bool
+	depends on OF
+	select GENERIC_PINCTRL_GROUPS
+	select GENERIC_PINMUX_FUNCTIONS
+	select GENERIC_PINCONF
+	select GPIOLIB
+	select GPIO_GENERIC
+	select GPIOLIB_IRQCHIP
+	select MFD_SYSCON
+
+config PINCTRL_MA35D1
+	bool "Pinctrl and GPIO driver for Nuvoton MA35D1"
+	depends on OF
+	select PINCTRL_MA35
+	help
+	  Say Y here to enable pin controller and GPIO support
+	  for Nuvoton MA35D1 SoC.
+endif
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
index 9e66f5dc74bf..6324e987b30d 100644
--- a/drivers/pinctrl/nuvoton/Makefile
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -3,3 +3,5 @@
 
 obj-$(CONFIG_PINCTRL_WPCM450)	+= pinctrl-wpcm450.o
 obj-$(CONFIG_PINCTRL_NPCM7XX)	+= pinctrl-npcm7xx.o
+obj-$(CONFIG_PINCTRL_MA35)	+= pinctrl-ma35.o
+obj-$(CONFIG_PINCTRL_MA35D1)	+= pinctrl-ma35d1.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c
new file mode 100644
index 000000000000..3130b6054654
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c
@@ -0,0 +1,1239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+#include <linux/gpio/driver.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "pinctrl-ma35.h"
+
+#define MA35_MFP_REG_BASE		0x80
+#define MA35_MFP_REG_OFFSET_PER_GROUP	8
+#define MA35_MFP_BITS_PER_PORT		4
+
+#define MA35_GPIO_GROUP_MAX		14
+#define MA35_GPIO_GROUP_PORT_MAX	16
+
+/* GPIO control registers */
+#define MA35_GP_REG_MODE		0x00
+#define MA35_GP_REG_DINOFF		0x04
+#define MA35_GP_REG_DOUT		0x08
+#define MA35_GP_REG_DATMSK		0x0c
+#define MA35_GP_REG_PIN			0x10
+#define MA35_GP_REG_DBEN		0x14
+#define MA35_GP_REG_INTTYPE		0x18
+#define MA35_GP_REG_INTEN		0x1c
+#define MA35_GP_REG_INTSRC		0x20
+#define MA35_GP_REG_SMTEN		0x24
+#define MA35_GP_REG_SLEWCTL		0x28
+#define MA35_GP_REG_SPW			0x2c
+#define MA35_GP_REG_PUSEL		0x30
+#define MA35_GP_REG_DSL			0x38
+#define MA35_GP_REG_DSH			0x3c
+
+/* GPIO mode control */
+#define MA35_GP_MODE_INPUT		0x0
+#define MA35_GP_MODE_OUTPUT		0x1
+#define MA35_GP_MODE_OPEN_DRAIN		0x2
+#define MA35_GP_MODE_QUASI		0x3
+
+/* GPIO pull-up and pull-down selection control */
+#define MA35_GP_PUSEL_DISABLE		0x0
+#define MA35_GP_PUSEL_PULL_UP		0x1
+#define MA35_GP_PUSEL_PULL_DOWN		0x2
+
+/* Each pin data input/output is mapped by address mapping */
+#define MA35_PIN_MAP_BASE		0x800
+
+#define MA35_GP_DSH_BASE_PORT		8
+
+#define VOLT_1_8			1800
+#define VOLT_3_3			3300
+
+char *gpio_group_name[] = {
+	"gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog",
+	"gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion",
+};
+
+struct ma35_pin_func {
+	const char		*name;
+	const char		**groups;
+	u32			ngroups;
+};
+
+struct ma35_pin_setting {
+	u32			offset;
+	u32			shift;
+	u32			muxval;
+	unsigned long		*configs;
+	unsigned int		nconfigs;
+};
+
+struct ma35_pin_group {
+	const char		*name;
+	unsigned int		npins;
+	unsigned int		*pins;
+	struct ma35_pin_setting	*settings;
+};
+
+struct ma35_pin_bank {
+	void __iomem		*reg_base;
+	struct clk		*clk;
+	int			irq;
+	u8			nr_pins;
+	char			*name;
+	u8			bank_num;
+	bool			valid;
+	struct device_node	*of_node;
+	struct gpio_chip	chip;
+	struct irq_chip		irqc;
+	u32			irqtype;
+	u32			irqinten;
+	struct regmap		*regmap;
+	struct device		*dev;
+	spinlock_t		lock;
+};
+
+struct ma35_pin_ctrl {
+	struct ma35_pin_bank	*pin_banks;
+	u32			nr_banks;
+	u32			nr_pins;
+};
+
+struct ma35_pinctrl {
+	struct device		*dev;
+	struct ma35_pin_ctrl	*ctrl;
+	struct pinctrl_dev	*pctl;
+	const struct ma35_pinctrl_soc_info *info;
+	struct regmap		*regmap;
+	struct ma35_pin_group	*groups;
+	unsigned int		ngroups;
+	struct ma35_pin_func	*functions;
+	unsigned int		nfunctions;
+};
+
+static int ma35_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return npctl->ngroups;
+}
+
+static const char *ma35_get_group_name(struct pinctrl_dev *pctldev,
+				       unsigned int selector)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return npctl->groups[selector].name;
+}
+
+static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
+			       const unsigned int **pins, unsigned int *npins)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+	if (selector >= npctl->ngroups)
+		return -EINVAL;
+
+	*pins = npctl->groups[selector].pins;
+	*npins = npctl->groups[selector].npins;
+
+	return 0;
+}
+
+static struct ma35_pin_group *ma35_pinctrl_find_group_by_name(
+			      const struct ma35_pinctrl *npctl, const char *name)
+{
+	int i;
+
+	for (i = 0; i < npctl->ngroups; i++) {
+		if (!strcmp(npctl->groups[i].name, name))
+			return &npctl->groups[i];
+	}
+
+	return NULL;
+}
+
+static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev,
+					    struct device_node *np,
+					    struct pinctrl_map **map,
+					    unsigned int *num_maps)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+	struct ma35_pin_group *grp;
+	struct pinctrl_map *new_map;
+	struct device_node *parent;
+	int map_num = 1;
+	int i;
+
+	/*
+	 * first find the group of this node and check if we need create
+	 * config maps for pins
+	 */
+	grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
+	if (!grp) {
+		dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
+		return -EINVAL;
+	}
+
+	map_num += grp->npins;
+	new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
+	if (!new_map)
+		return -ENOMEM;
+
+	*map = new_map;
+	*num_maps = map_num;
+	/* create mux map */
+	parent = of_get_parent(np);
+	if (!parent) {
+		devm_kfree(pctldev->dev, new_map);
+		return -EINVAL;
+	}
+
+	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+	new_map[0].data.mux.function = parent->name;
+	new_map[0].data.mux.group = np->name;
+	of_node_put(parent);
+
+	new_map++;
+	for (i = 0; i < grp->npins; i++) {
+		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+		new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);
+		new_map[i].data.configs.configs = grp->settings[i].configs;
+		new_map[i].data.configs.num_configs = grp->settings[i].nconfigs;
+	}
+	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+	return 0;
+}
+
+static void ma35_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map,
+			     unsigned int num_maps)
+{
+	devm_kfree(pctldev->dev, map);
+}
+
+static const struct pinctrl_ops ma35_pctrl_ops = {
+	.get_groups_count = ma35_get_groups_count,
+	.get_group_name = ma35_get_group_name,
+	.get_group_pins = ma35_get_group_pins,
+	.dt_node_to_map = ma35_pinctrl_dt_node_to_map_func,
+	.dt_free_map = ma35_dt_free_map,
+};
+
+static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return npctl->nfunctions;
+}
+
+static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+					     unsigned int selector)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return npctl->functions[selector].name;
+}
+
+static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev,
+				       unsigned int function,
+				       const char *const **groups,
+				       unsigned int *const num_groups)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+	*groups = npctl->functions[function].groups;
+	*num_groups = npctl->functions[function].ngroups;
+
+	return 0;
+}
+
+static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
+			       unsigned int group)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+	struct ma35_pin_group *grp = &npctl->groups[group];
+	struct ma35_pin_setting *setting = grp->settings;
+	u32 i, regval;
+
+	dev_dbg(npctl->dev, "enable function %s group %s\n",
+		npctl->functions[selector].name, npctl->groups[group].name);
+
+	for (i = 0; i < grp->npins; i++) {
+		regmap_read(npctl->regmap, setting->offset, &regval);
+		regval &= ~GENMASK(setting->shift + 3, setting->shift);
+		regval |= setting->muxval << setting->shift;
+
+		regmap_write(npctl->regmap, setting->offset, regval);
+		setting++;
+	}
+	return 0;
+}
+
+const struct pinmux_ops ma35_pmx_ops = {
+	.get_functions_count = ma35_pinmux_get_func_count,
+	.get_function_name = ma35_pinmux_get_func_name,
+	.get_function_groups = ma35_pinmux_get_func_groups,
+	.set_mux = ma35_pinmux_set_mux,
+	.strict = true,
+};
+
+static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+	void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
+	unsigned long flags;
+	unsigned int regval;
+
+	spin_lock_irqsave(&bank->lock, flags);
+
+	regval = readl(reg_mode);
+
+	regval &= ~GENMASK(gpio * 2 + 1, gpio * 2);
+	regval |= MA35_GP_MODE_INPUT << gpio * 2;
+
+	writel(regval, reg_mode);
+
+	spin_unlock_irqrestore(&bank->lock, flags);
+
+	return 0;
+}
+
+static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+
+	return readl(bank->reg_base + MA35_PIN_MAP_BASE + gpio * 4);
+}
+
+static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+
+	writel(val, bank->reg_base + MA35_PIN_MAP_BASE + gpio * 4);
+}
+
+static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio,
+					int val)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+	void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
+	void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
+	unsigned long flags;
+	unsigned int regval;
+
+	spin_lock_irqsave(&bank->lock, flags);
+
+	regval = readl(reg_dout);
+	if (val)
+		writel(regval | BIT(gpio), reg_dout);
+	else
+		writel(regval & ~BIT(gpio), reg_dout);
+
+	regval = readl(reg_mode);
+
+	regval &= ~GENMASK(gpio * 2 + 1, gpio * 2);
+	regval |= MA35_GP_MODE_OUTPUT << gpio * 2;
+
+	writel(regval, reg_mode);
+
+	spin_unlock_irqrestore(&bank->lock, flags);
+
+	return 0;
+}
+
+static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+	u32 reg_offs, bit_offs, regval;
+
+	if (gpio < 8) {
+		/* The MFP low register controls port 0 ~ 7 */
+		reg_offs = bank->bank_num * MA35_MFP_REG_OFFSET_PER_GROUP;
+		bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
+	} else {
+		/* The MFP high register controls port 8 ~ 15 */
+		reg_offs = bank->bank_num * MA35_MFP_REG_OFFSET_PER_GROUP + 4;
+		bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
+	}
+
+	regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, &regval);
+
+	regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
+
+	regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
+
+	return 0;
+}
+
+static void ma35_irq_gpio_mask(struct irq_data *d)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+	unsigned int num = (d->hwirq);
+	u32 regval;
+
+	regval = readl(reg_ien);
+
+	/*
+	 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
+	 * while bits 16 ~ 31 control high-level or rising edge trigger.
+	 * We disable both type of interrupt.
+	 */
+	regval &= ~(BIT(num + 16) | BIT(num));
+
+	writel(regval, reg_ien);
+}
+
+static void ma35_irq_gpio_unmask(struct irq_data *d)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+	void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
+	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+	unsigned int num = (d->hwirq);
+	u32 bval, regval;
+
+	bval = bank->irqtype & BIT(num);
+
+	regval = readl(reg_itype);
+	regval &= ~BIT(num);
+	writel(regval | bval, reg_itype);
+
+	bval = bank->irqinten & (BIT(num + 16) | BIT(num));
+
+	regval = readl(reg_ien);
+	regval &= ~(BIT(num + 16) | BIT(num));
+	writel(regval | bval, reg_ien);
+}
+
+static int ma35_irq_irqtype(struct irq_data *d, unsigned int type)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+	void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
+	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+	unsigned int num = (d->hwirq);
+
+	if (type == IRQ_TYPE_PROBE) {
+		writel(readl(reg_itype) & ~BIT(num), reg_itype);
+		writel(readl(reg_ien) | BIT(num) | BIT(num + 16), reg_ien);
+		bank->irqtype &= ~BIT(num);
+		bank->irqinten |= BIT(num) | BIT(num + 16);
+		return 0;
+	}
+
+	if (type & IRQ_TYPE_LEVEL_MASK) {
+		writel(readl(reg_itype) | BIT(num), reg_itype);
+		writel(readl(reg_ien) & ~(BIT(num) | BIT(num + 16)), reg_ien);
+		bank->irqtype |= BIT(num);
+		bank->irqinten &= ~(BIT(num) | BIT(num + 16));
+		if (type == IRQ_TYPE_LEVEL_HIGH) {
+			writel(readl(reg_ien) | BIT(num + 16), reg_ien);
+			bank->irqinten |= BIT(num + 16);
+			return 0;
+		}
+
+		if (type == IRQ_TYPE_LEVEL_LOW) {
+			writel(readl(reg_ien) | BIT(num), reg_ien);
+			bank->irqinten |= BIT(num);
+			return 0;
+		}
+
+	} else {
+		writel(readl(reg_itype) & ~BIT(num), reg_itype);
+		bank->irqtype &= ~BIT(num);
+
+		if (type & IRQ_TYPE_EDGE_RISING) {
+			writel(readl(reg_ien) | BIT(num + 16), reg_ien);
+			bank->irqinten |= BIT(num + 16);
+
+		} else {
+			writel(readl(reg_ien) & ~BIT(num + 16), reg_ien);
+			bank->irqinten &= ~BIT(num + 16);
+		}
+
+		if (type & IRQ_TYPE_EDGE_FALLING) {
+			writel(readl(reg_ien) | BIT(num), reg_ien);
+			bank->irqinten |= BIT(num);
+
+		} else {
+			writel(readl(reg_ien) & ~BIT(num), reg_ien);
+			bank->irqinten &= ~BIT(num);
+		}
+	}
+	return 0;
+}
+
+static void ma35_irq_demux_intgroup(struct irq_desc *desc)
+{
+	struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
+	struct irq_domain *irqdomain = bank->chip.irq.domain;
+	struct irq_chip *irqchip = irq_desc_get_chip(desc);
+	unsigned int j, isr;
+
+	chained_irq_enter(irqchip, desc);
+
+	isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
+
+	if (isr != 0) {
+		writel(isr, bank->reg_base + MA35_GP_REG_INTSRC);
+
+		for (j = 0; j < 16; j++) {
+			if (isr & 0x1)
+				generic_handle_irq(irq_find_mapping(irqdomain, j));
+			isr = isr >> 1;
+		}
+	}
+
+	chained_irq_exit(irqchip, desc);
+}
+
+static int ma35_gpiolib_register(struct platform_device *pdev,
+				 struct ma35_pinctrl *npctl)
+{
+	struct ma35_pin_ctrl *ctrl = npctl->ctrl;
+	struct ma35_pin_bank *bank = ctrl->pin_banks;
+	int ret;
+	int i;
+
+	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+		if (!bank->valid) {
+			dev_warn(&pdev->dev, "bank %s is not valid\n",
+				 bank->of_node->name);
+			continue;
+		}
+		bank->irqtype = 0;
+		bank->irqinten = 0;
+		bank->chip.label = bank->name;
+		bank->chip.of_gpio_n_cells = 2;
+		bank->chip.parent = &pdev->dev;
+		bank->chip.request = ma35_gpio_core_to_request;
+		bank->chip.direction_input = ma35_gpio_core_direction_in;
+		bank->chip.direction_output = ma35_gpio_core_direction_out;
+		bank->chip.get = ma35_gpio_core_get;
+		bank->chip.set = ma35_gpio_core_set;
+		bank->chip.base = -1;
+		bank->chip.ngpio = bank->nr_pins;
+		bank->chip.can_sleep = false;
+		spin_lock_init(&bank->lock);
+
+		if (bank->irq > 0) {
+			struct gpio_irq_chip *girq;
+
+			girq = &bank->chip.irq;
+			girq->chip = &bank->irqc;
+			girq->chip->name = bank->name;
+			girq->chip->irq_disable = ma35_irq_gpio_mask;
+			girq->chip->irq_enable = ma35_irq_gpio_unmask;
+			girq->chip->irq_set_type = ma35_irq_irqtype;
+			girq->chip->irq_mask = ma35_irq_gpio_mask;
+			girq->chip->irq_unmask = ma35_irq_gpio_unmask;
+			girq->chip->flags = IRQCHIP_MASK_ON_SUSPEND |
+			IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE;
+			girq->parent_handler = ma35_irq_demux_intgroup;
+			girq->num_parents = 1;
+
+			girq->parents = devm_kcalloc(&pdev->dev, 1,
+						     sizeof(*girq->parents),
+						     GFP_KERNEL);
+			if (!girq->parents)
+				return -ENOMEM;
+
+			girq->parents[0] = bank->irq;
+			girq->default_type = IRQ_TYPE_NONE;
+			girq->handler = handle_level_irq;
+		}
+
+		ret = gpiochip_add_data(&bank->chip, bank);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"failed to register gpio_chip %s, error code: %d\n",
+				bank->chip.label, ret);
+			goto fail;
+		}
+	}
+	return 0;
+fail:
+	for (--i, --bank; i >= 0; --i, --bank) {
+		if (!bank->valid)
+			continue;
+		gpiochip_remove(&bank->chip);
+	}
+	return ret;
+}
+
+static int ma35_get_bank_data(struct ma35_pin_bank *bank, struct ma35_pinctrl *npctl)
+{
+	struct resource res;
+
+	if (of_address_to_resource(bank->of_node, 0, &res)) {
+		dev_err(npctl->dev, "cannot find IO resource for bank\n");
+		return -ENOENT;
+	}
+
+	bank->reg_base = devm_ioremap_resource(npctl->dev, &res);
+	if (IS_ERR(bank->reg_base)) {
+		dev_err(npctl->dev, "cannot ioremap resource for bank\n");
+		return PTR_ERR(bank->reg_base);
+	}
+
+	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
+	bank->nr_pins = MA35_GPIO_GROUP_PORT_MAX;
+
+	bank->clk = of_clk_get(bank->of_node, 0);
+	if (IS_ERR(bank->clk))
+		return PTR_ERR(bank->clk);
+
+	return clk_prepare_enable(bank->clk);
+}
+
+static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl,
+				     struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct device_node *np;
+	struct ma35_pin_ctrl *ctrl;
+	struct ma35_pin_bank *bank;
+	int i;
+
+	ctrl = pctl->ctrl;
+	ctrl->nr_banks = MA35_GPIO_GROUP_MAX;
+	ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
+				       sizeof(*ctrl->pin_banks), GFP_KERNEL);
+	if (!ctrl->pin_banks)
+		return -ENOMEM;
+
+	for (i = 0; i < ctrl->nr_banks; i++) {
+		ctrl->pin_banks[i].bank_num = i;
+		ctrl->pin_banks[i].name = gpio_group_name[i];
+	}
+
+	for_each_child_of_node(node, np) {
+		if (!of_find_property(np, "gpio-controller", NULL))
+			continue;
+
+		bank = ctrl->pin_banks;
+		for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+			if (!strcmp(bank->name, np->name)) {
+				bank->of_node = np;
+				bank->regmap = pctl->regmap;
+				bank->dev = &pdev->dev;
+				if (!ma35_get_bank_data(bank, pctl))
+					bank->valid = true;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group,
+			       unsigned int *num)
+{
+	*group = gpio_num / MA35_GPIO_GROUP_PORT_MAX;
+	*num = gpio_num % MA35_GPIO_GROUP_PORT_MAX;
+}
+
+static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,
+				 int pull_up)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_PUSEL);
+
+	regval &= ~GENMASK(port * 2 + 1, port * 2);
+
+	switch (pull_up) {
+	case PIN_CONFIG_BIAS_PULL_UP:
+		regval |= MA35_GP_PUSEL_PULL_UP << port * 2;
+		break;
+
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		regval |= MA35_GP_PUSEL_PULL_DOWN << port * 2;
+		break;
+
+	case MA35_GP_PUSEL_DISABLE:
+		regval |= MA35_GP_PUSEL_DISABLE << port * 2;
+		break;
+
+	default:
+		regval |= MA35_GP_PUSEL_DISABLE << port * 2;
+		break;
+	}
+
+	writel(regval, base + MA35_GP_REG_PUSEL);
+
+	return 0;
+}
+
+static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval, mode;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_MODE);
+	mode = (regval & GENMASK(port * 2 + 1, port * 2)) >> port * 2;
+
+	if (mode == MA35_GP_MODE_OUTPUT)
+		return 1;
+
+	return 0;
+}
+
+static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval, mode;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_PUSEL);
+	mode = (regval & GENMASK(port * 2 + 1, port * 2)) >> port * 2;
+
+	switch (mode) {
+	case MA35_GP_PUSEL_PULL_UP:
+		return PIN_CONFIG_BIAS_PULL_UP;
+
+	case MA35_GP_PUSEL_PULL_DOWN:
+		return PIN_CONFIG_BIAS_PULL_DOWN;
+
+	case MA35_GP_PUSEL_DISABLE:
+		return PIN_CONFIG_BIAS_DISABLE;
+	}
+
+	return PIN_CONFIG_BIAS_DISABLE;
+}
+
+static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin,
+				   bool out)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_MODE);
+
+	regval &= ~GENMASK(port * 2 + 1, port * 2);
+	regval |= MA35_GP_MODE_OUTPUT << port * 2;
+
+	writel(regval, base + MA35_GP_REG_MODE);
+
+	return 0;
+}
+
+static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl,
+					   unsigned int pin, u16 *strength)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	if (port < MA35_GP_DSH_BASE_PORT) {
+		regval = readl(base + MA35_GP_REG_DSL);
+		*strength = (regval & GENMASK(port * 4 + 3, port * 4)) >> port * 4;
+	} else {
+		port -= MA35_GP_DSH_BASE_PORT;
+		regval = readl(base + MA35_GP_REG_DSH);
+		*strength = (regval & GENMASK(port * 4 + 3, port * 4)) >> port * 4;
+	}
+	return 0;
+}
+
+static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl,
+					   unsigned int pin, int strength)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	if (port < MA35_GP_DSH_BASE_PORT) {
+		regval = readl(base + MA35_GP_REG_DSL);
+		regval &= ~GENMASK(port * 4 + 3, port * 4);
+		regval |= strength << port * 4;
+		writel(regval, base + MA35_GP_REG_DSL);
+	} else {
+		port -= MA35_GP_DSH_BASE_PORT;
+		regval = readl(base + MA35_GP_REG_DSH);
+		regval &= ~GENMASK(port * 4 + 3, port * 4);
+		regval |= strength << port * 4;
+		writel(regval, base + MA35_GP_REG_DSH);
+	}
+
+	return 0;
+}
+
+static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl,
+					   unsigned int pin)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_SMTEN);
+
+	return !!(regval & BIT(port));
+}
+
+static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin,
+				    int enable)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_SMTEN);
+
+	if (enable)
+		regval |= BIT(port);
+	else
+		regval &= ~BIT(port);
+
+	writel(regval, base + MA35_GP_REG_SMTEN);
+
+	return 0;
+}
+
+static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl,
+				      unsigned int pin)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_SLEWCTL);
+
+	return (regval & GENMASK(port * 2 + 1, port * 2)) >> port * 2;
+}
+
+static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl,
+				      unsigned int pin, int rate)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_SLEWCTL);
+
+	regval &= ~GENMASK(port * 2 + 1, port * 2);
+	regval |= rate << port * 2;
+
+	writel(regval, base + MA35_GP_REG_SLEWCTL);
+
+	return 0;
+}
+
+static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl,
+					 unsigned int pin, int volt)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	if ((volt != VOLT_1_8) && (volt != VOLT_3_3))
+		return -EINVAL;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_SPW);
+
+	if (volt == VOLT_1_8)
+		regval &= ~BIT(port);
+	else
+		regval |= BIT(port);
+
+	writel(regval, base + MA35_GP_REG_SPW);
+
+	return 0;
+}
+
+static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl,
+					 unsigned int pin)
+{
+	int port, group_num;
+	void __iomem *base;
+	u32 regval;
+
+	ma35_gpio_cla_port(pin, &group_num, &port);
+	base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+	regval = readl(base + MA35_GP_REG_SPW);
+
+	if (regval & BIT(port))
+		return VOLT_3_3;
+	else
+		return VOLT_1_8;
+}
+
+static int ma35_pinconf_get(struct pinctrl_dev *pctldev,
+			   unsigned int pin, unsigned long *config)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+	enum pin_config_param param = pinconf_to_config_param(*config);
+	u16 arg;
+	int ret;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+	case PIN_CONFIG_BIAS_PULL_UP:
+		if (ma35_pinconf_get_pull(npctl, pin) == param)
+			arg = 1;
+		else
+			return -EINVAL;
+		break;
+
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);
+		if (ret)
+			return ret;
+		break;
+
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		arg = ma35_pinconf_get_schmitt_enable(npctl, pin);
+		break;
+
+	case PIN_CONFIG_SLEW_RATE:
+		arg = ma35_pinconf_get_slew_rate(npctl, pin);
+		break;
+
+	case PIN_CONFIG_OUTPUT_ENABLE:
+		arg = ma35_pinconf_get_output(npctl, pin);
+		break;
+
+	case PIN_CONFIG_POWER_SOURCE:
+		 arg = ma35_pinconf_get_power_source(npctl, pin);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	*config = pinconf_to_config_packed(param, arg);
+
+	return 0;
+}
+
+static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+			    unsigned long *configs, unsigned int num_configs)
+{
+	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+	enum pin_config_param param;
+	unsigned int arg = 0;
+	int i, ret = 0;
+
+	for (i = 0; i < num_configs; i++) {
+		param = pinconf_to_config_param(configs[i]);
+		arg = pinconf_to_config_argument(configs[i]);
+
+		switch (param) {
+		case PIN_CONFIG_BIAS_DISABLE:
+		case PIN_CONFIG_BIAS_PULL_UP:
+		case PIN_CONFIG_BIAS_PULL_DOWN:
+			ret = ma35_pinconf_set_pull(npctl, pin, param);
+			break;
+
+		case PIN_CONFIG_DRIVE_STRENGTH:
+			ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);
+			break;
+
+		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+			ret = ma35_pinconf_set_schmitt(npctl, pin, 1);
+			break;
+
+		case PIN_CONFIG_INPUT_SCHMITT:
+			ret = ma35_pinconf_set_schmitt(npctl, pin, arg);
+			break;
+
+		case PIN_CONFIG_SLEW_RATE:
+			ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);
+			break;
+
+		case PIN_CONFIG_OUTPUT_ENABLE:
+			ret = ma35_pinconf_set_output(npctl, pin, arg);
+			break;
+
+		case PIN_CONFIG_POWER_SOURCE:
+			ret = ma35_pinconf_set_power_source(npctl, pin, arg);
+			break;
+
+		default:
+			return -EINVAL;
+		}
+	}
+	return ret;
+}
+
+static const struct pinconf_ops ma35_pinconf_ops = {
+	.pin_config_get = ma35_pinconf_get,
+	.pin_config_set = ma35_pinconf_set,
+	.is_generic = true,
+};
+
+static int ma35_pinctrl_parse_groups(struct device_node *np,
+				    struct ma35_pin_group *grp,
+				    struct ma35_pinctrl *npctl, u32 index)
+{
+	struct ma35_pin_setting *pin;
+	const __be32 *list;
+	int i, j, size, ret;
+
+	dev_dbg(npctl->dev, "group(%d): %s\n", index, np->name);
+
+	grp->name = np->name;
+
+	/*
+	 * the binding format is nuvoton,pins = <bank pin-mfp pin-function>,
+	 * do sanity check and calculate pins number
+	 */
+	list = of_get_property(np, "nuvoton,pins", &size);
+	size /= sizeof(*list);
+	if (!size || size % 4) {
+		dev_err(npctl->dev, "wrong setting!\n");
+		return -EINVAL;
+	}
+
+	grp->npins = size / 4;
+
+	grp->pins = devm_kzalloc(npctl->dev, grp->npins * sizeof(*grp->pins),
+				 GFP_KERNEL);
+	if (!grp->pins)
+		return -ENOMEM;
+
+	pin = grp->settings = devm_kzalloc(npctl->dev,
+					   grp->npins * sizeof(*grp->settings),
+					   GFP_KERNEL);
+	if (!grp->settings)
+		return -ENOMEM;
+
+	for (i = 0, j = 0; i < size; i += 4, j++) {
+		struct device_node *np_config;
+		const __be32 *phandle;
+
+		pin->offset = be32_to_cpu(*list++);
+		pin->shift = be32_to_cpu(*list++);
+		pin->muxval = be32_to_cpu(*list++);
+
+		phandle = list++;
+		if (!phandle)
+			return -EINVAL;
+
+		np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
+
+		ret = pinconf_generic_parse_dt_config(np_config, NULL,
+						      &pin->configs,
+						      &pin->nconfigs);
+		if (ret)
+			return ret;
+		grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
+		pin++;
+	}
+	return 0;
+}
+
+static int ma35_pinctrl_parse_functions(struct device_node *np,
+					struct ma35_pinctrl *npctl,
+					u32 index)
+{
+	struct device_node *child;
+	struct ma35_pin_func *func;
+	struct ma35_pin_group *grp;
+	static u32 grp_index;
+	u32 ret, i = 0;
+
+	dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
+
+	func = &npctl->functions[index];
+
+	func->name = np->name;
+	func->ngroups = of_get_child_count(np);
+
+	if (func->ngroups <= 0)
+		return 0;
+
+	func->groups = devm_kzalloc(npctl->dev,
+				    func->ngroups * sizeof(char *), GFP_KERNEL);
+	if (!func->groups)
+		return -ENOMEM;
+
+	for_each_child_of_node(np, child) {
+		func->groups[i] = child->name;
+		grp = &npctl->groups[grp_index++];
+		ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++);
+		if (ret) {
+			of_node_put(child);
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int ma35_pinctrl_probe_dt(struct platform_device *pdev,
+				 struct ma35_pinctrl *npctl)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *child;
+	u32 i = 0;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	for_each_child_of_node(np, child) {
+		if (of_property_read_bool(child, "gpio-controller"))
+			continue;
+		npctl->nfunctions++;
+		npctl->ngroups += of_get_child_count(child);
+	}
+
+	npctl->functions = devm_kzalloc(&pdev->dev,
+					npctl->nfunctions * sizeof(*npctl->functions),
+					GFP_KERNEL);
+	if (!npctl->functions)
+		return -ENOMEM;
+
+	npctl->groups = devm_kzalloc(&pdev->dev,
+				     npctl->ngroups * sizeof(*npctl->groups),
+				     GFP_KERNEL);
+	if (!npctl->groups)
+		return -ENOMEM;
+
+	dev_dbg(&pdev->dev, "nfunctions = %d\n", npctl->nfunctions);
+	dev_dbg(&pdev->dev, "ngroups = %d\n", npctl->ngroups);
+
+	i = 0;
+
+	for_each_child_of_node(np, child) {
+		if (of_property_read_bool(child, "gpio-controller"))
+			continue;
+
+		ret = ma35_pinctrl_parse_functions(child, npctl, i++);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to parse function\n");
+			of_node_put(child);
+			return ret;
+		}
+	}
+	return 0;
+}
+
+int ma35_pinctrl_probe(struct platform_device *pdev,
+		       const struct ma35_pinctrl_soc_info *info)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct pinctrl_desc *ma35_pinctrl_desc;
+	struct ma35_pinctrl *npctl;
+	int ret;
+
+	if (!info || !info->pins || !info->npins) {
+		dev_err(&pdev->dev, "wrong pinctrl info\n");
+		return -EINVAL;
+	}
+
+	npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
+	if (!npctl)
+		return -ENOMEM;
+
+	ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
+	if (!ma35_pinctrl_desc)
+		return -ENOMEM;
+
+	npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
+	if (!npctl->ctrl)
+		return -ENOMEM;
+
+	ma35_pinctrl_desc->name = dev_name(&pdev->dev);
+	ma35_pinctrl_desc->pins = info->pins;
+	ma35_pinctrl_desc->npins = info->npins;
+	ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
+	ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
+	ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
+	ma35_pinctrl_desc->owner = THIS_MODULE;
+
+	npctl->info = info;
+	npctl->dev = &pdev->dev;
+
+	npctl->regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys");
+	if (IS_ERR(npctl->regmap))
+		return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
+				     "No syscfg phandle specified\n");
+
+	ma35_pinctrl_get_soc_data(npctl, pdev);
+
+	platform_set_drvdata(pdev, npctl);
+
+	ret = ma35_pinctrl_probe_dt(pdev, npctl);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
+
+	ret = devm_pinctrl_register_and_init(&pdev->dev, ma35_pinctrl_desc,
+					     npctl, &npctl->pctl);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
+
+	ret = pinctrl_enable(npctl->pctl);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
+
+	return ma35_gpiolib_register(pdev, npctl);
+}
+
+int __maybe_unused ma35_pinctrl_suspend(struct device *dev)
+{
+	struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
+
+	return pinctrl_force_sleep(npctl->pctl);
+}
+
+int __maybe_unused ma35_pinctrl_resume(struct device *dev)
+{
+	struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
+
+	return pinctrl_force_default(npctl->pctl);
+}
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.h b/drivers/pinctrl/nuvoton/pinctrl-ma35.h
new file mode 100644
index 000000000000..83ddf0e83ef7
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ */
+#ifndef __PINCTRL_MA35_H
+#define __PINCTRL_MA35_H
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+
+struct ma35_mux_desc {
+	const char *name;
+	u32 muxval;
+};
+
+struct ma35_pin_data {
+	u32 offset;
+	u32 shift;
+	struct ma35_mux_desc *muxes;
+};
+
+struct ma35_pinctrl_soc_info {
+	const struct pinctrl_pin_desc *pins;
+	unsigned int npins;
+	int (*get_pin_num)(int offset, int shift);
+};
+
+#define MA35_PIN(num, n, o, s, ...) {			\
+	.number = num,					\
+	.name = #n,					\
+	.drv_data = &(struct ma35_pin_data) {		\
+		.offset = o,				\
+		.shift = s,				\
+		.muxes = (struct ma35_mux_desc[]) {	\
+			 __VA_ARGS__, { } },		\
+	},						\
+}
+
+#define MA35_MUX(_val, _name) {				\
+	.name = _name,					\
+	.muxval = _val,					\
+}
+
+int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info);
+int ma35_pinctrl_suspend(struct device *dev);
+int ma35_pinctrl_resume(struct device *dev);
+
+#endif /* __PINCTRL_MA35_H */
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
new file mode 100644
index 000000000000..1035923235f2
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
@@ -0,0 +1,1797 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-ma35.h"
+
+static const struct pinctrl_pin_desc ma35d1_pins[] = {
+	MA35_PIN(0, PA0, 0x80, 0x0,
+		MA35_MUX(0x0, "GPA0"),
+		MA35_MUX(0x2, "UART1_nCTS"),
+		MA35_MUX(0x3, "UART16_RXD"),
+		MA35_MUX(0x6, "NAND_DATA0"),
+		MA35_MUX(0x7, "EBI_AD0"),
+		MA35_MUX(0x9, "EBI_ADR0")),
+	MA35_PIN(1, PA1, 0x80, 0x4,
+		MA35_MUX(0x0, "GPA1"),
+		MA35_MUX(0x2, "UART1_nRTS"),
+		MA35_MUX(0x3, "UART16_TXD"),
+		MA35_MUX(0x6, "NAND_DATA1"),
+		MA35_MUX(0x7, "EBI_AD1"),
+		MA35_MUX(0x9, "EBI_ADR1")),
+	MA35_PIN(2, PA2, 0x80, 0x8,
+		MA35_MUX(0x0, "GPA2"),
+		MA35_MUX(0x2, "UART1_RXD"),
+		MA35_MUX(0x6, "NAND_DATA2"),
+		MA35_MUX(0x7, "EBI_AD2"),
+		MA35_MUX(0x9, "EBI_ADR2")),
+	MA35_PIN(3, PA3, 0x80, 0xc,
+		MA35_MUX(0x0, "GPA3"),
+		MA35_MUX(0x2, "UART1_TXD"),
+		MA35_MUX(0x6, "NAND_DATA3"),
+		MA35_MUX(0x7, "EBI_AD3"),
+		MA35_MUX(0x9, "EBI_ADR3")),
+	MA35_PIN(4, PA4, 0x80, 0x10,
+		MA35_MUX(0x0, "GPA4"),
+		MA35_MUX(0x2, "UART3_nCTS"),
+		MA35_MUX(0x3, "UART2_RXD"),
+		MA35_MUX(0x6, "NAND_DATA4"),
+		MA35_MUX(0x7, "EBI_AD4"),
+		MA35_MUX(0x9, "EBI_ADR4")),
+	MA35_PIN(5, PA5, 0x80, 0x14,
+		MA35_MUX(0x0, "GPA5"),
+		MA35_MUX(0x2, "UART3_nRTS"),
+		MA35_MUX(0x3, "UART2_TXD"),
+		MA35_MUX(0x6, "NAND_DATA5"),
+		MA35_MUX(0x7, "EBI_AD5"),
+		MA35_MUX(0x9, "EBI_ADR5")),
+	MA35_PIN(6, PA6, 0x80, 0x18,
+		MA35_MUX(0x0, "GPA6"),
+		MA35_MUX(0x2, "UART3_RXD"),
+		MA35_MUX(0x6, "NAND_DATA6"),
+		MA35_MUX(0x7, "EBI_AD6"),
+		MA35_MUX(0x9, "EBI_ADR6")),
+	MA35_PIN(7, PA7, 0x80, 0x1c,
+		MA35_MUX(0x0, "GPA7"),
+		MA35_MUX(0x2, "UART3_TXD"),
+		MA35_MUX(0x6, "NAND_DATA7"),
+		MA35_MUX(0x7, "EBI_AD7"),
+		MA35_MUX(0x9, "EBI_ADR7")),
+	MA35_PIN(8, PA8, 0x84, 0x0,
+		MA35_MUX(0x0, "GPA8"),
+		MA35_MUX(0x2, "UART5_nCTS"),
+		MA35_MUX(0x3, "UART4_RXD"),
+		MA35_MUX(0x6, "NAND_RDY0"),
+		MA35_MUX(0x7, "EBI_AD8"),
+		MA35_MUX(0x9, "EBI_ADR8")),
+	MA35_PIN(9, PA9, 0x84, 0x4,
+		MA35_MUX(0x0, "GPA9"),
+		MA35_MUX(0x2, "UART5_nRTS"),
+		MA35_MUX(0x3, "UART4_TXD"),
+		MA35_MUX(0x6, "NAND_nRE"),
+		MA35_MUX(0x7, "EBI_AD9"),
+		MA35_MUX(0x9, "EBI_ADR9")),
+	MA35_PIN(10, PA10, 0x84, 0x8,
+		MA35_MUX(0x0, "GPA10"),
+		MA35_MUX(0x2, "UART5_RXD"),
+		MA35_MUX(0x6, "NAND_nWE"),
+		MA35_MUX(0x7, "EBI_AD10"),
+		MA35_MUX(0x9, "EBI_ADR10")),
+	MA35_PIN(11, PA11, 0x84, 0xc,
+		MA35_MUX(0x0, "GPA11"),
+		MA35_MUX(0x2, "UART5_TXD"),
+		MA35_MUX(0x6, "NAND_CLE"),
+		MA35_MUX(0x7, "EBI_AD11"),
+		MA35_MUX(0x9, "EBI_ADR11")),
+	MA35_PIN(12, PA12, 0x84, 0x10,
+		MA35_MUX(0x0, "GPA12"),
+		MA35_MUX(0x2, "UART7_nCTS"),
+		MA35_MUX(0x3, "UART8_RXD"),
+		MA35_MUX(0x6, "NAND_ALE"),
+		MA35_MUX(0x7, "EBI_AD12"),
+		MA35_MUX(0x9, "EBI_ADR12")),
+	MA35_PIN(13, PA13, 0x84, 0x14,
+		MA35_MUX(0x0, "GPA13"),
+		MA35_MUX(0x2, "UART7_nRTS"),
+		MA35_MUX(0x3, "UART8_TXD"),
+		MA35_MUX(0x6, "NAND_nCS0"),
+		MA35_MUX(0x7, "EBI_AD13"),
+		MA35_MUX(0x9, "EBI_ADR13")),
+	MA35_PIN(14, PA14, 0x84, 0x18,
+		MA35_MUX(0x0, "GPA14"),
+		MA35_MUX(0x2, "UART7_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x6, "NAND_nWP"),
+		MA35_MUX(0x7, "EBI_AD14"),
+		MA35_MUX(0x9, "EBI_ADR14")),
+	MA35_PIN(15, PA15, 0x84, 0x1c,
+		MA35_MUX(0x0, "GPA15"),
+		MA35_MUX(0x1, "EPWM0_CH2"),
+		MA35_MUX(0x2, "UART9_nCTS"),
+		MA35_MUX(0x3, "UART6_RXD"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x5, "CAN2_RXD"),
+		MA35_MUX(0x7, "EBI_ALE"),
+		MA35_MUX(0x9, "QEI0_A"),
+		MA35_MUX(0xb, "TM1"),
+		MA35_MUX(0xe, "RGMII0_PPS"),
+		MA35_MUX(0xf, "RMII0_PPS")),
+	MA35_PIN(16, PB0, 0x88, 0x0,
+		MA35_MUX(0x0, "GPB0"),
+		MA35_MUX(0x8, "EADC0_CH0")),
+	MA35_PIN(17, PB1, 0x88, 0x4,
+		MA35_MUX(0x0, "GPB1"),
+		MA35_MUX(0x8, "EADC0_CH1")),
+	MA35_PIN(18, PB2, 0x88, 0x8,
+		MA35_MUX(0x0, "GPB2"),
+		MA35_MUX(0x8, "EADC0_CH2")),
+	MA35_PIN(19, PB3, 0x88, 0xc,
+		MA35_MUX(0x0, "GPB3"),
+		MA35_MUX(0x8, "EADC0_CH3")),
+	MA35_PIN(20, PB4, 0x88, 0x10,
+		MA35_MUX(0x0, "GPB4"),
+		MA35_MUX(0x8, "EADC0_CH4")),
+	MA35_PIN(21, PB5, 0x88, 0x14,
+		MA35_MUX(0x0, "GPB5"),
+		MA35_MUX(0x8, "EADC0_CH5")),
+	MA35_PIN(22, PB6, 0x88, 0x18,
+		MA35_MUX(0x0, "GPB6"),
+		MA35_MUX(0x8, "EADC0_CH6")),
+	MA35_PIN(23, PB7, 0x88, 0x1c,
+		MA35_MUX(0x0, "GPB7"),
+		MA35_MUX(0x8, "EADC0_CH7")),
+	MA35_PIN(24, PB8, 0x8c, 0x0,
+		MA35_MUX(0x0, "GPB8"),
+		MA35_MUX(0x1, "EPWM2_BRAKE0"),
+		MA35_MUX(0x2, "UART2_nCTS"),
+		MA35_MUX(0x3, "UART1_RXD"),
+		MA35_MUX(0x4, "I2C2_SDA"),
+		MA35_MUX(0x5, "SPI0_SS1"),
+		MA35_MUX(0x6, "SPI0_I2SMCLK"),
+		MA35_MUX(0x8, "ADC0_CH0"),
+		MA35_MUX(0x9, "EBI_nCS0"),
+		MA35_MUX(0xb, "TM4"),
+		MA35_MUX(0xe, "QEI2_INDEX"),
+		MA35_MUX(0xf, "KPI_ROW6")),
+	MA35_PIN(25, PB9, 0x8c, 0x4,
+		MA35_MUX(0x0, "GPB9"),
+		MA35_MUX(0x1, "EPWM2_CH4"),
+		MA35_MUX(0x2, "UART2_nRTS"),
+		MA35_MUX(0x3, "UART1_TXD"),
+		MA35_MUX(0x4, "I2C2_SCL"),
+		MA35_MUX(0x5, "SPI0_CLK"),
+		MA35_MUX(0x6, "I2S0_MCLK"),
+		MA35_MUX(0x7, "CCAP1_HSYNC"),
+		MA35_MUX(0x8, "ADC0_CH1"),
+		MA35_MUX(0x9, "EBI_ALE"),
+		MA35_MUX(0xa, "EBI_AD13"),
+		MA35_MUX(0xb, "TM0_EXT"),
+		MA35_MUX(0xc, "I2S1_MCLK"),
+		MA35_MUX(0xd, "SC0_nCD"),
+		MA35_MUX(0xe, "QEI2_A"),
+		MA35_MUX(0xf, "KPI_ROW7")),
+	MA35_PIN(26, PB10, 0x8c, 0x8,
+		MA35_MUX(0x0, "GPB10"),
+		MA35_MUX(0x1, "EPWM2_CH5"),
+		MA35_MUX(0x2, "UART2_RXD"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x5, "SPI0_MOSI"),
+		MA35_MUX(0x6, "EBI_MCLK"),
+		MA35_MUX(0x7, "CCAP1_VSYNC"),
+		MA35_MUX(0x8, "ADC0_CH2"),
+		MA35_MUX(0x9, "EBI_ADR15"),
+		MA35_MUX(0xa, "EBI_AD14"),
+		MA35_MUX(0xb, "TM5"),
+		MA35_MUX(0xc, "I2C1_SDA"),
+		MA35_MUX(0xd, "INT1"),
+		MA35_MUX(0xe, "QEI2_B")),
+	MA35_PIN(27, PB11, 0x8c, 0xc,
+		MA35_MUX(0x0, "GPB11"),
+		MA35_MUX(0x1, "EPWM2_BRAKE1"),
+		MA35_MUX(0x2, "UART2_TXD"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x5, "SPI0_MISO"),
+		MA35_MUX(0x6, "I2S1_MCLK"),
+		MA35_MUX(0x7, "CCAP1_SFIELD"),
+		MA35_MUX(0x8, "ADC0_CH3"),
+		MA35_MUX(0x9, "EBI_nCS2"),
+		MA35_MUX(0xa, "EBI_ALE"),
+		MA35_MUX(0xb, "TM5_EXT"),
+		MA35_MUX(0xc, "I2C1_SCL"),
+		MA35_MUX(0xd, "INT2"),
+		MA35_MUX(0xe, "QEI2_INDEX")),
+	MA35_PIN(28, PB12, 0x8c, 0x10,
+		MA35_MUX(0x0, "GPB12"),
+		MA35_MUX(0x1, "EPWM2_CH0"),
+		MA35_MUX(0x2, "UART4_nCTS"),
+		MA35_MUX(0x3, "UART3_RXD"),
+		MA35_MUX(0x4, "I2C3_SDA"),
+		MA35_MUX(0x5, "CAN2_RXD"),
+		MA35_MUX(0x6, "I2S1_LRCK"),
+		MA35_MUX(0x8, "ADC0_CH4"),
+		MA35_MUX(0x9, "EBI_ADR16"),
+		MA35_MUX(0xe, "ECAP2_IC0")),
+	MA35_PIN(29, PB13, 0x8c, 0x14,
+		MA35_MUX(0x0, "GPB13"),
+		MA35_MUX(0x1, "EPWM2_CH1"),
+		MA35_MUX(0x2, "UART4_nRTS"),
+		MA35_MUX(0x3, "UART3_TXD"),
+		MA35_MUX(0x4, "I2C3_SCL"),
+		MA35_MUX(0x5, "CAN2_TXD"),
+		MA35_MUX(0x6, "I2S1_BCLK"),
+		MA35_MUX(0x8, "ADC0_CH5"),
+		MA35_MUX(0x9, "EBI_ADR17"),
+		MA35_MUX(0xe, "ECAP2_IC1")),
+	MA35_PIN(30, PB14, 0x8c, 0x18,
+		MA35_MUX(0x0, "GPB14"),
+		MA35_MUX(0x1, "EPWM2_CH2"),
+		MA35_MUX(0x2, "UART4_RXD"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x5, "I2C4_SDA"),
+		MA35_MUX(0x6, "I2S1_DI"),
+		MA35_MUX(0x8, "ADC0_CH6"),
+		MA35_MUX(0x9, "EBI_ADR18"),
+		MA35_MUX(0xe, "ECAP2_IC2")),
+	MA35_PIN(31, PB15, 0x8c, 0x1c,
+		MA35_MUX(0x0, "GPB15"),
+		MA35_MUX(0x1, "EPWM2_CH3"),
+		MA35_MUX(0x2, "UART4_TXD"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x5, "I2C4_SCL"),
+		MA35_MUX(0x6, "I2S1_DO"),
+		MA35_MUX(0x8, "ADC0_CH7"),
+		MA35_MUX(0x9, "EBI_ADR19")),
+	MA35_PIN(32, PC0, 0x90, 0x0,
+		MA35_MUX(0x0, "GPC0"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x6, "SD0_CMD/eMMC0_CMD")),
+	MA35_PIN(33, PC1, 0x90, 0x4,
+		MA35_MUX(0x0, "GPC1"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x6, "SD0_CLK/eMMC0_CLK")),
+	MA35_PIN(34, PC2, 0x90, 0x8,
+		MA35_MUX(0x0, "GPC2"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")),
+	MA35_PIN(35, PC3, 0x90, 0xc,
+		MA35_MUX(0x0, "GPC3"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")),
+	MA35_PIN(36, PC4, 0x90, 0x10,
+		MA35_MUX(0x0, "GPC4"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x6, "SD0_DAT2/eMMC0_DAT2")),
+	MA35_PIN(37, PC5, 0x90, 0x14,
+		MA35_MUX(0x0, "GPC5"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x6, "SD0_DAT3/eMMC0_DAT3")),
+	MA35_PIN(38, PC6, 0x90, 0x18,
+		MA35_MUX(0x0, "GPC6"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x6, "SD0_nCD")),
+	MA35_PIN(39, PC7, 0x90, 0x1c,
+		MA35_MUX(0x0, "GPC7"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x6, "SD0_WP")),
+	MA35_PIN(40, PC12, 0x94, 0x10,
+		MA35_MUX(0x0, "GPC12"),
+		MA35_MUX(0x2, "UART12_nCTS"),
+		MA35_MUX(0x3, "UART11_RXD"),
+		MA35_MUX(0x6, "LCM_DATA16")),
+	MA35_PIN(41, PC13, 0x94, 0x14,
+		MA35_MUX(0x0, "GPC13"),
+		MA35_MUX(0x2, "UART12_nRTS"),
+		MA35_MUX(0x3, "UART11_TXD"),
+		MA35_MUX(0x6, "LCM_DATA17")),
+	MA35_PIN(42, PC14, 0x94, 0x18,
+		MA35_MUX(0x0, "GPC14"),
+		MA35_MUX(0x2, "UART12_RXD"),
+		MA35_MUX(0x6, "LCM_DATA18")),
+	MA35_PIN(43, PC15, 0x94, 0x1c,
+		MA35_MUX(0x0, "GPC15"),
+		MA35_MUX(0x2, "UART12_TXD"),
+		MA35_MUX(0x6, "LCM_DATA19"),
+		MA35_MUX(0x7, "LCM_MPU_TE"),
+		MA35_MUX(0x8, "LCM_MPU_VSYNC")),
+	MA35_PIN(44, PD0, 0x98, 0x0,
+		MA35_MUX(0x0, "GPD0"),
+		MA35_MUX(0x2, "UART3_nCTS"),
+		MA35_MUX(0x3, "UART4_RXD"),
+		MA35_MUX(0x5, "QSPI0_SS0")),
+	MA35_PIN(45, PD1, 0x98, 0x4,
+		MA35_MUX(0x0, "GPD1"),
+		MA35_MUX(0x2, "UART3_nRTS"),
+		MA35_MUX(0x3, "UART4_TXD"),
+		MA35_MUX(0x5, "QSPI0_CLK")),
+	MA35_PIN(46, PD2, 0x98, 0x8,
+		MA35_MUX(0x0, "GPD2"),
+		MA35_MUX(0x2, "UART3_RXD"),
+		MA35_MUX(0x5, "QSPI0_MOSI0")),
+	MA35_PIN(47, PD3, 0x98, 0xc,
+		MA35_MUX(0x0, "GPD3"),
+		MA35_MUX(0x2, "UART3_TXD"),
+		MA35_MUX(0x5, "QSPI0_MISO0")),
+	MA35_PIN(48, PD4, 0x98, 0x10,
+		MA35_MUX(0x0, "GPD4"),
+		MA35_MUX(0x2, "UART1_nCTS"),
+		MA35_MUX(0x3, "UART2_RXD"),
+		MA35_MUX(0x4, "I2C2_SDA"),
+		MA35_MUX(0x5, "QSPI0_MOSI1")),
+	MA35_PIN(49, PD5, 0x98, 0x14,
+		MA35_MUX(0x0, "GPD5"),
+		MA35_MUX(0x2, "UART1_nRTS"),
+		MA35_MUX(0x3, "UART2_TXD"),
+		MA35_MUX(0x4, "I2C2_SCL"),
+		MA35_MUX(0x5, "QSPI0_MISO1")),
+	MA35_PIN(50, PD6, 0x98, 0x18,
+		MA35_MUX(0x0, "GPD6"),
+		MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+		MA35_MUX(0x2, "UART1_RXD"),
+		MA35_MUX(0x5, "QSPI1_MOSI1"),
+		MA35_MUX(0x6, "I2C0_SDA"),
+		MA35_MUX(0x7, "I2S0_MCLK"),
+		MA35_MUX(0x8, "EPWM0_CH0"),
+		MA35_MUX(0x9, "EBI_AD5"),
+		MA35_MUX(0xa, "SPI3_SS1"),
+		MA35_MUX(0xb, "TRACE_CLK")),
+	MA35_PIN(51, PD7, 0x98, 0x1c,
+		MA35_MUX(0x0, "GPD7"),
+		MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+		MA35_MUX(0x2, "UART1_TXD"),
+		MA35_MUX(0x5, "QSPI1_MISO1"),
+		MA35_MUX(0x6, "I2C0_SCL"),
+		MA35_MUX(0x7, "I2S1_MCLK"),
+		MA35_MUX(0x8, "EPWM0_CH1"),
+		MA35_MUX(0x9, "EBI_AD6"),
+		MA35_MUX(0xa, "SC1_nCD"),
+		MA35_MUX(0xb, "EADC0_ST")),
+	MA35_PIN(52, PD8, 0x9c, 0x0,
+		MA35_MUX(0x0, "GPD8"),
+		MA35_MUX(0x1, "EPWM0_BRAKE0"),
+		MA35_MUX(0x2, "UART16_nCTS"),
+		MA35_MUX(0x3, "UART15_RXD"),
+		MA35_MUX(0x5, "QSPI1_SS0"),
+		MA35_MUX(0x7, "I2S1_LRCK"),
+		MA35_MUX(0x8, "EPWM0_CH2"),
+		MA35_MUX(0x9, "EBI_AD7"),
+		MA35_MUX(0xa, "SC1_CLK"),
+		MA35_MUX(0xb, "TM0")),
+	MA35_PIN(53, PD9, 0x9c, 0x4,
+		MA35_MUX(0x0, "GPD9"),
+		MA35_MUX(0x1, "EPWM0_BRAKE1"),
+		MA35_MUX(0x2, "UART16_nRTS"),
+		MA35_MUX(0x3, "UART15_TXD"),
+		MA35_MUX(0x5, "QSPI1_CLK"),
+		MA35_MUX(0x7, "I2S1_BCLK"),
+		MA35_MUX(0x8, "EPWM0_CH3"),
+		MA35_MUX(0x9, "EBI_AD8"),
+		MA35_MUX(0xa, "SC1_DAT"),
+		MA35_MUX(0xb, "TM0_EXT")),
+	MA35_PIN(54, PD10, 0x9c, 0x8,
+		MA35_MUX(0x0, "GPD10"),
+		MA35_MUX(0x1, "EPWM1_BRAKE0"),
+		MA35_MUX(0x2, "UART16_RXD"),
+		MA35_MUX(0x5, "QSPI1_MOSI0"),
+		MA35_MUX(0x7, "I2S1_DI"),
+		MA35_MUX(0x8, "EPWM0_CH4"),
+		MA35_MUX(0x9, "EBI_AD9"),
+		MA35_MUX(0xa, "SC1_RST"),
+		MA35_MUX(0xb, "TM2")),
+	MA35_PIN(55, PD11, 0x9c, 0xc,
+		MA35_MUX(0x0, "GPD11"),
+		MA35_MUX(0x1, "EPWM1_BRAKE1"),
+		MA35_MUX(0x2, "UART16_TXD"),
+		MA35_MUX(0x5, "QSPI1_MISO0"),
+		MA35_MUX(0x7, "I2S1_DO"),
+		MA35_MUX(0x8, "EPWM0_CH5"),
+		MA35_MUX(0x9, "EBI_AD10"),
+		MA35_MUX(0xa, "SC1_PWR"),
+		MA35_MUX(0xb, "TM2_EXT")),
+	MA35_PIN(56, PD12, 0x9c, 0x10,
+		MA35_MUX(0x0, "GPD12"),
+		MA35_MUX(0x1, "EPWM0_BRAKE0"),
+		MA35_MUX(0x2, "UART11_TXD"),
+		MA35_MUX(0x3, "UART10_RXD"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x6, "TRACE_DATA0"),
+		MA35_MUX(0x7, "EBI_nCS1"),
+		MA35_MUX(0x8, "EBI_AD4"),
+		MA35_MUX(0x9, "QEI0_INDEX"),
+		MA35_MUX(0xb, "TM5"),
+		MA35_MUX(0xc, "I2S1_LRCK"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(57, PD13, 0x9c, 0x14,
+		MA35_MUX(0x0, "GPD13"),
+		MA35_MUX(0x1, "EPWM0_BRAKE1"),
+		MA35_MUX(0x2, "UART11_RXD"),
+		MA35_MUX(0x3, "UART10_TXD"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x6, "TRACE_DATA1"),
+		MA35_MUX(0x7, "EBI_nCS2"),
+		MA35_MUX(0x8, "EBI_AD5"),
+		MA35_MUX(0x9, "ECAP0_IC0"),
+		MA35_MUX(0xb, "TM5_EXT"),
+		MA35_MUX(0xc, "I2S1_BCLK")),
+	MA35_PIN(58, PD14, 0x9c, 0x18,
+		MA35_MUX(0x0, "GPD14"),
+		MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+		MA35_MUX(0x2, "UART11_nCTS"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x6, "TRACE_DATA2"),
+		MA35_MUX(0x7, "EBI_MCLK"),
+		MA35_MUX(0x8, "EBI_AD6"),
+		MA35_MUX(0x9, "ECAP0_IC1"),
+		MA35_MUX(0xb, "TM6"),
+		MA35_MUX(0xc, "I2S1_DI"),
+		MA35_MUX(0xd, "INT3")),
+	MA35_PIN(59, PD15, 0x9c, 0x1c,
+		MA35_MUX(0x0, "GPD15"),
+		MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+		MA35_MUX(0x2, "UART11_nRTS"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x6, "TRACE_DATA3"),
+		MA35_MUX(0x7, "EBI_ALE"),
+		MA35_MUX(0x8, "EBI_AD7"),
+		MA35_MUX(0x9, "ECAP0_IC2"),
+		MA35_MUX(0xb, "TM6_EXT"),
+		MA35_MUX(0xc, "I2S1_DO")),
+	MA35_PIN(60, PE0, 0xa0, 0x0,
+		MA35_MUX(0x0, "GPE0"),
+		MA35_MUX(0x2, "UART9_nCTS"),
+		MA35_MUX(0x3, "UART8_RXD"),
+		MA35_MUX(0x7, "CCAP1_DATA0"),
+		MA35_MUX(0x8, "RGMII0_MDC"),
+		MA35_MUX(0x9, "RMII0_MDC")),
+	MA35_PIN(61, PE1, 0xa0, 0x4,
+		MA35_MUX(0x0, "GPE1"),
+		MA35_MUX(0x2, "UART9_nRTS"),
+		MA35_MUX(0x3, "UART8_TXD"),
+		MA35_MUX(0x7, "CCAP1_DATA1"),
+		MA35_MUX(0x8, "RGMII0_MDIO"),
+		MA35_MUX(0x9, "RMII0_MDIO")),
+	MA35_PIN(62, PE2, 0xa0, 0x8,
+		MA35_MUX(0x0, "GPE2"),
+		MA35_MUX(0x2, "UART9_RXD"),
+		MA35_MUX(0x7, "CCAP1_DATA2"),
+		MA35_MUX(0x8, "RGMII0_TXCTL"),
+		MA35_MUX(0x9, "RMII0_TXEN")),
+	MA35_PIN(63, PE3, 0xa0, 0xc,
+		MA35_MUX(0x0, "GPE3"),
+		MA35_MUX(0x2, "UART9_TXD"),
+		MA35_MUX(0x7, "CCAP1_DATA3"),
+		MA35_MUX(0x8, "RGMII0_TXD0"),
+		MA35_MUX(0x9, "RMII0_TXD0")),
+	MA35_PIN(64, PE4, 0xa0, 0x10,
+		MA35_MUX(0x0, "GPE4"),
+		MA35_MUX(0x2, "UART4_nCTS"),
+		MA35_MUX(0x3, "UART3_RXD"),
+		MA35_MUX(0x7, "CCAP1_DATA4"),
+		MA35_MUX(0x8, "RGMII0_TXD1"),
+		MA35_MUX(0x9, "RMII0_TXD1")),
+	MA35_PIN(65, PE5, 0xa0, 0x14,
+		MA35_MUX(0x0, "GPE5"),
+		MA35_MUX(0x2, "UART4_nRTS"),
+		MA35_MUX(0x3, "UART3_TXD"),
+		MA35_MUX(0x7, "CCAP1_DATA5"),
+		MA35_MUX(0x8, "RGMII0_RXCLK"),
+		MA35_MUX(0x9, "RMII0_REFCLK")),
+	MA35_PIN(66, PE6, 0xa0, 0x18,
+		MA35_MUX(0x0, "GPE6"),
+		MA35_MUX(0x2, "UART4_RXD"),
+		MA35_MUX(0x7, "CCAP1_DATA6"),
+		MA35_MUX(0x8, "RGMII0_RXCTL"),
+		MA35_MUX(0x9, "RMII0_CRSDV")),
+	MA35_PIN(67, PE7, 0xa0, 0x1c,
+		MA35_MUX(0x0, "GPE7"),
+		MA35_MUX(0x2, "UART4_TXD"),
+		MA35_MUX(0x7, "CCAP1_DATA7"),
+		MA35_MUX(0x8, "RGMII0_RXD0"),
+		MA35_MUX(0x9, "RMII0_RXD0")),
+	MA35_PIN(68, PE8, 0xa4, 0x0,
+		MA35_MUX(0x0, "GPE8"),
+		MA35_MUX(0x2, "UART13_nCTS"),
+		MA35_MUX(0x3, "UART12_RXD"),
+		MA35_MUX(0x7, "CCAP1_SCLK"),
+		MA35_MUX(0x8, "RGMII0_RXD1"),
+		MA35_MUX(0x9, "RMII0_RXD1")),
+	MA35_PIN(69, PE9, 0xa4, 0x4,
+		MA35_MUX(0x0, "GPE9"),
+		MA35_MUX(0x2, "UART13_nRTS"),
+		MA35_MUX(0x3, "UART12_TXD"),
+		MA35_MUX(0x7, "CCAP1_PIXCLK"),
+		MA35_MUX(0x8, "RGMII0_RXD2"),
+		MA35_MUX(0x9, "RMII0_RXERR")),
+	MA35_PIN(70, PE10, 0xa4, 0x8,
+		MA35_MUX(0x0, "GPE10"),
+		MA35_MUX(0x2, "UART15_nCTS"),
+		MA35_MUX(0x3, "UART14_RXD"),
+		MA35_MUX(0x5, "SPI1_SS0"),
+		MA35_MUX(0x7, "CCAP1_HSYNC"),
+		MA35_MUX(0x8, "RGMII0_RXD3")),
+	MA35_PIN(71, PE11, 0xa4, 0xc,
+		MA35_MUX(0x0, "GPE11"),
+		MA35_MUX(0x2, "UART15_nRTS"),
+		MA35_MUX(0x3, "UART14_TXD"),
+		MA35_MUX(0x5, "SPI1_CLK"),
+		MA35_MUX(0x7, "CCAP1_VSYNC"),
+		MA35_MUX(0x8, "RGMII0_TXCLK")),
+	MA35_PIN(72, PE12, 0xa4, 0x10,
+		MA35_MUX(0x0, "GPE12"),
+		MA35_MUX(0x2, "UART15_RXD"),
+		MA35_MUX(0x5, "SPI1_MOSI"),
+		MA35_MUX(0x7, "CCAP1_DATA8"),
+		MA35_MUX(0x8, "RGMII0_TXD2")),
+	MA35_PIN(73, PE13, 0xa4, 0x14,
+		MA35_MUX(0x0, "GPE13"),
+		MA35_MUX(0x2, "UART15_TXD"),
+		MA35_MUX(0x5, "SPI1_MISO"),
+		MA35_MUX(0x7, "CCAP1_DATA9"),
+		MA35_MUX(0x8, "RGMII0_TXD3")),
+	MA35_PIN(74, PE14, 0xa4, 0x18,
+		MA35_MUX(0x0, "GPE14"),
+		MA35_MUX(0x1, "UART0_TXD")),
+	MA35_PIN(75, PE15, 0xa4, 0x1c,
+		MA35_MUX(0x0, "GPE15"),
+		MA35_MUX(0x1, "UART0_RXD")),
+	MA35_PIN(76, PF0, 0xa8, 0x0,
+		MA35_MUX(0x0, "GPF0"),
+		MA35_MUX(0x2, "UART2_nCTS"),
+		MA35_MUX(0x3, "UART1_RXD"),
+		MA35_MUX(0x6, "RGMII0_RXD3"),
+		MA35_MUX(0x8, "RGMII1_MDC"),
+		MA35_MUX(0x9, "RMII1_MDC"),
+		MA35_MUX(0xe, "KPI_COL0")),
+	MA35_PIN(77, PF1, 0xa8, 0x4,
+		MA35_MUX(0x0, "GPF1"),
+		MA35_MUX(0x2, "UART2_nRTS"),
+		MA35_MUX(0x3, "UART1_TXD"),
+		MA35_MUX(0x6, "RGMII0_TXCLK"),
+		MA35_MUX(0x8, "RGMII1_MDIO"),
+		MA35_MUX(0x9, "RMII1_MDIO"),
+		MA35_MUX(0xe, "KPI_COL1")),
+	MA35_PIN(78, PF2, 0xa8, 0x8,
+		MA35_MUX(0x0, "GPF2"),
+		MA35_MUX(0x2, "UART2_RXD"),
+		MA35_MUX(0x6, "RGMII0_TXD2"),
+		MA35_MUX(0x8, "RGMII1_TXCTL"),
+		MA35_MUX(0x9, "RMII1_TXEN"),
+		MA35_MUX(0xe, "KPI_COL2")),
+	MA35_PIN(79, PF3, 0xa8, 0xc,
+		MA35_MUX(0x0, "GPF3"),
+		MA35_MUX(0x2, "UART2_TXD"),
+		MA35_MUX(0x6, "RGMII0_TXD3"),
+		MA35_MUX(0x8, "RGMII1_TXD0"),
+		MA35_MUX(0x9, "RMII1_TXD0"),
+		MA35_MUX(0xe, "KPI_COL3")),
+	MA35_PIN(80, PF4, 0xa8, 0x10,
+		MA35_MUX(0x0, "GPF4"),
+		MA35_MUX(0x2, "UART11_nCTS"),
+		MA35_MUX(0x3, "UART10_RXD"),
+		MA35_MUX(0x4, "I2S0_LRCK"),
+		MA35_MUX(0x5, "SPI1_SS0"),
+		MA35_MUX(0x8, "RGMII1_TXD1"),
+		MA35_MUX(0x9, "RMII1_TXD1"),
+		MA35_MUX(0xd, "CAN2_RXD"),
+		MA35_MUX(0xe, "KPI_ROW0")),
+	MA35_PIN(81, PF5, 0xa8, 0x14,
+		MA35_MUX(0x0, "GPF5"),
+		MA35_MUX(0x2, "UART11_nRTS"),
+		MA35_MUX(0x3, "UART10_TXD"),
+		MA35_MUX(0x4, "I2S0_BCLK"),
+		MA35_MUX(0x5, "SPI1_CLK"),
+		MA35_MUX(0x8, "RGMII1_RXCLK"),
+		MA35_MUX(0x9, "RMII1_REFCLK"),
+		MA35_MUX(0xd, "CAN2_TXD"),
+		MA35_MUX(0xe, "KPI_ROW1")),
+	MA35_PIN(82, PF6, 0xa8, 0x18,
+		MA35_MUX(0x0, "GPF6"),
+		MA35_MUX(0x2, "UART11_RXD"),
+		MA35_MUX(0x4, "I2S0_DI"),
+		MA35_MUX(0x5, "SPI1_MOSI"),
+		MA35_MUX(0x8, "RGMII1_RXCTL"),
+		MA35_MUX(0x9, "RMII1_CRSDV"),
+		MA35_MUX(0xa, "I2C4_SDA"),
+		MA35_MUX(0xd, "SC0_CLK"),
+		MA35_MUX(0xe, "KPI_ROW2")),
+	MA35_PIN(83, PF7, 0xa8, 0x1c,
+		MA35_MUX(0x0, "GPF7"),
+		MA35_MUX(0x2, "UART11_TXD"),
+		MA35_MUX(0x4, "I2S0_DO"),
+		MA35_MUX(0x5, "SPI1_MISO"),
+		MA35_MUX(0x8, "RGMII1_RXD0"),
+		MA35_MUX(0x9, "RMII1_RXD0"),
+		MA35_MUX(0xa, "I2C4_SCL"),
+		MA35_MUX(0xd, "SC0_DAT"),
+		MA35_MUX(0xe, "KPI_ROW3")),
+	MA35_PIN(84, PF8, 0xac, 0x0,
+		MA35_MUX(0x0, "GPF8"),
+		MA35_MUX(0x2, "UART13_RXD"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x5, "SPI0_SS0"),
+		MA35_MUX(0x8, "RGMII1_RXD1"),
+		MA35_MUX(0x9, "RMII1_RXD1"),
+		MA35_MUX(0xd, "SC0_RST"),
+		MA35_MUX(0xe, "KPI_COL4")),
+	MA35_PIN(85, PF9, 0xac, 0x4,
+		MA35_MUX(0x0, "GPF9"),
+		MA35_MUX(0x2, "UART13_TXD"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x5, "SPI0_SS1"),
+		MA35_MUX(0x8, "RGMII1_RXD2"),
+		MA35_MUX(0x9, "RMII1_RXERR"),
+		MA35_MUX(0xd, "SC0_PWR"),
+		MA35_MUX(0xe, "KPI_COL5")),
+	MA35_PIN(86, PF10, 0xac, 0x8,
+		MA35_MUX(0x0, "GPF10"),
+		MA35_MUX(0x2, "UART13_nCTS"),
+		MA35_MUX(0x5, "I2S0_LRCK"),
+		MA35_MUX(0x6, "SPI1_SS0"),
+		MA35_MUX(0x8, "RGMII1_RXD3"),
+		MA35_MUX(0x9, "SC0_CLK"),
+		MA35_MUX(0xe, "KPI_COL6")),
+	MA35_PIN(87, PF11, 0xac, 0xc,
+		MA35_MUX(0x0, "GPF11"),
+		MA35_MUX(0x2, "UART13_nRTS"),
+		MA35_MUX(0x5, "I2S0_BCLK"),
+		MA35_MUX(0x6, "SPI1_CLK"),
+		MA35_MUX(0x8, "RGMII1_TXCLK"),
+		MA35_MUX(0x9, "SC0_DAT"),
+		MA35_MUX(0xe, "KPI_COL7")),
+	MA35_PIN(88, PF12, 0xac, 0x10,
+		MA35_MUX(0x0, "GPF12"),
+		MA35_MUX(0x5, "I2S0_DI"),
+		MA35_MUX(0x6, "SPI1_MOSI"),
+		MA35_MUX(0x8, "RGMII1_TXD2"),
+		MA35_MUX(0x9, "SC0_RST"),
+		MA35_MUX(0xe, "KPI_ROW4")),
+	MA35_PIN(89, PF13, 0xac, 0x14,
+		MA35_MUX(0x0, "GPF13"),
+		MA35_MUX(0x5, "I2S0_DO"),
+		MA35_MUX(0x6, "SPI1_MISO"),
+		MA35_MUX(0x8, "RGMII1_TXD3"),
+		MA35_MUX(0x9, "SC0_PWR"),
+		MA35_MUX(0xe, "KPI_ROW5")),
+	MA35_PIN(90, PF14, 0xac, 0x18,
+		MA35_MUX(0x0, "GPF14"),
+		MA35_MUX(0x1, "EPWM2_BRAKE0"),
+		MA35_MUX(0x2, "EADC0_ST"),
+		MA35_MUX(0x3, "RGMII1_PPS"),
+		MA35_MUX(0x4, "RMII1_PPS"),
+		MA35_MUX(0x5, "SPI0_I2SMCLK"),
+		MA35_MUX(0x6, "SPI1_I2SMCLK"),
+		MA35_MUX(0x7, "CCAP1_SFIELD"),
+		MA35_MUX(0x8, "RGMII0_PPS"),
+		MA35_MUX(0x9, "RMII0_PPS"),
+		MA35_MUX(0xb, "TM0"),
+		MA35_MUX(0xc, "INT0"),
+		MA35_MUX(0xd, "SPI1_SS1"),
+		MA35_MUX(0xe, "QEI2_INDEX"),
+		MA35_MUX(0xf, "I2S0_MCLK")),
+	MA35_PIN(91, PF15, 0xac, 0x1c,
+		MA35_MUX(0x0, "GPF15"),
+		MA35_MUX(0x1, "HSUSB0_VBUSVLD")),
+	MA35_PIN(92, PG0, 0xb0, 0x0,
+		MA35_MUX(0x0, "GPG0"),
+		MA35_MUX(0x1, "EPWM0_CH0"),
+		MA35_MUX(0x2, "UART7_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "SPI0_SS0"),
+		MA35_MUX(0x6, "EADC0_ST"),
+		MA35_MUX(0x7, "EBI_AD15"),
+		MA35_MUX(0x9, "I2S1_MCLK"),
+		MA35_MUX(0xa, "QEI0_INDEX"),
+		MA35_MUX(0xb, "TM1"),
+		MA35_MUX(0xc, "CLKO"),
+		MA35_MUX(0xd, "INT0"),
+		MA35_MUX(0xf, "EBI_ADR15")),
+	MA35_PIN(93, PG1, 0xb0, 0x4,
+		MA35_MUX(0x0, "GPG1"),
+		MA35_MUX(0x1, "EPWM0_CH3"),
+		MA35_MUX(0x2, "UART9_nRTS"),
+		MA35_MUX(0x3, "UART6_TXD"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x5, "CAN2_TXD"),
+		MA35_MUX(0x7, "EBI_nCS0"),
+		MA35_MUX(0x9, "QEI0_B"),
+		MA35_MUX(0xb, "TM1_EXT"),
+		MA35_MUX(0xe, "RGMII1_PPS"),
+		MA35_MUX(0xf, "RMII1_PPS")),
+	MA35_PIN(94, PG2, 0xb0, 0x8,
+		MA35_MUX(0x0, "GPG2"),
+		MA35_MUX(0x1, "EPWM0_CH4"),
+		MA35_MUX(0x2, "UART9_RXD"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x5, "SPI0_SS1"),
+		MA35_MUX(0x7, "EBI_ADR16"),
+		MA35_MUX(0x8, "EBI_nCS2"),
+		MA35_MUX(0xa, "QEI0_A"),
+		MA35_MUX(0xb, "TM3"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(95, PG3, 0xb0, 0xc,
+		MA35_MUX(0x0, "GPG3"),
+		MA35_MUX(0x1, "EPWM0_CH5"),
+		MA35_MUX(0x2, "UART9_TXD"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x5, "SPI0_I2SMCLK"),
+		MA35_MUX(0x7, "EBI_ADR17"),
+		MA35_MUX(0x8, "EBI_nCS1"),
+		MA35_MUX(0x9, "EBI_MCLK"),
+		MA35_MUX(0xa, "QEI0_B"),
+		MA35_MUX(0xb, "TM3_EXT"),
+		MA35_MUX(0xc, "I2S1_MCLK")),
+	MA35_PIN(96, PG4, 0xb0, 0x10,
+		MA35_MUX(0x0, "GPG4"),
+		MA35_MUX(0x1, "EPWM1_CH0"),
+		MA35_MUX(0x2, "UART5_nCTS"),
+		MA35_MUX(0x3, "UART6_RXD"),
+		MA35_MUX(0x5, "SPI3_SS0"),
+		MA35_MUX(0x6, "QEI1_INDEX"),
+		MA35_MUX(0x7, "EBI_ADR18"),
+		MA35_MUX(0x8, "EBI_nCS0"),
+		MA35_MUX(0x9, "I2S1_DO"),
+		MA35_MUX(0xa, "SC1_CLK"),
+		MA35_MUX(0xb, "TM4"),
+		MA35_MUX(0xd, "INT2"),
+		MA35_MUX(0xe, "ECAP1_IC2")),
+	MA35_PIN(97, PG5, 0xb0, 0x14,
+		MA35_MUX(0x0, "GPG5"),
+		MA35_MUX(0x1, "EPWM1_CH1"),
+		MA35_MUX(0x2, "UART5_nRTS"),
+		MA35_MUX(0x3, "UART6_TXD"),
+		MA35_MUX(0x5, "SPI3_CLK"),
+		MA35_MUX(0x6, "ECAP0_IC0"),
+		MA35_MUX(0x7, "EBI_ADR19"),
+		MA35_MUX(0x8, "EBI_ALE"),
+		MA35_MUX(0x9, "I2S1_DI"),
+		MA35_MUX(0xa, "SC1_DAT"),
+		MA35_MUX(0xb, "TM4_EXT")),
+	MA35_PIN(98, PG6, 0xb0, 0x18,
+		MA35_MUX(0x0, "GPG6"),
+		MA35_MUX(0x1, "EPWM1_CH2"),
+		MA35_MUX(0x2, "UART5_RXD"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x5, "SPI3_MOSI"),
+		MA35_MUX(0x6, "ECAP0_IC1"),
+		MA35_MUX(0x7, "EBI_nRD"),
+		MA35_MUX(0x9, "I2S1_BCLK"),
+		MA35_MUX(0xa, "SC1_RST"),
+		MA35_MUX(0xb, "TM7"),
+		MA35_MUX(0xd, "INT3")),
+	MA35_PIN(99, PG7, 0xb0, 0x1c,
+		MA35_MUX(0x0, "GPG7"),
+		MA35_MUX(0x1, "EPWM1_CH3"),
+		MA35_MUX(0x2, "UART5_TXD"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x5, "SPI3_MISO"),
+		MA35_MUX(0x6, "ECAP0_IC2"),
+		MA35_MUX(0x7, "EBI_nWR"),
+		MA35_MUX(0x9, "I2S1_LRCK"),
+		MA35_MUX(0xa, "SC1_PWR"),
+		MA35_MUX(0xb, "TM7_EXT")),
+	MA35_PIN(100, PG8, 0xb4, 0x0,
+		MA35_MUX(0x0, "GPG8"),
+		MA35_MUX(0x1, "EPWM1_CH4"),
+		MA35_MUX(0x2, "UART12_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x5, "SPI2_SS0"),
+		MA35_MUX(0x6, "LCM_VSYNC"),
+		MA35_MUX(0x7, "I2C3_SDA"),
+		MA35_MUX(0xc, "EBI_AD7"),
+		MA35_MUX(0xd, "EBI_nCS0")),
+	MA35_PIN(101, PG9, 0xb4, 0x4,
+		MA35_MUX(0x0, "GPG9"),
+		MA35_MUX(0x1, "EPWM1_CH5"),
+		MA35_MUX(0x2, "UART12_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "SPI2_CLK"),
+		MA35_MUX(0x6, "LCM_HSYNC"),
+		MA35_MUX(0x7, "I2C3_SCL"),
+		MA35_MUX(0xc, "EBI_AD8"),
+		MA35_MUX(0xd, "EBI_nCS1")),
+	MA35_PIN(102, PG10, 0xb4, 0x8,
+		MA35_MUX(0x0, "GPG10"),
+		MA35_MUX(0x2, "UART12_nRTS"),
+		MA35_MUX(0x3, "UART13_TXD"),
+		MA35_MUX(0x5, "SPI2_MOSI"),
+		MA35_MUX(0x6, "LCM_CLK"),
+		MA35_MUX(0xc, "EBI_AD9"),
+		MA35_MUX(0xd, "EBI_nWRH")),
+	MA35_PIN(103, PG11, 0xb4, 0xc,
+		MA35_MUX(0x0, "GPG11"),
+		MA35_MUX(0x3, "JTAG_TDO"),
+		MA35_MUX(0x5, "I2S0_MCLK"),
+		MA35_MUX(0x6, "NAND_RDY1"),
+		MA35_MUX(0x7, "EBI_nWRH"),
+		MA35_MUX(0x8, "EBI_nCS1"),
+		MA35_MUX(0xa, "EBI_AD0")),
+	MA35_PIN(104, PG12, 0xb4, 0x10,
+		MA35_MUX(0x0, "GPG12"),
+		MA35_MUX(0x3, "JTAG_TCK/SW_CLK"),
+		MA35_MUX(0x5, "I2S0_LRCK"),
+		MA35_MUX(0x7, "EBI_nWRL"),
+		MA35_MUX(0xa, "EBI_AD1")),
+	MA35_PIN(105, PG13, 0xb4, 0x14,
+		MA35_MUX(0x0, "GPG13"),
+		MA35_MUX(0x3, "JTAG_TMS/SW_DIO"),
+		MA35_MUX(0x5, "I2S0_BCLK"),
+		MA35_MUX(0x7, "EBI_MCLK"),
+		MA35_MUX(0xa, "EBI_AD2")),
+	MA35_PIN(106, PG14, 0xb4, 0x18,
+		MA35_MUX(0x0, "GPG14"),
+		MA35_MUX(0x3, "JTAG_TDI"),
+		MA35_MUX(0x5, "I2S0_DI"),
+		MA35_MUX(0x6, "NAND_nCS1"),
+		MA35_MUX(0x7, "EBI_ALE"),
+		MA35_MUX(0xa, "EBI_AD3")),
+	MA35_PIN(107, PG15, 0xb4, 0x1c,
+		MA35_MUX(0x0, "GPG15"),
+		MA35_MUX(0x3, "JTAG_nTRST"),
+		MA35_MUX(0x5, "I2S0_DO"),
+		MA35_MUX(0x7, "EBI_nCS0"),
+		MA35_MUX(0xa, "EBI_AD4")),
+	MA35_PIN(108, PH0, 0xb8, 0x0,
+		MA35_MUX(0x0, "GPH0"),
+		MA35_MUX(0x2, "UART8_nCTS"),
+		MA35_MUX(0x3, "UART7_RXD"),
+		MA35_MUX(0x6, "LCM_DATA8")),
+	MA35_PIN(109, PH1, 0xb8, 0x4,
+		MA35_MUX(0x0, "GPH1"),
+		MA35_MUX(0x2, "UART8_nRTS"),
+		MA35_MUX(0x3, "UART7_TXD"),
+		MA35_MUX(0x6, "LCM_DATA9")),
+	MA35_PIN(110, PH2, 0xb8, 0x8,
+		MA35_MUX(0x0, "GPH2"),
+		MA35_MUX(0x2, "UART8_RXD"),
+		MA35_MUX(0x6, "LCM_DATA10")),
+	MA35_PIN(111, PH3, 0xb8, 0xc,
+		MA35_MUX(0x0, "GPH3"),
+		MA35_MUX(0x2, "UART8_TXD"),
+		MA35_MUX(0x6, "LCM_DATA11")),
+	MA35_PIN(112, PH4, 0xb8, 0x10,
+		MA35_MUX(0x0, "GPH4"),
+		MA35_MUX(0x2, "UART10_nCTS"),
+		MA35_MUX(0x3, "UART9_RXD"),
+		MA35_MUX(0x6, "LCM_DATA12")),
+	MA35_PIN(113, PH5, 0xb8, 0x14,
+		MA35_MUX(0x0, "GPH5"),
+		MA35_MUX(0x2, "UART10_nRTS"),
+		MA35_MUX(0x3, "UART9_TXD"),
+		MA35_MUX(0x6, "LCM_DATA13")),
+	MA35_PIN(114, PH6, 0xb8, 0x18,
+		MA35_MUX(0x0, "GPH6"),
+		MA35_MUX(0x2, "UART10_RXD"),
+		MA35_MUX(0x6, "LCM_DATA14")),
+	MA35_PIN(115, PH7, 0xb8, 0x1c,
+		MA35_MUX(0x0, "GPH7"),
+		MA35_MUX(0x2, "UART10_TXD"),
+		MA35_MUX(0x6, "LCM_DATA15")),
+	MA35_PIN(116, PH8, 0xbc, 0x0,
+		MA35_MUX(0x0, "GPH8"),
+		MA35_MUX(0x6, "TAMPER0")),
+	MA35_PIN(117, PH9, 0xbc, 0x4,
+		MA35_MUX(0x0, "GPH9"),
+		MA35_MUX(0x4, "CLK_32KOUT"),
+		MA35_MUX(0x6, "TAMPER1")),
+	MA35_PIN(118, PH12, 0xbc, 0x10,
+		MA35_MUX(0x0, "GPH12"),
+		MA35_MUX(0x2, "UART14_nCTS"),
+		MA35_MUX(0x3, "UART13_RXD"),
+		MA35_MUX(0x6, "LCM_DATA20")),
+	MA35_PIN(119, PH13, 0xbc, 0x14,
+		MA35_MUX(0x0, "GPH13"),
+		MA35_MUX(0x2, "UART14_nRTS"),
+		MA35_MUX(0x3, "UART13_TXD"),
+		MA35_MUX(0x6, "LCM_DATA21")),
+	MA35_PIN(120, PH14, 0xbc, 0x18,
+		MA35_MUX(0x0, "GPH14"),
+		MA35_MUX(0x2, "UART14_RXD"),
+		MA35_MUX(0x6, "LCM_DATA22")),
+	MA35_PIN(121, PH15, 0xbc, 0x1c,
+		MA35_MUX(0x0, "GPH15"),
+		MA35_MUX(0x2, "UART14_TXD"),
+		MA35_MUX(0x6, "LCM_DATA23")),
+	MA35_PIN(122, PI0, 0xc0, 0x0,
+		MA35_MUX(0x0, "GPI0"),
+		MA35_MUX(0x1, "EPWM0_CH0"),
+		MA35_MUX(0x2, "UART12_nCTS"),
+		MA35_MUX(0x3, "UART11_RXD"),
+		MA35_MUX(0x4, "I2C2_SDA"),
+		MA35_MUX(0x5, "SPI3_SS0"),
+		MA35_MUX(0x7, "SC0_nCD"),
+		MA35_MUX(0x8, "EBI_ADR0"),
+		MA35_MUX(0xb, "TM0"),
+		MA35_MUX(0xc, "ECAP1_IC0")),
+	MA35_PIN(123, PI1, 0xc0, 0x4,
+		MA35_MUX(0x0, "GPI1"),
+		MA35_MUX(0x1, "EPWM0_CH1"),
+		MA35_MUX(0x2, "UART12_nRTS"),
+		MA35_MUX(0x3, "UART11_TXD"),
+		MA35_MUX(0x4, "I2C2_SCL"),
+		MA35_MUX(0x5, "SPI3_CLK"),
+		MA35_MUX(0x7, "SC0_CLK"),
+		MA35_MUX(0x8, "EBI_ADR1"),
+		MA35_MUX(0xb, "TM0_EXT"),
+		MA35_MUX(0xc, "ECAP1_IC1")),
+	MA35_PIN(124, PI2, 0xc0, 0x8,
+		MA35_MUX(0x0, "GPI2"),
+		MA35_MUX(0x1, "EPWM0_CH2"),
+		MA35_MUX(0x2, "UART12_RXD"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x5, "SPI3_MOSI"),
+		MA35_MUX(0x7, "SC0_DAT"),
+		MA35_MUX(0x8, "EBI_ADR2"),
+		MA35_MUX(0xb, "TM1"),
+		MA35_MUX(0xc, "ECAP1_IC2")),
+	MA35_PIN(125, PI3, 0xc0, 0xc,
+		MA35_MUX(0x0, "GPI3"),
+		MA35_MUX(0x1, "EPWM0_CH3"),
+		MA35_MUX(0x2, "UART12_TXD"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x5, "SPI3_MISO"),
+		MA35_MUX(0x7, "SC0_RST"),
+		MA35_MUX(0x8, "EBI_ADR3"),
+		MA35_MUX(0xb, "TM1_EXT")),
+	MA35_PIN(126, PI4, 0xc0, 0x10,
+		MA35_MUX(0x0, "GPI4"),
+		MA35_MUX(0x1, "EPWM0_CH4"),
+		MA35_MUX(0x2, "UART14_nCTS"),
+		MA35_MUX(0x3, "UART13_RXD"),
+		MA35_MUX(0x4, "I2C3_SDA"),
+		MA35_MUX(0x5, "SPI2_SS1"),
+		MA35_MUX(0x6, "I2S1_LRCK"),
+		MA35_MUX(0x8, "EBI_ADR4"),
+		MA35_MUX(0xd, "INT0")),
+	MA35_PIN(127, PI5, 0xc0, 0x14,
+		MA35_MUX(0x0, "GPI5"),
+		MA35_MUX(0x1, "EPWM0_CH5"),
+		MA35_MUX(0x2, "UART14_nRTS"),
+		MA35_MUX(0x3, "UART13_TXD"),
+		MA35_MUX(0x4, "I2C3_SCL"),
+		MA35_MUX(0x6, "I2S1_BCLK"),
+		MA35_MUX(0x8, "EBI_ADR5"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(128, PI6, 0xc0, 0x18,
+		MA35_MUX(0x0, "GPI6"),
+		MA35_MUX(0x1, "EPWM0_BRAKE0"),
+		MA35_MUX(0x2, "UART14_RXD"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x6, "I2S1_DI"),
+		MA35_MUX(0x8, "EBI_ADR6"),
+		MA35_MUX(0xc, "QEI1_INDEX"),
+		MA35_MUX(0xd, "INT2")),
+	MA35_PIN(129, PI7, 0xc0, 0x1c,
+		MA35_MUX(0x0, "GPI7"),
+		MA35_MUX(0x1, "EPWM0_BRAKE1"),
+		MA35_MUX(0x2, "UART14_TXD"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x6, "I2S1_DO"),
+		MA35_MUX(0x8, "EBI_ADR7"),
+		MA35_MUX(0xc, "ECAP0_IC0"),
+		MA35_MUX(0xd, "INT3")),
+	MA35_PIN(130, PI8, 0xc4, 0x0,
+		MA35_MUX(0x0, "GPI8"),
+		MA35_MUX(0x2, "UART4_nCTS"),
+		MA35_MUX(0x3, "UART3_RXD"),
+		MA35_MUX(0x6, "LCM_DATA0"),
+		MA35_MUX(0xc, "EBI_AD11")),
+	MA35_PIN(131, PI9, 0xc4, 0x4,
+		MA35_MUX(0x0, "GPI9"),
+		MA35_MUX(0x2, "UART4_nRTS"),
+		MA35_MUX(0x3, "UART3_TXD"),
+		MA35_MUX(0x6, "LCM_DATA1"),
+		MA35_MUX(0xc, "EBI_AD12")),
+	MA35_PIN(132, PI10, 0xc4, 0x8,
+		MA35_MUX(0x0, "GPI10"),
+		MA35_MUX(0x2, "UART4_RXD"),
+		MA35_MUX(0x6, "LCM_DATA2"),
+		MA35_MUX(0xc, "EBI_AD13")),
+	MA35_PIN(133, PI11, 0xC4, 0xc,
+		MA35_MUX(0x0, "GPI11"),
+		MA35_MUX(0x2, "UART4_TXD"),
+		MA35_MUX(0x6, "LCM_DATA3"),
+		MA35_MUX(0xc, "EBI_AD14")),
+	MA35_PIN(134, PI12, 0xc4, 0x10,
+		MA35_MUX(0x0, "GPI12"),
+		MA35_MUX(0x2, "UART6_nCTS"),
+		MA35_MUX(0x3, "UART5_RXD"),
+		MA35_MUX(0x6, "LCM_DATA4")),
+	MA35_PIN(135, PI13, 0xc4, 0x14,
+		MA35_MUX(0x0, "GPI13"),
+		MA35_MUX(0x2, "UART6_nRTS"),
+		MA35_MUX(0x3, "UART5_TXD"),
+		MA35_MUX(0x6, "LCM_DATA5")),
+	MA35_PIN(136, PI14, 0xc4, 0x18,
+		MA35_MUX(0x0, "GPI14"),
+		MA35_MUX(0x2, "UART6_RXD"),
+		MA35_MUX(0x6, "LCM_DATA6")),
+	MA35_PIN(137, PI15, 0xc4, 0x1c,
+		MA35_MUX(0x0, "GPI15"),
+		MA35_MUX(0x2, "UART6_TXD"),
+		MA35_MUX(0x6, "LCM_DATA7")),
+	MA35_PIN(138, PJ0, 0xc8, 0x0,
+		MA35_MUX(0x0, "GPJ0"),
+		MA35_MUX(0x1, "EPWM1_BRAKE0"),
+		MA35_MUX(0x2, "UART8_nCTS"),
+		MA35_MUX(0x3, "UART7_RXD"),
+		MA35_MUX(0x4, "I2C2_SDA"),
+		MA35_MUX(0x5, "SPI2_SS0"),
+		MA35_MUX(0x6, "eMMC1_DAT4"),
+		MA35_MUX(0x7, "I2S0_LRCK"),
+		MA35_MUX(0x8, "SC0_CLK"),
+		MA35_MUX(0x9, "EBI_AD11"),
+		MA35_MUX(0xa, "EBI_ADR16"),
+		MA35_MUX(0xb, "EBI_nCS0"),
+		MA35_MUX(0xc, "EBI_AD7")),
+	MA35_PIN(139, PJ1, 0xc8, 0x4,
+		MA35_MUX(0x0, "GPJ1"),
+		MA35_MUX(0x1, "EPWM1_BRAKE1"),
+		MA35_MUX(0x2, "UART8_nRTS"),
+		MA35_MUX(0x3, "UART7_TXD"),
+		MA35_MUX(0x4, "I2C2_SCL"),
+		MA35_MUX(0x5, "SPI2_CLK"),
+		MA35_MUX(0x6, "eMMC1_DAT5"),
+		MA35_MUX(0x7, "I2S0_BCLK"),
+		MA35_MUX(0x8, "SC0_DAT"),
+		MA35_MUX(0x9, "EBI_AD12"),
+		MA35_MUX(0xa, "EBI_ADR17"),
+		MA35_MUX(0xb, "EBI_nCS1"),
+		MA35_MUX(0xc, "EBI_AD8")),
+	MA35_PIN(140, PJ2, 0xc8, 0x8,
+		MA35_MUX(0x0, "GPJ2"),
+		MA35_MUX(0x1, "EPWM1_CH4"),
+		MA35_MUX(0x2, "UART8_RXD"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x5, "SPI2_MOSI"),
+		MA35_MUX(0x6, "eMMC1_DAT6"),
+		MA35_MUX(0x7, "I2S0_DI"),
+		MA35_MUX(0x8, "SC0_RST"),
+		MA35_MUX(0x9, "EBI_AD13"),
+		MA35_MUX(0xa, "EBI_ADR18"),
+		MA35_MUX(0xb, "EBI_nWRH"),
+		MA35_MUX(0xc, "EBI_AD9")),
+	MA35_PIN(141, PJ3, 0xc8, 0xc,
+		MA35_MUX(0x0, "GPJ3"),
+		MA35_MUX(0x1, "EPWM1_CH5"),
+		MA35_MUX(0x2, "UART8_TXD"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x5, "SPI2_MISO"),
+		MA35_MUX(0x6, "eMMC1_DAT7"),
+		MA35_MUX(0x7, "I2S0_DO"),
+		MA35_MUX(0x8, "SC0_PWR"),
+		MA35_MUX(0x9, "EBI_AD14"),
+		MA35_MUX(0xa, "EBI_ADR19"),
+		MA35_MUX(0xb, "EBI_nWRL"),
+		MA35_MUX(0xc, "EBI_AD10")),
+	MA35_PIN(142, PJ4, 0xc8, 0x10,
+		MA35_MUX(0x0, "GPJ4"),
+		MA35_MUX(0x4, "I2C3_SDA"),
+		MA35_MUX(0x6, "SD1_WP")),
+	MA35_PIN(143, PJ5, 0xc8, 0x14,
+		MA35_MUX(0x0, "GPJ5"),
+		MA35_MUX(0x4, "I2C3_SCL"),
+		MA35_MUX(0x6, "SD1_nCD")),
+	MA35_PIN(144, PJ6, 0xc8, 0x18,
+		MA35_MUX(0x0, "GPJ6"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")),
+	MA35_PIN(145, PJ7, 0xc8, 0x1c,
+		MA35_MUX(0x0, "GPJ7"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")),
+	MA35_PIN(146, PJ8, 0xcc, 0x0,
+		MA35_MUX(0x0, "GPJ8"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")),
+	MA35_PIN(147, PJ9, 0xcc, 0x4,
+		MA35_MUX(0x0, "GPJ9"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")),
+	MA35_PIN(148, PJ10, 0xcc, 0x8,
+		MA35_MUX(0x0, "GPJ10"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")),
+	MA35_PIN(149, PJ11, 0xcc, 0xc,
+		MA35_MUX(0x0, "GPJ11"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")),
+	MA35_PIN(150, PJ12, 0xcc, 0x10,
+		MA35_MUX(0x0, "GPJ12"),
+		MA35_MUX(0x1, "EPWM1_CH2"),
+		MA35_MUX(0x2, "UART2_nCTS"),
+		MA35_MUX(0x3, "UART1_RXD"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x5, "SPI3_SS0"),
+		MA35_MUX(0x7, "SC1_CLK"),
+		MA35_MUX(0x8, "EBI_ADR12"),
+		MA35_MUX(0xb, "TM2"),
+		MA35_MUX(0xc, "QEI0_INDEX")),
+	MA35_PIN(151, PJ13, 0xcc, 0x14,
+		MA35_MUX(0x0, "GPJ13"),
+		MA35_MUX(0x1, "EPWM1_CH3"),
+		MA35_MUX(0x2, "UART2_nRTS"),
+		MA35_MUX(0x3, "UART1_TXD"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x5, "SPI3_MOSI"),
+		MA35_MUX(0x7, "SC1_DAT"),
+		MA35_MUX(0x8, "EBI_ADR13"),
+		MA35_MUX(0xb, "TM2_EXT")),
+	MA35_PIN(152, PJ14, 0xcc, 0x18,
+		MA35_MUX(0x0, "GPJ14"),
+		MA35_MUX(0x1, "EPWM1_CH4"),
+		MA35_MUX(0x2, "UART2_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x5, "SPI3_MISO"),
+		MA35_MUX(0x7, "SC1_RST"),
+		MA35_MUX(0x8, "EBI_ADR14"),
+		MA35_MUX(0xb, "TM3")),
+	MA35_PIN(153, PJ15, 0xcc, 0x1c,
+		MA35_MUX(0x0, "GPJ15"),
+		MA35_MUX(0x1, "EPWM1_CH5"),
+		MA35_MUX(0x2, "UART2_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "SPI3_CLK"),
+		MA35_MUX(0x6, "EADC0_ST"),
+		MA35_MUX(0x7, "SC1_PWR"),
+		MA35_MUX(0x8, "EBI_ADR15"),
+		MA35_MUX(0xb, "TM3_EXT"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(154, PK0, 0xd0, 0x0,
+		MA35_MUX(0x0, "GPK0"),
+		MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+		MA35_MUX(0x2, "UART16_nCTS"),
+		MA35_MUX(0x3, "UART15_RXD"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x6, "I2S1_MCLK"),
+		MA35_MUX(0x8, "EBI_ADR8"),
+		MA35_MUX(0xb, "TM7"),
+		MA35_MUX(0xc, "ECAP0_IC1")),
+	MA35_PIN(155, PK1, 0xd0, 0x4,
+		MA35_MUX(0x0, "GPK1"),
+		MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+		MA35_MUX(0x2, "UART16_nRTS"),
+		MA35_MUX(0x3, "UART15_TXD"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x6, "EADC0_ST"),
+		MA35_MUX(0x8, "EBI_ADR9"),
+		MA35_MUX(0xb, "TM7_EXT"),
+		MA35_MUX(0xc, "ECAP0_IC2")),
+	MA35_PIN(156, PK2, 0xd0, 0x8,
+		MA35_MUX(0x0, "GPK2"),
+		MA35_MUX(0x1, "EPWM1_CH0"),
+		MA35_MUX(0x2, "UART16_RXD"),
+		MA35_MUX(0x3, "CAN2_RXD"),
+		MA35_MUX(0x5, "SPI3_I2SMCLK"),
+		MA35_MUX(0x7, "SC0_PWR"),
+		MA35_MUX(0x8, "EBI_ADR10"),
+		MA35_MUX(0xc, "QEI0_A")),
+	MA35_PIN(157, PK3, 0xd0, 0xc,
+		MA35_MUX(0x0, "GPK3"),
+		MA35_MUX(0x1, "EPWM1_CH1"),
+		MA35_MUX(0x2, "UART16_TXD"),
+		MA35_MUX(0x3, "CAN2_TXD"),
+		MA35_MUX(0x5, "SPI3_SS1"),
+		MA35_MUX(0x7, "SC1_nCD"),
+		MA35_MUX(0x8, "EBI_ADR11"),
+		MA35_MUX(0xc, "QEI0_B")),
+	MA35_PIN(158, PK4, 0xd0, 0x10,
+		MA35_MUX(0x0, "GPK4"),
+		MA35_MUX(0x2, "UART12_nCTS"),
+		MA35_MUX(0x3, "UART13_RXD"),
+		MA35_MUX(0x5, "SPI2_MISO"),
+		MA35_MUX(0x6, "LCM_DEN"),
+		MA35_MUX(0xc, "EBI_AD10"),
+		MA35_MUX(0xd, "EBI_nWRL")),
+	MA35_PIN(159, PK5, 0xd0, 0x14,
+		MA35_MUX(0x0, "GPK5"),
+		MA35_MUX(0x1, "EPWM1_CH1"),
+		MA35_MUX(0x2, "UART12_nRTS"),
+		MA35_MUX(0x3, "UART13_TXD"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x5, "SPI2_CLK"),
+		MA35_MUX(0x7, "I2S1_DI"),
+		MA35_MUX(0x8, "SC0_DAT"),
+		MA35_MUX(0x9, "EADC0_ST"),
+		MA35_MUX(0xb, "TM8_EXT"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(160, PK6, 0xd0, 0x18,
+		MA35_MUX(0x0, "GPK6"),
+		MA35_MUX(0x1, "EPWM1_CH2"),
+		MA35_MUX(0x2, "UART12_RXD"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x5, "SPI2_MOSI"),
+		MA35_MUX(0x7, "I2S1_BCLK"),
+		MA35_MUX(0x8, "SC0_RST"),
+		MA35_MUX(0xb, "TM6"),
+		MA35_MUX(0xd, "INT2")),
+	MA35_PIN(161, PK7, 0xd0, 0x1c,
+		MA35_MUX(0x0, "GPK7"),
+		MA35_MUX(0x1, "EPWM1_CH3"),
+		MA35_MUX(0x2, "UART12_TXD"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x5, "SPI2_MISO"),
+		MA35_MUX(0x7, "I2S1_LRCK"),
+		MA35_MUX(0x8, "SC0_PWR"),
+		MA35_MUX(0x9, "CLKO"),
+		MA35_MUX(0xb, "TM6_EXT"),
+		MA35_MUX(0xd, "INT3")),
+	MA35_PIN(162, PK8, 0xd4, 0x0,
+		MA35_MUX(0x0, "GPK8"),
+		MA35_MUX(0x1, "EPWM1_CH0"),
+		MA35_MUX(0x4, "I2C3_SDA"),
+		MA35_MUX(0x5, "SPI3_CLK"),
+		MA35_MUX(0x7, "EADC0_ST"),
+		MA35_MUX(0x8, "EBI_AD15"),
+		MA35_MUX(0x9, "EBI_MCLK"),
+		MA35_MUX(0xa, "EBI_ADR15"),
+		MA35_MUX(0xb, "TM8"),
+		MA35_MUX(0xc, "QEI1_INDEX")),
+	MA35_PIN(163, PK9, 0xd4, 0x4,
+		MA35_MUX(0x0, "GPK9"),
+		MA35_MUX(0x4, "I2C3_SCL"),
+		MA35_MUX(0x6, "CCAP0_SCLK"),
+		MA35_MUX(0x8, "EBI_AD0"),
+		MA35_MUX(0xa, "EBI_ADR0")),
+	MA35_PIN(164, PK10, 0xd4, 0x8,
+		MA35_MUX(0x0, "GPK10"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x6, "CCAP0_PIXCLK"),
+		MA35_MUX(0x8, "EBI_AD1"),
+		MA35_MUX(0xa, "EBI_ADR1")),
+	MA35_PIN(165, PK11, 0xd4, 0xc,
+		MA35_MUX(0x0, "GPK11"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x6, "CCAP0_HSYNC"),
+		MA35_MUX(0x8, "EBI_AD2"),
+		MA35_MUX(0xa, "EBI_ADR2")),
+	MA35_PIN(166, PK12, 0xd4, 0x10,
+		MA35_MUX(0x0, "GPK12"),
+		MA35_MUX(0x1, "EPWM2_CH0"),
+		MA35_MUX(0x2, "UART1_nCTS"),
+		MA35_MUX(0x3, "UART13_RXD"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x5, "I2S0_LRCK"),
+		MA35_MUX(0x6, "SPI1_SS0"),
+		MA35_MUX(0x8, "SC0_CLK"),
+		MA35_MUX(0xb, "TM10"),
+		MA35_MUX(0xd, "INT2")),
+	MA35_PIN(167, PK13, 0xd4, 0x14,
+		MA35_MUX(0x0, "GPK13"),
+		MA35_MUX(0x1, "EPWM2_CH1"),
+		MA35_MUX(0x2, "UART1_nRTS"),
+		MA35_MUX(0x3, "UART13_TXD"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x5, "I2S0_BCLK"),
+		MA35_MUX(0x6, "SPI1_CLK"),
+		MA35_MUX(0x8, "SC0_DAT"),
+		MA35_MUX(0xb, "TM10_EXT")),
+	MA35_PIN(168, PK14, 0xd4, 0x18,
+		MA35_MUX(0x0, "GPK14"),
+		MA35_MUX(0x1, "EPWM2_CH2"),
+		MA35_MUX(0x2, "UART1_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x5, "I2S0_DI"),
+		MA35_MUX(0x6, "SPI1_MOSI"),
+		MA35_MUX(0x8, "SC0_RST"),
+		MA35_MUX(0xa, "I2C5_SDA"),
+		MA35_MUX(0xb, "TM11"),
+		MA35_MUX(0xd, "INT3")),
+	MA35_PIN(169, PK15, 0xd4, 0x1c,
+		MA35_MUX(0x0, "GPK15"),
+		MA35_MUX(0x1, "EPWM2_CH3"),
+		MA35_MUX(0x2, "UART1_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "I2S0_DO"),
+		MA35_MUX(0x6, "SPI1_MISO"),
+		MA35_MUX(0x8, "SC0_PWR"),
+		MA35_MUX(0xa, "I2C5_SCL"),
+		MA35_MUX(0xb, "TM11_EXT")),
+	MA35_PIN(170, PL0, 0xd8, 0x0,
+		MA35_MUX(0x0, "GPL0"),
+		MA35_MUX(0x1, "EPWM1_CH0"),
+		MA35_MUX(0x2, "UART11_nCTS"),
+		MA35_MUX(0x3, "UART10_RXD"),
+		MA35_MUX(0x4, "I2C3_SDA"),
+		MA35_MUX(0x5, "SPI2_MOSI"),
+		MA35_MUX(0x6, "QSPI1_MOSI1"),
+		MA35_MUX(0x7, "I2S0_LRCK"),
+		MA35_MUX(0x8, "EBI_AD11"),
+		MA35_MUX(0x9, "SC1_CLK"),
+		MA35_MUX(0xb, "TM5"),
+		MA35_MUX(0xc, "QEI1_A")),
+	MA35_PIN(171, PL1, 0xd8, 0x4,
+		MA35_MUX(0x0, "GPL1"),
+		MA35_MUX(0x1, "EPWM1_CH1"),
+		MA35_MUX(0x2, "UART11_nRTS"),
+		MA35_MUX(0x3, "UART10_TXD"),
+		MA35_MUX(0x4, "I2C3_SCL"),
+		MA35_MUX(0x5, "SPI2_MISO"),
+		MA35_MUX(0x6, "QSPI1_MISO1"),
+		MA35_MUX(0x7, "I2S0_BCLK"),
+		MA35_MUX(0x8, "EBI_AD12"),
+		MA35_MUX(0x9, "SC1_DAT"),
+		MA35_MUX(0xb, "TM5_EXT"),
+		MA35_MUX(0xc, "QEI1_B")),
+	MA35_PIN(172, PL2, 0xd8, 0x8,
+		MA35_MUX(0x0, "GPL2"),
+		MA35_MUX(0x1, "EPWM1_CH2"),
+		MA35_MUX(0x2, "UART11_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x5, "SPI2_SS0"),
+		MA35_MUX(0x6, "QSPI1_SS1"),
+		MA35_MUX(0x7, "I2S0_DI"),
+		MA35_MUX(0x8, "EBI_AD13"),
+		MA35_MUX(0x9, "SC1_RST"),
+		MA35_MUX(0xb, "TM7"),
+		MA35_MUX(0xc, "QEI1_INDEX")),
+	MA35_PIN(173, PL3, 0xd8, 0xc,
+		MA35_MUX(0x0, "GPL3"),
+		MA35_MUX(0x1, "EPWM1_CH3"),
+		MA35_MUX(0x2, "UART11_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "SPI2_CLK"),
+		MA35_MUX(0x6, "QSPI1_CLK"),
+		MA35_MUX(0x7, "I2S0_DO"),
+		MA35_MUX(0x8, "EBI_AD14"),
+		MA35_MUX(0x9, "SC1_PWR"),
+		MA35_MUX(0xb, "TM7_EXT"),
+		MA35_MUX(0xc, "ECAP0_IC0")),
+	MA35_PIN(174, PL4, 0xd8, 0x10,
+		MA35_MUX(0x0, "GPL4"),
+		MA35_MUX(0x1, "EPWM1_CH4"),
+		MA35_MUX(0x2, "UART2_nCTS"),
+		MA35_MUX(0x3, "UART1_RXD"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x5, "SPI3_MOSI"),
+		MA35_MUX(0x6, "QSPI1_MOSI0"),
+		MA35_MUX(0x7, "I2S0_MCLK"),
+		MA35_MUX(0x8, "EBI_nRD"),
+		MA35_MUX(0x9, "SC1_nCD"),
+		MA35_MUX(0xb, "TM9"),
+		MA35_MUX(0xc, "ECAP0_IC1")),
+	MA35_PIN(175, PL5, 0xd8, 0x14,
+		MA35_MUX(0x0, "GPL5"),
+		MA35_MUX(0x1, "EPWM1_CH5"),
+		MA35_MUX(0x2, "UART2_nRTS"),
+		MA35_MUX(0x3, "UART1_TXD"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x5, "SPI3_MISO"),
+		MA35_MUX(0x6, "QSPI1_MISO0"),
+		MA35_MUX(0x7, "I2S1_MCLK"),
+		MA35_MUX(0x8, "EBI_nWR"),
+		MA35_MUX(0x9, "SC0_nCD"),
+		MA35_MUX(0xb, "TM9_EXT"),
+		MA35_MUX(0xc, "ECAP0_IC2")),
+	MA35_PIN(176, PL6, 0xd8, 0x18,
+		MA35_MUX(0x0, "GPL6"),
+		MA35_MUX(0x1, "EPWM0_CH0"),
+		MA35_MUX(0x2, "UART2_RXD"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x6, "QSPI1_MOSI1"),
+		MA35_MUX(0x7, "TRACE_CLK"),
+		MA35_MUX(0x8, "EBI_AD5"),
+		MA35_MUX(0xb, "TM3"),
+		MA35_MUX(0xc, "ECAP1_IC0"),
+		MA35_MUX(0xd, "INT0")),
+	MA35_PIN(177, PL7, 0xd8, 0x1c,
+		MA35_MUX(0x0, "GPL7"),
+		MA35_MUX(0x1, "EPWM0_CH1"),
+		MA35_MUX(0x2, "UART2_TXD"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x6, "QSPI1_MISO1"),
+		MA35_MUX(0x8, "EBI_AD6"),
+		MA35_MUX(0xb, "TM3_EXT"),
+		MA35_MUX(0xc, "ECAP1_IC1"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(178, PL8, 0xdc, 0x0,
+		MA35_MUX(0x0, "GPL8"),
+		MA35_MUX(0x1, "EPWM0_CH2"),
+		MA35_MUX(0x2, "UART14_nCTS"),
+		MA35_MUX(0x3, "UART13_RXD"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x5, "SPI3_SS0"),
+		MA35_MUX(0x6, "EPWM0_CH4"),
+		MA35_MUX(0x7, "I2S1_LRCK"),
+		MA35_MUX(0x8, "EBI_AD7"),
+		MA35_MUX(0x9, "SC0_CLK"),
+		MA35_MUX(0xb, "TM4"),
+		MA35_MUX(0xc, "ECAP1_IC2"),
+		MA35_MUX(0xd, "INT2")),
+	MA35_PIN(179, PL9, 0xdc, 0x4,
+		MA35_MUX(0x0, "GPL9"),
+		MA35_MUX(0x1, "EPWM0_CH3"),
+		MA35_MUX(0x2, "UART14_nRTS"),
+		MA35_MUX(0x3, "UART13_TXD"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x5, "SPI3_CLK"),
+		MA35_MUX(0x6, "EPWM1_CH4"),
+		MA35_MUX(0x7, "I2S1_BCLK"),
+		MA35_MUX(0x8, "EBI_AD8"),
+		MA35_MUX(0x9, "SC0_DAT"),
+		MA35_MUX(0xb, "TM4_EXT"),
+		MA35_MUX(0xc, "QEI0_A"),
+		MA35_MUX(0xd, "INT3")),
+	MA35_PIN(180, PL10, 0xdc, 0x8,
+		MA35_MUX(0x0, "GPL10"),
+		MA35_MUX(0x1, "EPWM0_CH4"),
+		MA35_MUX(0x2, "UART14_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x5, "SPI3_MOSI"),
+		MA35_MUX(0x6, "EPWM0_CH5"),
+		MA35_MUX(0x7, "I2S1_DI"),
+		MA35_MUX(0x8, "EBI_AD9"),
+		MA35_MUX(0x9, "SC0_RST"),
+		MA35_MUX(0xb, "EBI_nWRH"),
+		MA35_MUX(0xc, "QEI0_B")),
+	MA35_PIN(181, PL11, 0xdc, 0xc,
+		MA35_MUX(0x0, "GPL11"),
+		MA35_MUX(0x1, "EPWM0_CH5"),
+		MA35_MUX(0x2, "UART14_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "SPI3_MISO"),
+		MA35_MUX(0x6, "EPWM1_CH5"),
+		MA35_MUX(0x7, "I2S1_DO"),
+		MA35_MUX(0x8, "EBI_AD10"),
+		MA35_MUX(0x9, "SC0_PWR"),
+		MA35_MUX(0xb, "EBI_nWRL"),
+		MA35_MUX(0xc, "QEI0_INDEX")),
+	MA35_PIN(182, PL12, 0xdc, 0x10,
+		MA35_MUX(0x0, "GPL12"),
+		MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+		MA35_MUX(0x2, "UART7_nCTS"),
+		MA35_MUX(0x3, "ECAP1_IC0"),
+		MA35_MUX(0x4, "UART14_RXD"),
+		MA35_MUX(0x5, "SPI0_SS0"),
+		MA35_MUX(0x6, "I2S1_LRCK"),
+		MA35_MUX(0x7, "SC1_CLK"),
+		MA35_MUX(0x8, "EBI_AD0"),
+		MA35_MUX(0x9, "HSUSBH_PWREN"),
+		MA35_MUX(0xa, "I2C2_SDA"),
+		MA35_MUX(0xb, "TM0"),
+		MA35_MUX(0xc, "EPWM0_CH2"),
+		MA35_MUX(0xd, "EBI_AD11"),
+		MA35_MUX(0xe, "RGMII0_PPS"),
+		MA35_MUX(0xf, "RMII0_PPS")),
+	MA35_PIN(183, PL13, 0xdc, 0x14,
+		MA35_MUX(0x0, "GPL13"),
+		MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+		MA35_MUX(0x2, "UART7_nRTS"),
+		MA35_MUX(0x3, "ECAP1_IC1"),
+		MA35_MUX(0x4, "UART14_TXD"),
+		MA35_MUX(0x5, "SPI0_CLK"),
+		MA35_MUX(0x6, "I2S1_BCLK"),
+		MA35_MUX(0x7, "SC1_DAT"),
+		MA35_MUX(0x8, "EBI_AD1"),
+		MA35_MUX(0x9, "HSUSBH_OVC"),
+		MA35_MUX(0xa, "I2C2_SCL"),
+		MA35_MUX(0xb, "TM0_EXT"),
+		MA35_MUX(0xc, "EPWM0_CH3"),
+		MA35_MUX(0xd, "EBI_AD12"),
+		MA35_MUX(0xe, "RGMII1_PPS"),
+		MA35_MUX(0xf, "RMII1_PPS")),
+	MA35_PIN(184, PL14, 0xdc, 0x18,
+		MA35_MUX(0x0, "GPL14"),
+		MA35_MUX(0x1, "EPWM0_CH2"),
+		MA35_MUX(0x2, "UART7_RXD"),
+		MA35_MUX(0x4, "CAN1_RXD"),
+		MA35_MUX(0x5, "SPI0_MOSI"),
+		MA35_MUX(0x6, "I2S1_DI"),
+		MA35_MUX(0x7, "SC1_RST"),
+		MA35_MUX(0x8, "EBI_AD2"),
+		MA35_MUX(0xb, "TM2"),
+		MA35_MUX(0xc, "INT0"),
+		MA35_MUX(0xd, "EBI_AD13")),
+	MA35_PIN(185, PL15, 0xdc, 0x1c,
+		MA35_MUX(0x0, "GPL15"),
+		MA35_MUX(0x1, "EPWM0_CH1"),
+		MA35_MUX(0x2, "UART7_TXD"),
+		MA35_MUX(0x3, "TRACE_CLK"),
+		MA35_MUX(0x4, "CAN1_TXD"),
+		MA35_MUX(0x5, "SPI0_MISO"),
+		MA35_MUX(0x6, "I2S1_DO"),
+		MA35_MUX(0x7, "SC1_PWR"),
+		MA35_MUX(0x8, "EBI_AD3"),
+		MA35_MUX(0xb, "TM2_EXT"),
+		MA35_MUX(0xc, "INT2"),
+		MA35_MUX(0xd, "EBI_AD14")),
+	MA35_PIN(186, PM0, 0xe0, 0x0,
+		MA35_MUX(0x0, "GPM0"),
+		MA35_MUX(0x4, "I2C4_SDA"),
+		MA35_MUX(0x6, "CCAP0_VSYNC"),
+		MA35_MUX(0x8, "EBI_AD3"),
+		MA35_MUX(0xa, "EBI_ADR3")),
+	MA35_PIN(187, PM1, 0xe0, 0x4,
+		MA35_MUX(0x0, "GPM1"),
+		MA35_MUX(0x4, "I2C4_SCL"),
+		MA35_MUX(0x5, "SPI3_I2SMCLK"),
+		MA35_MUX(0x6, "CCAP0_SFIELD"),
+		MA35_MUX(0x8, "EBI_AD4"),
+		MA35_MUX(0xa, "EBI_ADR4")),
+	MA35_PIN(188, PM2, 0xe0, 0x8,
+		MA35_MUX(0x0, "GPM2"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x6, "CCAP0_DATA0"),
+		MA35_MUX(0x8, "EBI_AD5"),
+		MA35_MUX(0xa, "EBI_ADR5")),
+	MA35_PIN(189, PM3, 0xe0, 0xc,
+		MA35_MUX(0x0, "GPM3"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x6, "CCAP0_DATA1"),
+		MA35_MUX(0x8, "EBI_AD6"),
+		MA35_MUX(0xa, "EBI_ADR6")),
+	MA35_PIN(190, PM4, 0xe0, 0x10,
+		MA35_MUX(0x0, "GPM4"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x6, "CCAP0_DATA2"),
+		MA35_MUX(0x8, "EBI_AD7"),
+		MA35_MUX(0xa, "EBI_ADR7")),
+	MA35_PIN(191, PM5, 0xe0, 0x14,
+		MA35_MUX(0x0, "GPM5"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x6, "CCAP0_DATA3"),
+		MA35_MUX(0x8, "EBI_AD8"),
+		MA35_MUX(0xa, "EBI_ADR8")),
+	MA35_PIN(192, PM6, 0xe0, 0x18,
+		MA35_MUX(0x0, "GPM6"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x6, "CCAP0_DATA4"),
+		MA35_MUX(0x8, "EBI_AD9"),
+		MA35_MUX(0xa, "EBI_ADR9")),
+	MA35_PIN(193, PM7, 0xe0, 0x1c,
+		MA35_MUX(0x0, "GPM7"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x6, "CCAP0_DATA5"),
+		MA35_MUX(0x8, "EBI_AD10"),
+		MA35_MUX(0xa, "EBI_ADR10")),
+	MA35_PIN(194, PM8, 0xe4, 0x0,
+		MA35_MUX(0x0, "GPM8"),
+		MA35_MUX(0x4, "I2C0_SDA"),
+		MA35_MUX(0x6, "CCAP0_DATA6"),
+		MA35_MUX(0x8, "EBI_AD11"),
+		MA35_MUX(0xa, "EBI_ADR11")),
+	MA35_PIN(195, PM9, 0xe4, 0x4,
+		MA35_MUX(0x0, "GPM9"),
+		MA35_MUX(0x4, "I2C0_SCL"),
+		MA35_MUX(0x6, "CCAP0_DATA7"),
+		MA35_MUX(0x8, "EBI_AD12"),
+		MA35_MUX(0xa, "EBI_ADR12")),
+	MA35_PIN(196, PM10, 0xe4, 0x8,
+		MA35_MUX(0x0, "GPM10"),
+		MA35_MUX(0x1, "EPWM1_CH2"),
+		MA35_MUX(0x3, "CAN2_RXD"),
+		MA35_MUX(0x5, "SPI3_SS0"),
+		MA35_MUX(0x6, "CCAP0_DATA8"),
+		MA35_MUX(0x7, "SPI2_I2SMCLK"),
+		MA35_MUX(0x8, "EBI_AD13"),
+		MA35_MUX(0xa, "EBI_ADR13")),
+	MA35_PIN(197, PM11, 0xe4, 0xc,
+		MA35_MUX(0x0, "GPM11"),
+		MA35_MUX(0x1, "EPWM1_CH3"),
+		MA35_MUX(0x3, "CAN2_TXD"),
+		MA35_MUX(0x5, "SPI3_SS1"),
+		MA35_MUX(0x6, "CCAP0_DATA9"),
+		MA35_MUX(0x7, "SPI2_SS1"),
+		MA35_MUX(0x8, "EBI_AD14"),
+		MA35_MUX(0xa, "EBI_ADR14")),
+	MA35_PIN(198, PM12, 0xe4, 0x10,
+		MA35_MUX(0x0, "GPM12"),
+		MA35_MUX(0x1, "EPWM1_CH4"),
+		MA35_MUX(0x2, "UART10_nCTS"),
+		MA35_MUX(0x3, "TRACE_DATA0"),
+		MA35_MUX(0x4, "UART11_RXD"),
+		MA35_MUX(0x5, "I2C2_SDA"),
+		MA35_MUX(0x7, "SC1_nCD"),
+		MA35_MUX(0x8, "EBI_AD8"),
+		MA35_MUX(0x9, "I2S1_MCLK"),
+		MA35_MUX(0xb, "TM8")),
+	MA35_PIN(199, PM13, 0xe4, 0x14,
+		MA35_MUX(0x0, "GPM13"),
+		MA35_MUX(0x1, "EPWM1_CH5"),
+		MA35_MUX(0x2, "UART10_nRTS"),
+		MA35_MUX(0x3, "TRACE_DATA1"),
+		MA35_MUX(0x4, "UART11_TXD"),
+		MA35_MUX(0x5, "I2C2_SCL"),
+		MA35_MUX(0x8, "EBI_AD9"),
+		MA35_MUX(0x9, "ECAP1_IC0"),
+		MA35_MUX(0xb, "TM8_EXT")),
+	MA35_PIN(200, PM14, 0xe4, 0x18,
+		MA35_MUX(0x0, "GPM14"),
+		MA35_MUX(0x1, "EPWM1_BRAKE0"),
+		MA35_MUX(0x2, "UART10_RXD"),
+		MA35_MUX(0x3, "TRACE_DATA2"),
+		MA35_MUX(0x4, "CAN2_RXD"),
+		MA35_MUX(0x6, "I2C3_SDA"),
+		MA35_MUX(0x8, "EBI_AD10"),
+		MA35_MUX(0x9, "ECAP1_IC1"),
+		MA35_MUX(0xb, "TM10"),
+		MA35_MUX(0xd, "INT1")),
+	MA35_PIN(201, PM15, 0xe4, 0x1c,
+		MA35_MUX(0x0, "GPM15"),
+		MA35_MUX(0x1, "EPWM1_BRAKE1"),
+		MA35_MUX(0x2, "UART10_TXD"),
+		MA35_MUX(0x3, "TRACE_DATA3"),
+		MA35_MUX(0x4, "CAN2_TXD"),
+		MA35_MUX(0x6, "I2C3_SCL"),
+		MA35_MUX(0x8, "EBI_AD11"),
+		MA35_MUX(0x9, "ECAP1_IC2"),
+		MA35_MUX(0xb, "TM10_EXT"),
+		MA35_MUX(0xd, "INT2")),
+	MA35_PIN(202, PN0, 0xe8, 0x0,
+		MA35_MUX(0x0, "GPN0"),
+		MA35_MUX(0x4, "I2C2_SDA"),
+		MA35_MUX(0x6, "CCAP1_DATA0")),
+	MA35_PIN(203, PN1, 0xe8, 0x4,
+		MA35_MUX(0x0, "GPN1"),
+		MA35_MUX(0x4, "I2C2_SCL"),
+		MA35_MUX(0x6, "CCAP1_DATA1")),
+	MA35_PIN(204, PN2, 0xe8, 0x8,
+		MA35_MUX(0x0, "GPN2"),
+		MA35_MUX(0x3, "CAN0_RXD"),
+		MA35_MUX(0x6, "CCAP1_DATA2")),
+	MA35_PIN(205, PN3, 0xe8, 0xc,
+		MA35_MUX(0x0, "GPN3"),
+		MA35_MUX(0x3, "CAN0_TXD"),
+		MA35_MUX(0x6, "CCAP1_DATA3")),
+	MA35_PIN(206, PN4, 0xe8, 0x10,
+		MA35_MUX(0x0, "GPN4"),
+		MA35_MUX(0x4, "I2C1_SDA"),
+		MA35_MUX(0x6, "CCAP1_DATA4")),
+	MA35_PIN(207, PN5, 0xe8, 0x14,
+		MA35_MUX(0x0, "GPN5"),
+		MA35_MUX(0x4, "I2C1_SCL"),
+		MA35_MUX(0x6, "CCAP1_DATA5")),
+	MA35_PIN(208, PN6, 0xe8, 0x18,
+		MA35_MUX(0x0, "GPN6"),
+		MA35_MUX(0x3, "CAN1_RXD"),
+		MA35_MUX(0x6, "CCAP1_DATA6")),
+	MA35_PIN(209, PN7, 0xe8, 0x1c,
+		MA35_MUX(0x0, "GPN7"),
+		MA35_MUX(0x3, "CAN1_TXD"),
+		MA35_MUX(0x6, "CCAP1_DATA7")),
+	MA35_PIN(210, PN10, 0xec, 0x8,
+		MA35_MUX(0x0, "GPN10"),
+		MA35_MUX(0x3, "CAN2_RXD"),
+		MA35_MUX(0x6, "CCAP1_SCLK")),
+	MA35_PIN(211, PN11, 0xec, 0xc,
+		MA35_MUX(0x0, "GPN11"),
+		MA35_MUX(0x3, "CAN2_TXD"),
+		MA35_MUX(0x6, "CCAP1_PIXCLK")),
+	MA35_PIN(212, PN12, 0xec, 0x10,
+		MA35_MUX(0x0, "GPN12"),
+		MA35_MUX(0x2, "UART6_nCTS"),
+		MA35_MUX(0x3, "UART12_RXD"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x6, "CCAP1_HSYNC")),
+	MA35_PIN(213, PN13, 0xec, 0x14,
+		MA35_MUX(0x0, "GPN13"),
+		MA35_MUX(0x2, "UART6_nRTS"),
+		MA35_MUX(0x3, "UART12_TXD"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x6, "CCAP1_VSYNC")),
+	MA35_PIN(214, PN14, 0xec, 0x18,
+		MA35_MUX(0x0, "GPN14"),
+		MA35_MUX(0x2, "UART6_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x5, "SPI1_SS1"),
+		MA35_MUX(0x6, "CCAP1_SFIELD"),
+		MA35_MUX(0x7, "SPI1_I2SMCLK")),
+	MA35_PIN(215, PN15, 0xec, 0x1c,
+		MA35_MUX(0x0, "GPN15"),
+		MA35_MUX(0x1, "EPWM2_CH4"),
+		MA35_MUX(0x2, "UART6_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x5, "I2S0_MCLK"),
+		MA35_MUX(0x6, "SPI1_SS1"),
+		MA35_MUX(0x7, "SPI1_I2SMCLK"),
+		MA35_MUX(0x8, "SC0_nCD"),
+		MA35_MUX(0x9, "EADC0_ST"),
+		MA35_MUX(0xa, "CLKO"),
+		MA35_MUX(0xb, "TM6")),
+	MA35_PIN(216, PN8, 0xec, 0x0,
+		MA35_MUX(0x0, "GPN8"),
+		MA35_MUX(0x1, "EPWM2_CH4"),
+		MA35_MUX(0x4, "I2C0_SDA"),
+		MA35_MUX(0x5, "SPI2_I2SMCLK"),
+		MA35_MUX(0x6, "CCAP1_DATA8")),
+	MA35_PIN(217, PN9, 0xec, 0x4,
+		MA35_MUX(0x0, "GPN9"),
+		MA35_MUX(0x1, "EPWM2_CH5"),
+		MA35_MUX(0x4, "I2C0_SCL"),
+		MA35_MUX(0x5, "SPI1_I2SMCLK"),
+		MA35_MUX(0x6, "CCAP1_DATA9")),
+	MA35_PIN(218, PN10, 0xec, 0x8,
+		MA35_MUX(0x0, "GPN10"),
+		MA35_MUX(0x3, "CAN2_RXD"),
+		MA35_MUX(0x4, "USBHL2_DM"),
+		MA35_MUX(0x6, "CCAP1_SCLK")),
+	MA35_PIN(219, PN11, 0xec, 0xc,
+		MA35_MUX(0x0, "GPN11"),
+		MA35_MUX(0x3, "CAN2_TXD"),
+		MA35_MUX(0x4, "USBHL2_DP"),
+		MA35_MUX(0x6, "CCAP1_PIXCLK")),
+	MA35_PIN(220, PN12, 0xec, 0x10,
+		MA35_MUX(0x0, "GPN12"),
+		MA35_MUX(0x2, "UART6_nCTS"),
+		MA35_MUX(0x3, "UART12_RXD"),
+		MA35_MUX(0x4, "I2C5_SDA"),
+		MA35_MUX(0x6, "CCAP1_HSYNC")),
+	MA35_PIN(221, PN13, 0xec, 0x14,
+		MA35_MUX(0x0, "GPN13"),
+		MA35_MUX(0x2, "UART6_nRTS"),
+		MA35_MUX(0x3, "UART12_TXD"),
+		MA35_MUX(0x4, "I2C5_SCL"),
+		MA35_MUX(0x6, "CCAP1_VSYNC")),
+	MA35_PIN(222, PN14, 0xec, 0x18,
+		MA35_MUX(0x0, "GPN14"),
+		MA35_MUX(0x2, "UART6_RXD"),
+		MA35_MUX(0x3, "CAN3_RXD"),
+		MA35_MUX(0x4, "USBHL3_DM"),
+		MA35_MUX(0x5, "SPI1_SS1"),
+		MA35_MUX(0x6, "CCAP1_SFIELD"),
+		MA35_MUX(0x7, "SPI1_I2SMCLK")),
+	MA35_PIN(223, PN15, 0xec, 0x1c,
+		MA35_MUX(0x0, "GPN15"),
+		MA35_MUX(0x1, "EPWM2_CH4"),
+		MA35_MUX(0x2, "UART6_TXD"),
+		MA35_MUX(0x3, "CAN3_TXD"),
+		MA35_MUX(0x4, "USBHL3_DP"),
+		MA35_MUX(0x5, "I2S0_MCLK"),
+		MA35_MUX(0x6, "SPI1_SS1"),
+		MA35_MUX(0x7, "SPI1_I2SMCLK"),
+		MA35_MUX(0x8, "SC0_nCD"),
+		MA35_MUX(0x9, "EADC0_ST"),
+		MA35_MUX(0xa, "CLKO"),
+		MA35_MUX(0xb, "TM6")),
+};
+
+static int ma35d1_get_pin_num(int offset, int shift)
+{
+	return (offset - 0x80) * 2 + shift / 4;
+}
+
+static struct ma35_pinctrl_soc_info ma35d1_pinctrl_info = {
+	.pins = ma35d1_pins,
+	.npins = ARRAY_SIZE(ma35d1_pins),
+	.get_pin_num = ma35d1_get_pin_num,
+};
+
+const struct dev_pm_ops ma35d1_pinctrl_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(ma35_pinctrl_suspend, ma35_pinctrl_resume)
+};
+
+static int ma35d1_pinctrl_probe(struct platform_device *pdev)
+{
+	return ma35_pinctrl_probe(pdev, &ma35d1_pinctrl_info);
+}
+
+static const struct of_device_id ma35d1_pinctrl_of_match[] = {
+	{ .compatible = "nuvoton,ma35d1-pinctrl", },
+	{ },
+};
+
+static struct platform_driver ma35d1_pinctrl_driver = {
+	.probe = ma35d1_pinctrl_probe,
+	.driver = {
+		.name = "ma35d1-pinctrl",
+		.pm = &ma35d1_pinctrl_pm_ops,
+		.of_match_table = ma35d1_pinctrl_of_match,
+	},
+};
+
+static int __init ma35d1_pinctrl_init(void)
+{
+	return platform_driver_register(&ma35d1_pinctrl_driver);
+}
+arch_initcall(ma35d1_pinctrl_init);
+
+MODULE_AUTHOR("schung@nuvoton.com");
+MODULE_DESCRIPTION("Nuvoton MA35D1 pinctrl driver");
+MODULE_LICENSE("GPL");
-- 
2.34.1