From: Thomas Richard <thomas.richard@bootlin.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
thomas.petazzoni@bootlin.com, DanieleCleri@aaeon.eu,
GaryWang@aaeon.com.tw
Subject: Re: [PATCH RFC v2 6/6] pinctrl: Add pin controller driver for AAEON UP boards
Date: Tue, 15 Apr 2025 10:39:29 +0200 [thread overview]
Message-ID: <91ede632-f339-4bcb-908f-49ed0fcadbd0@bootlin.com> (raw)
In-Reply-To: <243d0ab5-8354-496c-8c58-0a85adf1a4e4@bootlin.com>
On 4/9/25 16:02, Thomas Richard wrote:
> On 3/17/25 19:42, Andy Shevchenko wrote:
>>> + board_id = (enum upboard_board_id)dmi_id->driver_data;
>>> +
>>> + switch (board_id) {
>>> + case BOARD_UP_APL01:
>>> + pctrl->maps = upboard_pinctrl_mapping_up_apl01;
>>> + pctrl->nmaps = ARRAY_SIZE(upboard_pinctrl_mapping_up_apl01);
>>> + break;
>>
>> Hmm... This is strange. Seems it has only Apollo Lake in the name while
>> the above states that there is UP board support (which is Cherry Trail based).
>
> There is pinctrl code for UP and UP Squared. But I only added mapping
> for UP Squared board because it was the easiest board to add (all needed
> pinctrl groups and functions are already defined in the Intel pinctrl
> driver).
> I wanted to focus on the driver itself and the forwarder library, and
> send later an other series to add UP board support (with the
> corresponding functions/groups in the Intel pinctrl driver).
>
> So yes UP board pinctrl part is unused for now, but everything is ready
> to add support for UP board in the future.
>
> Otherwise I can remove UP part if you prefer.
Hi Andy,
I just realized that my wording was incorrect, so let me clarify.
The UP Board [1] (based on Cherry Trail) is not supported at all (its
FPGA is not supported by the MFD driver), and there is no plan to
support it.
The "up" code (for example upboard_up_pinctrl_data) is for most boards
of the UP family (UP 7000, UPXi12, UP Squared Pro 7000 ...) but not the
UP Board [1]. Indeed for now there is no pinctrl mapping for these boards.
The "up2" code is for the UP Squared board which uses a different FPGA.
As I explained I only added pinctrl mapping for the UP Squared board, as
it was the easiest one (no need to add groups/functions in Intel pinctrl
driver). But the plan is to add support for other boards (UP 7000,
IPXi12 ...) later.
Regarding the name of the pinctrl mapping for UP Squared board, it is
indeed a bit confusing, I will rename it.
[1]
https://www.aaeon.com/en/product/detail/up-board-computer-board-for-professional-makers
Best Regards,
Thomas
prev parent reply other threads:[~2025-04-15 8:39 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-17 15:37 [PATCH RFC v2 0/6] Add pinctrl support for the AAEON UP board FPGA Thomas Richard
2025-03-17 15:37 ` [PATCH RFC v2 1/6] gpiolib: add gpiochip_add_pin_range_sparse() function Thomas Richard
2025-03-17 16:59 ` Andy Shevchenko
2025-04-09 13:49 ` Thomas Richard
2025-03-17 15:38 ` [PATCH RFC v2 2/6] gpio: aggregator: refactor the forwarder part Thomas Richard
2025-03-17 17:04 ` Andy Shevchenko
2025-03-17 15:38 ` [PATCH RFC v2 3/6] gpio: aggregator: export symbols of the gpio-fwd library Thomas Richard
2025-03-17 17:10 ` Andy Shevchenko
2025-03-17 15:38 ` [PATCH RFC v2 4/6] gpio: aggregator: handle runtime registration of gpio_desc in gpiochip_fwd Thomas Richard
2025-03-17 17:13 ` Andy Shevchenko
2025-04-09 14:50 ` Thomas Richard
2025-03-17 15:38 ` [PATCH RFC v2 5/6] gpio: aggregator: add possibility to attach data to the forwarder Thomas Richard
2025-03-18 13:18 ` Bartosz Golaszewski
2025-03-17 15:38 ` [PATCH RFC v2 6/6] pinctrl: Add pin controller driver for AAEON UP boards Thomas Richard
2025-03-17 18:42 ` Andy Shevchenko
2025-04-09 14:02 ` Thomas Richard
2025-04-15 8:39 ` Thomas Richard [this message]
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