[PATCH 0/5] Add support for VeriSilicon APB GPIO driver

[PATCH 0/5] Add support for VeriSilicon APB GPIO driver

[Nikolaos Pasaloukos]

This patchset adds a GPIO driver for the VeriSilicon APB v0.2
hardware. This controller is used in the Blaize BLZP1600
SoC for its GPIO interface. It is essential for upstream
support of the SoC since it is used to provide signals for the
Ethernet, SD and many other interfaces.

It also adds VeriSilicon as a vendor prefix, devicetree
bindings for the controller and the driver itself.

Adds the GPIO interface to the Blaize BLZP1600 SoC devicetree
and includes it in the ARM generic kernel defconfig.

The hardware itself consists of 32 I/O pins. It has
programmable interrupt generation capability on the pins.
The interrupts can be edge or level triggered and it
includes a de-bounce circuit.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
Nikolaos Pasaloukos (5):
      dt-bindings: Add VeriSilicon vendor prefix
      dt-bindings: Document VeriSilicon APB GPIO driver
      gpio: vsiapb: Add VeriSilicon APB support
      arm64: dts: blaize-blzp1600: Add VeriSilicon GPIO support
      arm64: defconfig: Add VeriSilicon GPIO driver

 .../devicetree/bindings/gpio/vsi,apb-gpio.yaml     |  83 ++++++
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 MAINTAINERS                                        |  10 +
 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts |  36 +++
 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi    |  12 +
 arch/arm64/configs/defconfig                       |   1 +
 drivers/gpio/Kconfig                               |   9 +
 drivers/gpio/Makefile                              |   1 +
 drivers/gpio/gpio-vsiapb.c                         | 284 +++++++++++++++++++++
 9 files changed, 438 insertions(+)
---
base-commit: 6d5039eb97a58be0817ee0f5956ec4d22047f42a
change-id: 20250117-kernel-upstreaming-add_gpio_support-b4ce05eff7a5

Best regards,
-- 
Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

[PATCH 1/5] dt-bindings: Add VeriSilicon vendor prefix

[Nikolaos Pasaloukos]

VeriSilicon Microelectronics is a custom silicon service
provider.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5079ca6ce1d1e9e2b52312439e4b1d48b262200c..14dfefbffe05180a4d8b62b3b54fc25964f56028 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1643,6 +1643,8 @@ patternProperties:
     description: Vision Optical Technology Co., Ltd.
   "^vscom,.*":
     description: VS Visions Systems GmbH
+  "^vsi,.*":
+    description: VeriSilicon Microelectronics Co., Ltd.
   "^vxt,.*":
     description: VXT Ltd
   "^wacom,.*":

-- 
2.43.0

Re: [PATCH 1/5] dt-bindings: Add VeriSilicon vendor prefix

[Krzysztof Kozlowski]

On 12/02/2025 14:46, Nikolaos Pasaloukos wrote:
> VeriSilicon Microelectronics is a custom silicon service
> provider.
> 
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 5079ca6ce1d1e9e2b52312439e4b1d48b262200c..14dfefbffe05180a4d8b62b3b54fc25964f56028 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -1643,6 +1643,8 @@ patternProperties:
>      description: Vision Optical Technology Co., Ltd.
>    "^vscom,.*":
>      description: VS Visions Systems GmbH
> +  "^vsi,.*":

Better verisilicon. This is supposed to match the web domain.

> +    description: VeriSilicon Microelectronics Co., Ltd.
Best regards,
Krzysztof

[PATCH 2/5] dt-bindings: Document VeriSilicon APB GPIO driver

[Nikolaos Pasaloukos]

This is a custom silicon GPIO driver provided from VeriSilicon
Microelectronics. It has 32 input/output ports which can be
configured as edge or level triggered interrupts. It also provides
a de-bounce feature.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 .../devicetree/bindings/gpio/vsi,apb-gpio.yaml     | 83 ++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..4a293b44e03895b6a45cb85f42c47c46b64f5638
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/vsi,apb-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: VeriSilicon APB GPIO controller
+
+description: |
+  VeriSilicon GPIO controllers have a configurable number of ports, each
+  of which are intended to be represented as child nodes with the generic
+  GPIO-controller properties as described in this bindings file.
+
+maintainers:
+  - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+  - James Cowgill <james.cowgill@blaize.com>
+  - Matthew Redfearn <matthew.redfearn@blaize.com>
+  - Neil Jones <neil.jones@blaize.com>
+
+properties:
+  $nodename:
+    pattern: "^gpio@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - description: Verisilicon APB GPIO controller
+        items:
+          - enum:
+              - vsi,apb-gpio-0.2
+
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  ngpios:
+    default: 32
+    minimum: 1
+    maximum: 32
+
+  interrupts:
+    description: |
+      The interrupts to the parent controller raised when GPIOs generate
+      the interrupts. Specify a single interrupt since the controller
+      provides one combined interrupt for all GPIOs.
+    maxItems: 1
+
+  gpio-line-names: true
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+
+dependencies:
+  interrupt-controller: [ interrupts ]
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpio: gpio@4c0000 {
+      compatible = "vsi,apb-gpio-0.2";
+      reg = <0x004c0000 0x1000>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      ngpios = <32>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...

-- 
2.43.0

Re: [PATCH 2/5] dt-bindings: Document VeriSilicon APB GPIO driver

[Krzysztof Kozlowski]

On 12/02/2025 14:46, Nikolaos Pasaloukos wrote:
> diff --git a/Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..4a293b44e03895b6a45cb85f42c47c46b64f5638
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/vsi,apb-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: VeriSilicon APB GPIO controller
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  VeriSilicon GPIO controllers have a configurable number of ports, each
> +  of which are intended to be represented as child nodes with the generic
> +  GPIO-controller properties as described in this bindings file.
> +
> +maintainers:
> +  - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> +  - James Cowgill <james.cowgill@blaize.com>
> +  - Matthew Redfearn <matthew.redfearn@blaize.com>
> +  - Neil Jones <neil.jones@blaize.com>
> +
> +properties:
> +  $nodename:
> +    pattern: "^gpio@[0-9a-f]+$"
> +
> +  compatible:
> +    oneOf:

Drop

> +      - description: Verisilicon APB GPIO controller

Drop

> +        items:
> +          - enum:

Missing SoC compatible. Maybe IP block is simple enough to use the same
generic compatible for all implementations, but usually Rob was
suggesting that it is anyway not the best approach, so I would just make
it SoC specific only (and rename the file to match compatible). If the
fallback is really usable by every implementation, it could stay, but
OTOH, your 'ngpios' property already suggests that it is not enough to
use fallback alone.


> +
> +  reg:
> +    maxItems: 1
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  ngpios:
> +    default: 32
> +    minimum: 1
> +    maximum: 32
> +
> +  interrupts:
> +    description: |
> +      The interrupts to the parent controller raised when GPIOs generate
> +      the interrupts. Specify a single interrupt since the controller
> +      provides one combined interrupt for all GPIOs.

Drop description, obvious.

> +    maxItems: 1
> +
> +  gpio-line-names: true
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 2
> +



Best regards,
Krzysztof

[PATCH 4/5] arm64: dts: blaize-blzp1600: Add VeriSilicon GPIO support

[Nikolaos Pasaloukos]

Blaize BLZP1600 uses the custom silicon provided from
VeriSilicon to add GPIO support.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts | 36 ++++++++++++++++++++++
 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi    | 12 ++++++++
 2 files changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
index 7e3cef2ed3522e202487e799b2021cd45398e006..fb5415eb347a028fc65090027a4c4fc89c8280f5 100644
--- a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -81,3 +81,39 @@ gpio_expander_m2: gpio@75 {
 				  "UART1_TO_RSP";	/* GPIO_15 */
 	};
 };
+
+&gpio0 {
+	status = "okay";
+	gpio-line-names = "PERST_N",		/* GPIO_0 */
+			  "LM96063_ALERT_N",	/* GPIO_1 */
+			  "INA3221_PV",		/* GPIO_2 */
+			  "INA3221_CRIT",	/* GPIO_3 */
+			  "INA3221_WARN",	/* GPIO_4 */
+			  "INA3221_TC",		/* GPIO_5 */
+			  "QSPI0_RST_N",	/* GPIO_6 */
+			  "LM96063_TCRIT_N",	/* GPIO_7 */
+			  "DSI_TCH_INT",	/* GPIO_8 */
+			  "DSI_RST",		/* GPIO_9 */
+			  "DSI_BL",		/* GPIO_10 */
+			  "DSI_INT",		/* GPIO_11 */
+			  "ETH_RST",		/* GPIO_12 */
+			  "CSI0_RST",		/* GPIO_13 */
+			  "CSI0_PWDN",		/* GPIO_14 */
+			  "CSI1_RST",		/* GPIO_15 */
+			  "CSI1_PWDN",		/* GPIO_16 */
+			  "CSI2_RST",		/* GPIO_17 */
+			  "CSI2_PWDN",		/* GPIO_18 */
+			  "CSI3_RST",		/* GPIO_19 */
+			  "CSI3_PWDN",		/* GPIO_20 */
+			  "ADAC_RST",		/* GPIO_21 */
+			  "SD_SW_VDD",		/* GPIO_22 */
+			  "SD_PON_VDD",		/* GPIO_23 */
+			  "GPIO_EXP_INT",	/* GPIO_24 */
+			  "BOARD_ID_0",		/* GPIO_25 */
+			  "SDIO1_SW_VDD",	/* GPIO_26 */
+			  "SDIO1_PON_VDD",	/* GPIO_27 */
+			  "SDIO2_SW_VDD",	/* GPIO_28 */
+			  "SDIO2_PON_VDD",	/* GPIO_29 */
+			  "BOARD_ID_1",		/* GPIO_30 */
+			  "BOARD_ID_2";		/* GPIO_31 */
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
index 7d399e6a532f5b24385dd837be965be771c7d24c..7f31e3055f70c1dac798deab073787df83e798d3 100644
--- a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -120,6 +120,18 @@ gic: interrupt-controller@410000 {
 						 IRQ_TYPE_LEVEL_LOW)>;
 		};
 
+		gpio0: gpio@4c0000 {
+			compatible = "vsi,apb-gpio-0.2";
+			reg = <0x4c0000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
 		uart0: serial@4d0000 {
 			compatible = "ns16550a";
 			reg = <0x4d0000 0x1000>;

-- 
2.43.0

[PATCH 3/5] gpio: vsiapb: Add VeriSilicon APB support

[Nikolaos Pasaloukos]

VeriSilicon APB v0.2 is a custom GPIO design provided from VeriSilicon
Microelectronics. It has 32 input/output ports which can be
configured as edge or level triggered interrupts. It also provides
a de-bounce feature.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 MAINTAINERS                |  10 ++
 drivers/gpio/Kconfig       |   9 ++
 drivers/gpio/Makefile      |   1 +
 drivers/gpio/gpio-vsiapb.c | 284 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 304 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index eb75c95f6c455516f7b1c8b3a39ddded5b38e0a9..ad75f7df37d8d63e14846e659666230b137a7ea1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25343,6 +25343,16 @@ S:	Maintained
 F:	Documentation/networking/vrf.rst
 F:	drivers/net/vrf.c
 
+VSI APB GPIO DRIVER
+M:	James Cowgill <james.cowgill@blaize.com>
+M:	Matt Redfearn <matt.redfearn@blaize.com>
+M:	Neil Jones <neil.jones@blaize.com>
+M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+L:	linux-gpio@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml
+F:	drivers/gpio/gpio-vsiapb.c
+
 VSPRINTF
 M:	Petr Mladek <pmladek@suse.com>
 M:	Steven Rostedt <rostedt@goodmis.org>
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index add5ad29a673c09082a913cb2404073b2034af48..654603f790c7db2481265c2ab7d90eec4be79856 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -769,6 +769,15 @@ config GPIO_VISCONTI
 	help
 	  Say yes here to support GPIO on Tohisba Visconti.
 
+config GPIO_VSIAPB
+	tristate "Verisilicon APB GPIO support"
+	depends on OF_GPIO
+	select GPIO_GENERIC
+	select GPIOLIB_IRQCHIP
+	select IRQ_DOMAIN_HIERARCHY
+	help
+	  Say Y or M here to add support for the Verisilicon APB GPIO device.
+
 config GPIO_WCD934X
 	tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
 	depends on MFD_WCD934X && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index af3ba4d81b583842893ea69e677fbe2abf31bc7b..f0f2dd711c84b9159418154419664c7c1f28340f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -189,6 +189,7 @@ obj-$(CONFIG_GPIO_VIPERBOARD)		+= gpio-viperboard.o
 obj-$(CONFIG_GPIO_VIRTUSER)		+= gpio-virtuser.o
 obj-$(CONFIG_GPIO_VIRTIO)		+= gpio-virtio.o
 obj-$(CONFIG_GPIO_VISCONTI)		+= gpio-visconti.o
+obj-$(CONFIG_GPIO_VSIAPB)		+= gpio-vsiapb.o
 obj-$(CONFIG_GPIO_VX855)		+= gpio-vx855.o
 obj-$(CONFIG_GPIO_WCD934X)		+= gpio-wcd934x.o
 obj-$(CONFIG_GPIO_WHISKEY_COVE)		+= gpio-wcove.o
diff --git a/drivers/gpio/gpio-vsiapb.c b/drivers/gpio/gpio-vsiapb.c
new file mode 100644
index 0000000000000000000000000000000000000000..dab7c579235058724a9b3f07ce302eed5e4f5fce
--- /dev/null
+++ b/drivers/gpio/gpio-vsiapb.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2019 VeriSilicon Limited.
+ * Copyright (C) 2025 Blaize, Inc.
+ */
+
+#include <linux/errno.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define GPIO_DIR_REG	0x00
+#define GPIO_CTRL_REG	0x04
+#define GPIO_SET_REG	0x08
+#define GPIO_CLR_REG	0x0C
+#define GPIO_ODATA_REG	0x10
+#define GPIO_IDATA_REG	0x14
+#define GPIO_IEN_REG	0x18
+#define GPIO_IS_REG	0x1C
+#define GPIO_IBE_REG	0x20
+#define GPIO_IEV_REG	0x24
+#define GPIO_RIS_REG	0x28
+#define GPIO_IM_REG	0x2C
+#define GPIO_MIS_REG	0x30
+#define GPIO_IC_REG	0x34
+#define GPIO_DB_REG	0x38
+#define GPIO_DFG_REG	0x3C
+
+#define DRIVER_NAME "vsiapb-gpio"
+
+struct vsiapb_gpio {
+	void __iomem *base;
+	struct gpio_chip gc;
+	int irq;
+};
+
+static inline struct vsiapb_gpio *get_vsiapb_from_irq_data(struct irq_data *d)
+{
+	return gpiochip_get_data(irq_data_get_irq_chip_data(d));
+}
+
+static inline struct vsiapb_gpio *get_vsiapb_from_irq_desc(struct irq_desc *d)
+{
+	return gpiochip_get_data(irq_desc_get_handler_data(d));
+}
+
+static inline u32 vsiapb_gpio_read(struct vsiapb_gpio *chip, unsigned int offset)
+{
+	return readl_relaxed(chip->base + offset);
+}
+
+static inline void vsiapb_gpio_write(struct vsiapb_gpio *chip, unsigned int offset, u32 val)
+{
+	writel_relaxed(val, chip->base + offset);
+}
+
+static inline void vsiapb_gpio_rmw(void __iomem *reg, u32 mask, bool set)
+{
+	u32 val = readl_relaxed(reg);
+
+	if (set)
+		val |= mask;
+	else
+		val &= ~mask;
+
+	writel_relaxed(val, reg);
+}
+
+static void vsiapb_gpio_irq_mask(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1);
+}
+
+static void vsiapb_gpio_irq_unmask(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0);
+}
+
+static void vsiapb_gpio_irq_ack(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	vsiapb_gpio_write(chip, GPIO_IC_REG, BIT(d->hwirq));
+}
+
+static void vsiapb_gpio_irq_enable(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d));
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0);
+	vsiapb_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1);
+}
+
+static void vsiapb_gpio_irq_disable(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0);
+	gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d));
+}
+
+static int vsiapb_gpio_irq_set_type(struct irq_data *d, u32 type)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+	u32 edge_level, single_both, fall_rise;
+	int mask = BIT(d->hwirq);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	edge_level = vsiapb_gpio_read(chip, GPIO_IS_REG);
+	single_both = vsiapb_gpio_read(chip, GPIO_IBE_REG);
+	fall_rise = vsiapb_gpio_read(chip, GPIO_IEV_REG);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_BOTH:
+		edge_level &= ~mask;
+		single_both |= mask;
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		edge_level &= ~mask;
+		single_both &= ~mask;
+		fall_rise |= mask;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		edge_level &= ~mask;
+		single_both &= ~mask;
+		fall_rise &= ~mask;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		edge_level |= mask;
+		fall_rise |= mask;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		edge_level |= mask;
+		fall_rise &= ~mask;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	vsiapb_gpio_write(chip, GPIO_IS_REG, edge_level);
+	vsiapb_gpio_write(chip, GPIO_IBE_REG, single_both);
+	vsiapb_gpio_write(chip, GPIO_IEV_REG, fall_rise);
+
+	if (type & IRQ_TYPE_LEVEL_MASK)
+		irq_set_handler_locked(d, handle_level_irq);
+	else
+		irq_set_handler_locked(d, handle_edge_irq);
+
+	return 0;
+}
+
+static const struct irq_chip vsiapb_gpio_irqchip = {
+	.name = DRIVER_NAME,
+	.irq_ack = vsiapb_gpio_irq_ack,
+	.irq_mask = vsiapb_gpio_irq_mask,
+	.irq_unmask = vsiapb_gpio_irq_unmask,
+	.irq_set_type = vsiapb_gpio_irq_set_type,
+	.irq_enable = vsiapb_gpio_irq_enable,
+	.irq_disable = vsiapb_gpio_irq_disable,
+	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void vsiapb_gpio_irqhandler(struct irq_desc *desc)
+{
+	struct vsiapb_gpio *gpio = get_vsiapb_from_irq_desc(desc);
+	struct irq_chip *irqchip = irq_desc_get_chip(desc);
+	unsigned long irq_status;
+	int hwirq = 0;
+
+	chained_irq_enter(irqchip, desc);
+	irq_status = vsiapb_gpio_read(gpio, GPIO_RIS_REG);
+	for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio)
+		generic_handle_domain_irq(gpio->gc.irq.domain, hwirq);
+
+	chained_irq_exit(irqchip, desc);
+}
+
+static int vsiapb_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset,
+				    unsigned int debounce)
+{
+	struct vsiapb_gpio *chip = gpiochip_get_data(gc);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce);
+
+	return 0;
+}
+
+static int vsiapb_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config)
+{
+	u32 debounce;
+
+	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
+		return -ENOTSUPP;
+
+	debounce = pinconf_to_config_argument(config);
+	return vsiapb_gpio_set_debounce(gc, offset, debounce);
+}
+
+static int vsiapb_gpio_probe(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct vsiapb_gpio *chip;
+	struct gpio_chip *gc;
+	int ret;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(chip->base))
+		return PTR_ERR(chip->base);
+
+	ret = bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG,
+			 chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG,
+			 chip->base + GPIO_DIR_REG, NULL, 0);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "Failed to register generic gpio\n");
+
+	/* configure the gpio chip */
+	gc = &chip->gc;
+	gc->owner = THIS_MODULE;
+	gc->set_config = vsiapb_gpio_set_config;
+
+	if (of_property_read_bool(node, "interrupt-controller")) {
+		struct gpio_irq_chip *girq;
+
+		chip->irq = platform_get_irq(pdev, 0);
+		if (chip->irq < 0)
+			return chip->irq;
+
+		girq = &gc->irq;
+		gpio_irq_chip_set_chip(girq, &vsiapb_gpio_irqchip);
+		girq->parent_handler = vsiapb_gpio_irqhandler;
+		girq->num_parents = 1;
+		girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
+		if (!girq->parents)
+			return -ENOMEM;
+
+		girq->parents[0] = chip->irq;
+		girq->default_type = IRQ_TYPE_NONE;
+	}
+
+	return devm_gpiochip_add_data(&pdev->dev, gc, chip);
+}
+
+static const struct of_device_id vsiapb_of_match[] = {
+	{ .compatible = "vsi,apb-gpio-0.2", },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, vsiapb_of_match);
+
+static struct platform_driver vsiapb_gpio_driver = {
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(vsiapb_of_match),
+	},
+	.probe		= vsiapb_gpio_probe,
+};
+
+module_platform_driver(vsiapb_gpio_driver);
+
+MODULE_AUTHOR("Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>");
+MODULE_DESCRIPTION("Verisilicon APB GPIO driver");
+MODULE_LICENSE("GPL");

-- 
2.43.0

Re: [PATCH 3/5] gpio: vsiapb: Add VeriSilicon APB support

[Linus Walleij]

Hi Nikolaos,

thanks for your patch!

This driver is really high quality, only nitpicks below.

With these addressed:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

On Wed, Feb 12, 2025 at 2:47 PM Nikolaos Pasaloukos
<nikolaos.pasaloukos@blaize.com> wrote:

> VeriSilicon APB v0.2 is a custom GPIO design provided from VeriSilicon
> Microelectronics. It has 32 input/output ports which can be
> configured as edge or level triggered interrupts. It also provides
> a de-bounce feature.
>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
(...)
> +config GPIO_VSIAPB
> +       tristate "Verisilicon APB GPIO support"
> +       depends on OF_GPIO
> +       select GPIO_GENERIC
> +       select GPIOLIB_IRQCHIP
> +       select IRQ_DOMAIN_HIERARCHY

Are you really using the hierarchical domain?

Not in this driver, right? This is just regular chained IRQ.

> +       /* configure the gpio chip */
> +       gc = &chip->gc;
> +       gc->owner = THIS_MODULE;

I think the core sets up owner for you so you can drop this assignment?

Yours,
Linus Walleij

[PATCH 5/5] arm64: defconfig: Add VeriSilicon GPIO driver

[Nikolaos Pasaloukos]

Add support for VeriSilicon GPIO controller.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 246a13412bf05221e4e306ff0857dde13f0fd155..26d7b99a276f737b57f317f7d7ca1228d1183a02 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -660,6 +660,7 @@ CONFIG_GPIO_RCAR=y
 CONFIG_GPIO_SYSCON=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_GPIO_VISCONTI=y
+CONFIG_GPIO_VSIAPB=y
 CONFIG_GPIO_WCD934X=m
 CONFIG_GPIO_VF610=y
 CONFIG_GPIO_XGENE=y

-- 
2.43.0

Re: [PATCH 5/5] arm64: defconfig: Add VeriSilicon GPIO driver

[Krzysztof Kozlowski]

On 12/02/2025 14:46, Nikolaos Pasaloukos wrote:
> Add support for VeriSilicon GPIO controller.

You enable not add support, but still the main question is: Why? Which
devices needs it? Why this cannot be a module?



Best regards,
Krzysztof

Re: [PATCH 5/5] arm64: defconfig: Add VeriSilicon GPIO driver

[Nikolaos Pasaloukos]

On 12/02/2025 15:25, Krzysztof Kozlowski wrote:

> On 12/02/2025 14:46, Nikolaos Pasaloukos wrote:
>> Add support for VeriSilicon GPIO controller.
> You enable not add support, but still the main question is: Why? Which
> devices needs it? Why this cannot be a module?

Hi Krzysztof,

Thank you for your fast review and apologies for the typo. I forgot to
mention on the commit message but I have mentioned in the cover letter
that the driver is needed for the Blaize BLZP1600 CB2 board which is
already supported on v6.14. I will fix the commit message on V2.

This driver enables support (controls) for multiple peripherals on
the board, like Ethernet for NFS boot, SD and eMMC to load modules from
these media. Without this driver build in the kernel, it will be hard to
mount a filesystem and load modules.

Kind regards,
Nikolaos

>
>
>
> Best regards,
> Krzysztof

Re: [PATCH 5/5] arm64: defconfig: Add VeriSilicon GPIO driver

[Bartosz Golaszewski]

On Wed, Feb 12, 2025 at 5:20 PM Nikolaos Pasaloukos
<nikolaos.pasaloukos@blaize.com> wrote:
>
> On 12/02/2025 15:25, Krzysztof Kozlowski wrote:
>
> > On 12/02/2025 14:46, Nikolaos Pasaloukos wrote:
> >> Add support for VeriSilicon GPIO controller.
> > You enable not add support, but still the main question is: Why? Which
> > devices needs it? Why this cannot be a module?
>
> Hi Krzysztof,
>
> Thank you for your fast review and apologies for the typo. I forgot to
> mention on the commit message but I have mentioned in the cover letter
> that the driver is needed for the Blaize BLZP1600 CB2 board which is
> already supported on v6.14. I will fix the commit message on V2.
>
> This driver enables support (controls) for multiple peripherals on
> the board, like Ethernet for NFS boot, SD and eMMC to load modules from
> these media. Without this driver build in the kernel, it will be hard to
> mount a filesystem and load modules.
>

That's alright but typically you'd want to have something like:

default y if ARCH_BLAIZE

in the driver's Kconfig entry.

Bart

Re: [PATCH 5/5] arm64: defconfig: Add VeriSilicon GPIO driver

[Nikolaos Pasaloukos]

On 12/02/2025 16:28, Bartosz Golaszewski wrote:

> On Wed, Feb 12, 2025 at 5:20 PM Nikolaos Pasaloukos
> <nikolaos.pasaloukos@blaize.com> wrote:
>> On 12/02/2025 15:25, Krzysztof Kozlowski wrote:
>>
>>> On 12/02/2025 14:46, Nikolaos Pasaloukos wrote:
>>>> Add support for VeriSilicon GPIO controller.
>>> You enable not add support, but still the main question is: Why? Which
>>> devices needs it? Why this cannot be a module?
>> Hi Krzysztof,
>>
>> Thank you for your fast review and apologies for the typo. I forgot to
>> mention on the commit message but I have mentioned in the cover letter
>> that the driver is needed for the Blaize BLZP1600 CB2 board which is
>> already supported on v6.14. I will fix the commit message on V2.
>>
>> This driver enables support (controls) for multiple peripherals on
>> the board, like Ethernet for NFS boot, SD and eMMC to load modules from
>> these media. Without this driver build in the kernel, it will be hard to
>> mount a filesystem and load modules.
>>
> That's alright but typically you'd want to have something like:
>
> default y if ARCH_BLAIZE
>
> in the driver's Kconfig entry.
>
> Bart

Hi Bart,

Thank you for your suggestion. I will fix it on V2.

Kind regards,
Nikolaos