[PATCH V2 0/2] gpio: pmic-eic-sprd: Modification of UNISOC Platform PMIC EIC Driver

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* [PATCH V2 0/2] gpio: pmic-eic-sprd: Modification of UNISOC Platform PMIC EIC Driver
@ 2023-09-21 12:25 Wenhua Lin
  2023-09-21 12:25 ` [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic Wenhua Lin
  2023-09-21 12:25 ` [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip Wenhua Lin
  0 siblings, 2 replies; 12+ messages in thread
From: Wenhua Lin @ 2023-09-21 12:25 UTC (permalink / raw)
  To: Linus Walleij, Andy Shevchenko, Bartosz Golaszewski
  Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-gpio, linux-kernel,
	wenhua lin, Wenhua Lin, Xiongpeng Wu

Recently, some bugs have been discovered during use, and patch1
and patch2 are bug fixes.

Change in V2:
-Change commit message and title in PATCH 1/2.
-PATCH 2/2 add can_sleep flag for PMIC EIC chip 
split into a separate patch in PATCH 1/2.
-Delete the modification of IRQF_TRIGGER_LOW.

Wenhua Lin (2):
  gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip

 drivers/gpio/gpio-pmic-eic-sprd.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-21 12:25 [PATCH V2 0/2] gpio: pmic-eic-sprd: Modification of UNISOC Platform PMIC EIC Driver Wenhua Lin
@ 2023-09-21 12:25 ` Wenhua Lin
  2023-09-27  7:21   ` Bartosz Golaszewski
                     ` (2 more replies)
  2023-09-21 12:25 ` [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip Wenhua Lin
  1 sibling, 3 replies; 12+ messages in thread
From: Wenhua Lin @ 2023-09-21 12:25 UTC (permalink / raw)
  To: Linus Walleij, Andy Shevchenko, Bartosz Golaszewski
  Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-gpio, linux-kernel,
	wenhua lin, Wenhua Lin, Xiongpeng Wu

A bank PMIC EIC contains 16 EICs, and the operating registers
are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
will cause the configuration of other EICs to be affected when
operating a certain EIC. In order to solve this problem, the register
operation bits of each PMIC EIC are maintained through the two-dimensional
array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.

Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
---
 drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
index c3e4d90f6b18..442968bb2490 100644
--- a/drivers/gpio/gpio-pmic-eic-sprd.c
+++ b/drivers/gpio/gpio-pmic-eic-sprd.c
@@ -57,7 +57,7 @@ struct sprd_pmic_eic {
 	struct gpio_chip chip;
 	struct regmap *map;
 	u32 offset;
-	u8 reg[CACHE_NR_REGS];
+	u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
 	struct mutex buslock;
 	int irq;
 };
@@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 	u32 offset = irqd_to_hwirq(data);
 
-	pmic_eic->reg[REG_IE] = 0;
-	pmic_eic->reg[REG_TRIG] = 0;
+	pmic_eic->reg[offset][REG_IE] = 0;
+	pmic_eic->reg[offset][REG_TRIG] = 0;
 
 	gpiochip_disable_irq(chip, offset);
 }
@@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
 
 	gpiochip_enable_irq(chip, offset);
 
-	pmic_eic->reg[REG_IE] = 1;
-	pmic_eic->reg[REG_TRIG] = 1;
+	pmic_eic->reg[offset][REG_IE] = 1;
+	pmic_eic->reg[offset][REG_TRIG] = 1;
 }
 
 static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
@@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
 {
 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
+	u32 offset = irqd_to_hwirq(data);
 
 	switch (flow_type) {
 	case IRQ_TYPE_LEVEL_HIGH:
-		pmic_eic->reg[REG_IEV] = 1;
+		pmic_eic->reg[offset][REG_IEV] = 1;
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
-		pmic_eic->reg[REG_IEV] = 0;
+		pmic_eic->reg[offset][REG_IEV] = 0;
 		break;
 	case IRQ_TYPE_EDGE_RISING:
 	case IRQ_TYPE_EDGE_FALLING:
@@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
 			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
 	} else {
 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
-				     pmic_eic->reg[REG_IEV]);
+				     pmic_eic->reg[offset][REG_IEV]);
 	}
 
 	/* Set irq unmask */
 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
-			     pmic_eic->reg[REG_IE]);
+			     pmic_eic->reg[offset][REG_IE]);
 	/* Generate trigger start pulse for debounce EIC */
 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
-			     pmic_eic->reg[REG_TRIG]);
+			     pmic_eic->reg[offset][REG_TRIG]);
 
 	mutex_unlock(&pmic_eic->buslock);
 }
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-21 12:25 ` [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic Wenhua Lin
@ 2023-09-27  7:21   ` Bartosz Golaszewski
  2023-09-27  9:04   ` Baolin Wang
  2023-09-28  9:00   ` Chunyan Zhang
  2 siblings, 0 replies; 12+ messages in thread
From: Bartosz Golaszewski @ 2023-09-27  7:21 UTC (permalink / raw)
  To: Wenhua Lin
  Cc: Linus Walleij, Andy Shevchenko, Orson Zhai, Baolin Wang,
	Chunyan Zhang, linux-gpio, linux-kernel, wenhua lin, Xiongpeng Wu

On Thu, Sep 21, 2023 at 2:27 PM Wenhua Lin <Wenhua.Lin@unisoc.com> wrote:
>
> A bank PMIC EIC contains 16 EICs, and the operating registers
> are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
> Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
> will cause the configuration of other EICs to be affected when
> operating a certain EIC. In order to solve this problem, the register
> operation bits of each PMIC EIC are maintained through the two-dimensional
> array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.
>
> Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> ---
>  drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
>  1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> index c3e4d90f6b18..442968bb2490 100644
> --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
>         struct gpio_chip chip;
>         struct regmap *map;
>         u32 offset;
> -       u8 reg[CACHE_NR_REGS];
> +       u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
>         struct mutex buslock;
>         int irq;
>  };
> @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
>         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
>         u32 offset = irqd_to_hwirq(data);
>
> -       pmic_eic->reg[REG_IE] = 0;
> -       pmic_eic->reg[REG_TRIG] = 0;
> +       pmic_eic->reg[offset][REG_IE] = 0;
> +       pmic_eic->reg[offset][REG_TRIG] = 0;
>
>         gpiochip_disable_irq(chip, offset);
>  }
> @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
>
>         gpiochip_enable_irq(chip, offset);
>
> -       pmic_eic->reg[REG_IE] = 1;
> -       pmic_eic->reg[REG_TRIG] = 1;
> +       pmic_eic->reg[offset][REG_IE] = 1;
> +       pmic_eic->reg[offset][REG_TRIG] = 1;
>  }
>
>  static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
>  {
>         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
>         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> +       u32 offset = irqd_to_hwirq(data);
>
>         switch (flow_type) {
>         case IRQ_TYPE_LEVEL_HIGH:
> -               pmic_eic->reg[REG_IEV] = 1;
> +               pmic_eic->reg[offset][REG_IEV] = 1;
>                 break;
>         case IRQ_TYPE_LEVEL_LOW:
> -               pmic_eic->reg[REG_IEV] = 0;
> +               pmic_eic->reg[offset][REG_IEV] = 0;
>                 break;
>         case IRQ_TYPE_EDGE_RISING:
>         case IRQ_TYPE_EDGE_FALLING:
> @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
>                         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
>         } else {
>                 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
> -                                    pmic_eic->reg[REG_IEV]);
> +                                    pmic_eic->reg[offset][REG_IEV]);
>         }
>
>         /* Set irq unmask */
>         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
> -                            pmic_eic->reg[REG_IE]);
> +                            pmic_eic->reg[offset][REG_IE]);
>         /* Generate trigger start pulse for debounce EIC */
>         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
> -                            pmic_eic->reg[REG_TRIG]);
> +                            pmic_eic->reg[offset][REG_TRIG]);
>
>         mutex_unlock(&pmic_eic->buslock);
>  }
> --
> 2.17.1
>

This looks good to me but I want to let the SPRD maintainers
review/test it before applying.

Bart

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-21 12:25 ` [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic Wenhua Lin
  2023-09-27  7:21   ` Bartosz Golaszewski
@ 2023-09-27  9:04   ` Baolin Wang
  2023-09-27  9:24     ` Chunyan Zhang
  2023-09-28  9:00   ` Chunyan Zhang
  2 siblings, 1 reply; 12+ messages in thread
From: Baolin Wang @ 2023-09-27  9:04 UTC (permalink / raw)
  To: Wenhua Lin, Linus Walleij, Andy Shevchenko, Bartosz Golaszewski
  Cc: Orson Zhai, Chunyan Zhang, linux-gpio, linux-kernel, wenhua lin,
	Xiongpeng Wu



On 9/21/2023 8:25 PM, Wenhua Lin wrote:
> A bank PMIC EIC contains 16 EICs, and the operating registers
> are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
> Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
> will cause the configuration of other EICs to be affected when
> operating a certain EIC. In order to solve this problem, the register
> operation bits of each PMIC EIC are maintained through the two-dimensional
> array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.

LGTM. And this also deserves a Fixes tag.
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>

> Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> ---
>   drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
>   1 file changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> index c3e4d90f6b18..442968bb2490 100644
> --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
>   	struct gpio_chip chip;
>   	struct regmap *map;
>   	u32 offset;
> -	u8 reg[CACHE_NR_REGS];
> +	u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
>   	struct mutex buslock;
>   	int irq;
>   };
> @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
>   	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
>   	u32 offset = irqd_to_hwirq(data);
>   
> -	pmic_eic->reg[REG_IE] = 0;
> -	pmic_eic->reg[REG_TRIG] = 0;
> +	pmic_eic->reg[offset][REG_IE] = 0;
> +	pmic_eic->reg[offset][REG_TRIG] = 0;
>   
>   	gpiochip_disable_irq(chip, offset);
>   }
> @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
>   
>   	gpiochip_enable_irq(chip, offset);
>   
> -	pmic_eic->reg[REG_IE] = 1;
> -	pmic_eic->reg[REG_TRIG] = 1;
> +	pmic_eic->reg[offset][REG_IE] = 1;
> +	pmic_eic->reg[offset][REG_TRIG] = 1;
>   }
>   
>   static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
>   {
>   	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
>   	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> +	u32 offset = irqd_to_hwirq(data);
>   
>   	switch (flow_type) {
>   	case IRQ_TYPE_LEVEL_HIGH:
> -		pmic_eic->reg[REG_IEV] = 1;
> +		pmic_eic->reg[offset][REG_IEV] = 1;
>   		break;
>   	case IRQ_TYPE_LEVEL_LOW:
> -		pmic_eic->reg[REG_IEV] = 0;
> +		pmic_eic->reg[offset][REG_IEV] = 0;
>   		break;
>   	case IRQ_TYPE_EDGE_RISING:
>   	case IRQ_TYPE_EDGE_FALLING:
> @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
>   			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
>   	} else {
>   		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
> -				     pmic_eic->reg[REG_IEV]);
> +				     pmic_eic->reg[offset][REG_IEV]);
>   	}
>   
>   	/* Set irq unmask */
>   	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
> -			     pmic_eic->reg[REG_IE]);
> +			     pmic_eic->reg[offset][REG_IE]);
>   	/* Generate trigger start pulse for debounce EIC */
>   	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
> -			     pmic_eic->reg[REG_TRIG]);
> +			     pmic_eic->reg[offset][REG_TRIG]);
>   
>   	mutex_unlock(&pmic_eic->buslock);
>   }

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-27  9:04   ` Baolin Wang
@ 2023-09-27  9:24     ` Chunyan Zhang
  2023-09-27  9:49       ` Baolin Wang
  0 siblings, 1 reply; 12+ messages in thread
From: Chunyan Zhang @ 2023-09-27  9:24 UTC (permalink / raw)
  To: Baolin Wang
  Cc: Wenhua Lin, Linus Walleij, Andy Shevchenko, Bartosz Golaszewski,
	Orson Zhai, linux-gpio, linux-kernel, wenhua lin, Xiongpeng Wu

On Wed, 27 Sept 2023 at 17:04, Baolin Wang
<baolin.wang@linux.alibaba.com> wrote:
>
>
>
> On 9/21/2023 8:25 PM, Wenhua Lin wrote:
> > A bank PMIC EIC contains 16 EICs, and the operating registers
> > are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
> > Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
> > will cause the configuration of other EICs to be affected when
> > operating a certain EIC. In order to solve this problem, the register
> > operation bits of each PMIC EIC are maintained through the two-dimensional
> > array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.
>
> LGTM. And this also deserves a Fixes tag.

Do we really need a two-dimensional array to save 16-bit value?

> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
>
> > Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> > ---
> >   drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
> >   1 file changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> > index c3e4d90f6b18..442968bb2490 100644
> > --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> > +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> > @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
> >       struct gpio_chip chip;
> >       struct regmap *map;
> >       u32 offset;
> > -     u8 reg[CACHE_NR_REGS];
> > +     u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
> >       struct mutex buslock;
> >       int irq;
> >   };
> > @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
> >       struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> >       u32 offset = irqd_to_hwirq(data);
> >
> > -     pmic_eic->reg[REG_IE] = 0;
> > -     pmic_eic->reg[REG_TRIG] = 0;
> > +     pmic_eic->reg[offset][REG_IE] = 0;
> > +     pmic_eic->reg[offset][REG_TRIG] = 0;
> >
> >       gpiochip_disable_irq(chip, offset);
> >   }
> > @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
> >
> >       gpiochip_enable_irq(chip, offset);
> >
> > -     pmic_eic->reg[REG_IE] = 1;
> > -     pmic_eic->reg[REG_TRIG] = 1;
> > +     pmic_eic->reg[offset][REG_IE] = 1;
> > +     pmic_eic->reg[offset][REG_TRIG] = 1;
> >   }
> >
> >   static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> > @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> >   {
> >       struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
> >       struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> > +     u32 offset = irqd_to_hwirq(data);
> >
> >       switch (flow_type) {
> >       case IRQ_TYPE_LEVEL_HIGH:
> > -             pmic_eic->reg[REG_IEV] = 1;
> > +             pmic_eic->reg[offset][REG_IEV] = 1;
> >               break;
> >       case IRQ_TYPE_LEVEL_LOW:
> > -             pmic_eic->reg[REG_IEV] = 0;
> > +             pmic_eic->reg[offset][REG_IEV] = 0;
> >               break;
> >       case IRQ_TYPE_EDGE_RISING:
> >       case IRQ_TYPE_EDGE_FALLING:
> > @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
> >                       sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
> >       } else {
> >               sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
> > -                                  pmic_eic->reg[REG_IEV]);
> > +                                  pmic_eic->reg[offset][REG_IEV]);
> >       }
> >
> >       /* Set irq unmask */
> >       sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
> > -                          pmic_eic->reg[REG_IE]);
> > +                          pmic_eic->reg[offset][REG_IE]);
> >       /* Generate trigger start pulse for debounce EIC */
> >       sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
> > -                          pmic_eic->reg[REG_TRIG]);
> > +                          pmic_eic->reg[offset][REG_TRIG]);
> >
> >       mutex_unlock(&pmic_eic->buslock);
> >   }

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-27  9:24     ` Chunyan Zhang
@ 2023-09-27  9:49       ` Baolin Wang
  0 siblings, 0 replies; 12+ messages in thread
From: Baolin Wang @ 2023-09-27  9:49 UTC (permalink / raw)
  To: Chunyan Zhang
  Cc: Wenhua Lin, Linus Walleij, Andy Shevchenko, Bartosz Golaszewski,
	Orson Zhai, linux-gpio, linux-kernel, wenhua lin, Xiongpeng Wu



On 9/27/2023 5:24 PM, Chunyan Zhang wrote:
> On Wed, 27 Sept 2023 at 17:04, Baolin Wang
> <baolin.wang@linux.alibaba.com> wrote:
>>
>>
>>
>> On 9/21/2023 8:25 PM, Wenhua Lin wrote:
>>> A bank PMIC EIC contains 16 EICs, and the operating registers
>>> are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
>>> Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
>>> will cause the configuration of other EICs to be affected when
>>> operating a certain EIC. In order to solve this problem, the register
>>> operation bits of each PMIC EIC are maintained through the two-dimensional
>>> array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.
>>
>> LGTM. And this also deserves a Fixes tag.
> 
> Do we really need a two-dimensional array to save 16-bit value?

I also considering this, but after more thinking, I think this patch is 
a simple fix.

Now I realized the problem is that, if we use one array to cache a bank 
of EICs' status, the pmic_eic->reg[] array can contain incorrect 
configuration for other EICs in the same bank.

Yes, we can have another fix, for example, setting the pmic_eic->reg[] 
to some invalid values (maybe -1) in sprd_pmic_eic_bus_sync_unlock() 
after setting one EIC. Thus when setting another EIC, we can validate if 
the cached reg is a valid value, if not, we do not need to set the 
register. But like I said above, this seems more complicated.

>> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
>>
>>> Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
>>> ---
>>>    drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
>>>    1 file changed, 11 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
>>> index c3e4d90f6b18..442968bb2490 100644
>>> --- a/drivers/gpio/gpio-pmic-eic-sprd.c
>>> +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
>>> @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
>>>        struct gpio_chip chip;
>>>        struct regmap *map;
>>>        u32 offset;
>>> -     u8 reg[CACHE_NR_REGS];
>>> +     u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
>>>        struct mutex buslock;
>>>        int irq;
>>>    };
>>> @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
>>>        struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
>>>        u32 offset = irqd_to_hwirq(data);
>>>
>>> -     pmic_eic->reg[REG_IE] = 0;
>>> -     pmic_eic->reg[REG_TRIG] = 0;
>>> +     pmic_eic->reg[offset][REG_IE] = 0;
>>> +     pmic_eic->reg[offset][REG_TRIG] = 0;
>>>
>>>        gpiochip_disable_irq(chip, offset);
>>>    }
>>> @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
>>>
>>>        gpiochip_enable_irq(chip, offset);
>>>
>>> -     pmic_eic->reg[REG_IE] = 1;
>>> -     pmic_eic->reg[REG_TRIG] = 1;
>>> +     pmic_eic->reg[offset][REG_IE] = 1;
>>> +     pmic_eic->reg[offset][REG_TRIG] = 1;
>>>    }
>>>
>>>    static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
>>> @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
>>>    {
>>>        struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
>>>        struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
>>> +     u32 offset = irqd_to_hwirq(data);
>>>
>>>        switch (flow_type) {
>>>        case IRQ_TYPE_LEVEL_HIGH:
>>> -             pmic_eic->reg[REG_IEV] = 1;
>>> +             pmic_eic->reg[offset][REG_IEV] = 1;
>>>                break;
>>>        case IRQ_TYPE_LEVEL_LOW:
>>> -             pmic_eic->reg[REG_IEV] = 0;
>>> +             pmic_eic->reg[offset][REG_IEV] = 0;
>>>                break;
>>>        case IRQ_TYPE_EDGE_RISING:
>>>        case IRQ_TYPE_EDGE_FALLING:
>>> @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
>>>                        sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
>>>        } else {
>>>                sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
>>> -                                  pmic_eic->reg[REG_IEV]);
>>> +                                  pmic_eic->reg[offset][REG_IEV]);
>>>        }
>>>
>>>        /* Set irq unmask */
>>>        sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
>>> -                          pmic_eic->reg[REG_IE]);
>>> +                          pmic_eic->reg[offset][REG_IE]);
>>>        /* Generate trigger start pulse for debounce EIC */
>>>        sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
>>> -                          pmic_eic->reg[REG_TRIG]);
>>> +                          pmic_eic->reg[offset][REG_TRIG]);
>>>
>>>        mutex_unlock(&pmic_eic->buslock);
>>>    }

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-21 12:25 ` [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic Wenhua Lin
  2023-09-27  7:21   ` Bartosz Golaszewski
  2023-09-27  9:04   ` Baolin Wang
@ 2023-09-28  9:00   ` Chunyan Zhang
  2024-01-02  7:29     ` wenhua lin
  2 siblings, 1 reply; 12+ messages in thread
From: Chunyan Zhang @ 2023-09-28  9:00 UTC (permalink / raw)
  To: Wenhua Lin
  Cc: Linus Walleij, Andy Shevchenko, Bartosz Golaszewski, Orson Zhai,
	Baolin Wang, linux-gpio, linux-kernel, wenhua lin, Xiongpeng Wu

On Thu, 21 Sept 2023 at 20:27, Wenhua Lin <Wenhua.Lin@unisoc.com> wrote:
>
> A bank PMIC EIC contains 16 EICs, and the operating registers
> are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
> Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
> will cause the configuration of other EICs to be affected when
> operating a certain EIC. In order to solve this problem, the register
> operation bits of each PMIC EIC are maintained through the two-dimensional
> array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.
>
> Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> ---
>  drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
>  1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> index c3e4d90f6b18..442968bb2490 100644
> --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
>         struct gpio_chip chip;
>         struct regmap *map;
>         u32 offset;
> -       u8 reg[CACHE_NR_REGS];
> +       u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
>         struct mutex buslock;
>         int irq;
>  };
> @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
>         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
>         u32 offset = irqd_to_hwirq(data);
>
> -       pmic_eic->reg[REG_IE] = 0;
> -       pmic_eic->reg[REG_TRIG] = 0;
> +       pmic_eic->reg[offset][REG_IE] = 0;
> +       pmic_eic->reg[offset][REG_TRIG] = 0;

I would suggest just using this one-dimensional array which is enough
for saving 16-bit values.

To solve the issue mentioned in the commit message, we can set/clear
the bit according to the value of 'offset', for example:

pmic_eic->reg[REG_IE] &= ~BIT(offset);

>
>         gpiochip_disable_irq(chip, offset);
>  }
> @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
>
>         gpiochip_enable_irq(chip, offset);
>
> -       pmic_eic->reg[REG_IE] = 1;
> -       pmic_eic->reg[REG_TRIG] = 1;
> +       pmic_eic->reg[offset][REG_IE] = 1;
> +       pmic_eic->reg[offset][REG_TRIG] = 1;

For setting operations:

pmic_eic->reg[REG_IE] |= BIT(offset);

>  }
>
>  static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
>  {
>         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
>         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> +       u32 offset = irqd_to_hwirq(data);
>
>         switch (flow_type) {
>         case IRQ_TYPE_LEVEL_HIGH:
> -               pmic_eic->reg[REG_IEV] = 1;
> +               pmic_eic->reg[offset][REG_IEV] = 1;
>                 break;
>         case IRQ_TYPE_LEVEL_LOW:
> -               pmic_eic->reg[REG_IEV] = 0;
> +               pmic_eic->reg[offset][REG_IEV] = 0;
>                 break;
>         case IRQ_TYPE_EDGE_RISING:
>         case IRQ_TYPE_EDGE_FALLING:
> @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
>                         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
>         } else {
>                 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
> -                                    pmic_eic->reg[REG_IEV]);
> +                                    pmic_eic->reg[offset][REG_IEV]);

When using the array we can deal with it like below since
sprd_pmic_eic_update() would do a shift for the parameter 'val':

(pmic_eic->reg[REG_IEV] & BIT(offset)) ? 1 : 0;

>         }
>
>         /* Set irq unmask */
>         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
> -                            pmic_eic->reg[REG_IE]);
> +                            pmic_eic->reg[offset][REG_IE]);
>         /* Generate trigger start pulse for debounce EIC */
>         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
> -                            pmic_eic->reg[REG_TRIG]);
> +                            pmic_eic->reg[offset][REG_TRIG]);

Similar here.

Thanks,
Chunyan

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic
  2023-09-28  9:00   ` Chunyan Zhang
@ 2024-01-02  7:29     ` wenhua lin
  0 siblings, 0 replies; 12+ messages in thread
From: wenhua lin @ 2024-01-02  7:29 UTC (permalink / raw)
  To: Chunyan Zhang
  Cc: Wenhua Lin, Linus Walleij, Andy Shevchenko, Bartosz Golaszewski,
	Orson Zhai, Baolin Wang, linux-gpio, linux-kernel, Xiongpeng Wu

On Thu, Sep 28, 2023 at 5:01 PM Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>
> On Thu, 21 Sept 2023 at 20:27, Wenhua Lin <Wenhua.Lin@unisoc.com> wrote:
> >
> > A bank PMIC EIC contains 16 EICs, and the operating registers
> > are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
> > Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
> > will cause the configuration of other EICs to be affected when
> > operating a certain EIC. In order to solve this problem, the register
> > operation bits of each PMIC EIC are maintained through the two-dimensional
> > array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference.
> >
> > Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> > ---
> >  drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
> >  1 file changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> > index c3e4d90f6b18..442968bb2490 100644
> > --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> > +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> > @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
> >         struct gpio_chip chip;
> >         struct regmap *map;
> >         u32 offset;
> > -       u8 reg[CACHE_NR_REGS];
> > +       u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
> >         struct mutex buslock;
> >         int irq;
> >  };
> > @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
> >         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> >         u32 offset = irqd_to_hwirq(data);
> >
> > -       pmic_eic->reg[REG_IE] = 0;
> > -       pmic_eic->reg[REG_TRIG] = 0;
> > +       pmic_eic->reg[offset][REG_IE] = 0;
> > +       pmic_eic->reg[offset][REG_TRIG] = 0;
>
> I would suggest just using this one-dimensional array which is enough
> for saving 16-bit values.
>
> To solve the issue mentioned in the commit message, we can set/clear
> the bit according to the value of 'offset', for example:
>
> pmic_eic->reg[REG_IE] &= ~BIT(offset);
>
> >
> >         gpiochip_disable_irq(chip, offset);
> >  }
> > @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
> >
> >         gpiochip_enable_irq(chip, offset);
> >
> > -       pmic_eic->reg[REG_IE] = 1;
> > -       pmic_eic->reg[REG_TRIG] = 1;
> > +       pmic_eic->reg[offset][REG_IE] = 1;
> > +       pmic_eic->reg[offset][REG_TRIG] = 1;
>
> For setting operations:
>
> pmic_eic->reg[REG_IE] |= BIT(offset);
>
> >  }
> >
> >  static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> > @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> >  {
> >         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
> >         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
> > +       u32 offset = irqd_to_hwirq(data);
> >
> >         switch (flow_type) {
> >         case IRQ_TYPE_LEVEL_HIGH:
> > -               pmic_eic->reg[REG_IEV] = 1;
> > +               pmic_eic->reg[offset][REG_IEV] = 1;
> >                 break;
> >         case IRQ_TYPE_LEVEL_LOW:
> > -               pmic_eic->reg[REG_IEV] = 0;
> > +               pmic_eic->reg[offset][REG_IEV] = 0;
> >                 break;
> >         case IRQ_TYPE_EDGE_RISING:
> >         case IRQ_TYPE_EDGE_FALLING:
> > @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
> >                         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
> >         } else {
> >                 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
> > -                                    pmic_eic->reg[REG_IEV]);
> > +                                    pmic_eic->reg[offset][REG_IEV]);
>
> When using the array we can deal with it like below since
> sprd_pmic_eic_update() would do a shift for the parameter 'val':
>
> (pmic_eic->reg[REG_IEV] & BIT(offset)) ? 1 : 0;
>

Thank you very much for your review.
I will fix this issue in patch v3.

> >         }
> >
> >         /* Set irq unmask */
> >         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
> > -                            pmic_eic->reg[REG_IE]);
> > +                            pmic_eic->reg[offset][REG_IE]);
> >         /* Generate trigger start pulse for debounce EIC */
> >         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
> > -                            pmic_eic->reg[REG_TRIG]);
> > +                            pmic_eic->reg[offset][REG_TRIG]);
>
> Similar here.
>
> Thanks,
> Chunyan

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip
  2023-09-21 12:25 [PATCH V2 0/2] gpio: pmic-eic-sprd: Modification of UNISOC Platform PMIC EIC Driver Wenhua Lin
  2023-09-21 12:25 ` [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic Wenhua Lin
@ 2023-09-21 12:25 ` Wenhua Lin
  2023-09-21 15:39   ` Andy Shevchenko
  2023-09-27  9:05   ` Baolin Wang
  1 sibling, 2 replies; 12+ messages in thread
From: Wenhua Lin @ 2023-09-21 12:25 UTC (permalink / raw)
  To: Linus Walleij, Andy Shevchenko, Bartosz Golaszewski
  Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-gpio, linux-kernel,
	wenhua lin, Wenhua Lin, Xiongpeng Wu

The drivers uses a mutex and I2C bus access in its PMIC EIC chip
get implementation. This means these functions can sleep and the PMIC EIC
chip should set the can_sleep property to true.

This will ensure that a warning is printed when trying to get the
value from a context that potentially can't sleep.

Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
---
 drivers/gpio/gpio-pmic-eic-sprd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
index 442968bb2490..f04a40288638 100644
--- a/drivers/gpio/gpio-pmic-eic-sprd.c
+++ b/drivers/gpio/gpio-pmic-eic-sprd.c
@@ -353,6 +353,7 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
 	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
 	pmic_eic->chip.set = sprd_pmic_eic_set;
 	pmic_eic->chip.get = sprd_pmic_eic_get;
+	pmic_eic->chip.can_sleep = true;
 
 	irq = &pmic_eic->chip.irq;
 	gpio_irq_chip_set_chip(irq, &pmic_eic_irq_chip);
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip
  2023-09-21 12:25 ` [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip Wenhua Lin
@ 2023-09-21 15:39   ` Andy Shevchenko
  2023-09-27  7:13     ` Bartosz Golaszewski
  2023-09-27  9:05   ` Baolin Wang
  1 sibling, 1 reply; 12+ messages in thread
From: Andy Shevchenko @ 2023-09-21 15:39 UTC (permalink / raw)
  To: Wenhua Lin
  Cc: Linus Walleij, Bartosz Golaszewski, Orson Zhai, Baolin Wang,
	Chunyan Zhang, linux-gpio, linux-kernel, wenhua lin, Xiongpeng Wu

On Thu, Sep 21, 2023 at 08:25:27PM +0800, Wenhua Lin wrote:
> The drivers uses a mutex and I2C bus access in its PMIC EIC chip
> get implementation. This means these functions can sleep and the PMIC EIC
> chip should set the can_sleep property to true.
> 
> This will ensure that a warning is printed when trying to get the
> value from a context that potentially can't sleep.

This deserves a Fixes tag.

-- 
With Best Regards,
Andy Shevchenko



^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip
  2023-09-21 15:39   ` Andy Shevchenko
@ 2023-09-27  7:13     ` Bartosz Golaszewski
  0 siblings, 0 replies; 12+ messages in thread
From: Bartosz Golaszewski @ 2023-09-27  7:13 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: Wenhua Lin, Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
	linux-gpio, linux-kernel, wenhua lin, Xiongpeng Wu

On Thu, Sep 21, 2023 at 5:40 PM Andy Shevchenko <andy@kernel.org> wrote:
>
> On Thu, Sep 21, 2023 at 08:25:27PM +0800, Wenhua Lin wrote:
> > The drivers uses a mutex and I2C bus access in its PMIC EIC chip
> > get implementation. This means these functions can sleep and the PMIC EIC
> > chip should set the can_sleep property to true.
> >
> > This will ensure that a warning is printed when trying to get the
> > value from a context that potentially can't sleep.
>
> This deserves a Fixes tag.
>
> --
> With Best Regards,
> Andy Shevchenko
>
>

Added when applying and queued for fixes.

Bart

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip
  2023-09-21 12:25 ` [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip Wenhua Lin
  2023-09-21 15:39   ` Andy Shevchenko
@ 2023-09-27  9:05   ` Baolin Wang
  1 sibling, 0 replies; 12+ messages in thread
From: Baolin Wang @ 2023-09-27  9:05 UTC (permalink / raw)
  To: Wenhua Lin, Linus Walleij, Andy Shevchenko, Bartosz Golaszewski
  Cc: Orson Zhai, Chunyan Zhang, linux-gpio, linux-kernel, wenhua lin,
	Xiongpeng Wu



On 9/21/2023 8:25 PM, Wenhua Lin wrote:
> The drivers uses a mutex and I2C bus access in its PMIC EIC chip
> get implementation. This means these functions can sleep and the PMIC EIC
> chip should set the can_sleep property to true.
> 
> This will ensure that a warning is printed when trying to get the
> value from a context that potentially can't sleep.

LGTM.
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>

> Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> ---
>   drivers/gpio/gpio-pmic-eic-sprd.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> index 442968bb2490..f04a40288638 100644
> --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> @@ -353,6 +353,7 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
>   	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
>   	pmic_eic->chip.set = sprd_pmic_eic_set;
>   	pmic_eic->chip.get = sprd_pmic_eic_get;
> +	pmic_eic->chip.can_sleep = true;
>   
>   	irq = &pmic_eic->chip.irq;
>   	gpio_irq_chip_set_chip(irq, &pmic_eic_irq_chip);

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2024-01-02  7:29 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-21 12:25 [PATCH V2 0/2] gpio: pmic-eic-sprd: Modification of UNISOC Platform PMIC EIC Driver Wenhua Lin
2023-09-21 12:25 ` [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays maintain pmic eic Wenhua Lin
2023-09-27  7:21   ` Bartosz Golaszewski
2023-09-27  9:04   ` Baolin Wang
2023-09-27  9:24     ` Chunyan Zhang
2023-09-27  9:49       ` Baolin Wang
2023-09-28  9:00   ` Chunyan Zhang
2024-01-02  7:29     ` wenhua lin
2023-09-21 12:25 ` [PATCH V2 2/2] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip Wenhua Lin
2023-09-21 15:39   ` Andy Shevchenko
2023-09-27  7:13     ` Bartosz Golaszewski
2023-09-27  9:05   ` Baolin Wang

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