* [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl
@ 2017-01-27 16:15 Alexandre TORGUE
2017-01-27 16:15 ` [PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq Alexandre TORGUE
` (5 more replies)
0 siblings, 6 replies; 21+ messages in thread
From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw)
To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland,
Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard,
lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
This series adds support of a dedicated driver for STM32F469 MCU pinctroller.
This add generates some changes inside STM32 pinctrl driver and inside STM32
device tree.
Changes in STM32 pinctrl driver:
-------------------------------
- Add STM32F469 driver.
- Change STM32 pinctrl core in order to use "gpio-ranges" devicetree definitions.
Indeed, on STM32F469 there an hole in BANK J. We need to declare a gpio-ranges
in gpioj controller node to handle this hole.
Changes in STM32 device tree:
----------------------------
I propose a new architecture (a new file split) for pinmux definition:
- Create a common stm32f4-pinctrl.dtsi for pinmuxing definitions
which are common between STM32F429 and STM32F469 MCU.
- Create dedicated stm32fxxx-pinctrl.dtsi file for each MCU
(stm32f429-pinctrl.dtsi and stm32f469-pinctrl.dtsi) each one will
include stm32f4-pinctrl.dtsi. All differences (pinmuxing or GPIO
bank holes) will be put inside the dedicated files.
This series fix a locking issue when a gpio is used as IRQ.
Regards
Alex
Alexandre TORGUE (8):
pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
pinctrl: stm32: use gpio-ranges to declare bank range
Documentation: dt: Add bindings for STM32 pinctrl
includes: dt-bindings: Rename STM32F429 pinctrl DT bindings
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
ARM: Kconfig: Introduce MACH_STM32F469 flag
ARM: dts: stm32: create dedicated files for pinctrl definitions
.../bindings/pinctrl/st,stm32-pinctrl.txt | 57 +-
arch/arm/Kconfig | 5 +
arch/arm/boot/dts/stm32429i-eval.dts | 1 +
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 196 +++
arch/arm/boot/dts/stm32f429-disco.dts | 1 +
arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 106 ++
arch/arm/boot/dts/stm32f429.dtsi | 153 --
arch/arm/boot/dts/stm32f469-disco.dts | 1 +
arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 107 ++
drivers/pinctrl/stm32/Kconfig | 6 +
drivers/pinctrl/stm32/Makefile | 1 +
drivers/pinctrl/stm32/pinctrl-stm32.c | 129 +-
drivers/pinctrl/stm32/pinctrl-stm32f469.c | 1574 ++++++++++++++++++++
include/dt-bindings/pinctrl/stm32f4-pinfunc.h | 1302 ++++++++++++++++
include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1239 ---------------
15 files changed, 3414 insertions(+), 1464 deletions(-)
create mode 100644 arch/arm/boot/dts/stm32f4-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stm32f429-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stm32f469-pinctrl.dtsi
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f469.c
create mode 100644 include/dt-bindings/pinctrl/stm32f4-pinfunc.h
delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h
--
1.9.1
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^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq 2017-01-27 16:15 [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre TORGUE @ 2017-01-27 16:15 ` Alexandre TORGUE 2017-01-30 15:15 ` Linus Walleij [not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> ` (4 subsequent siblings) 5 siblings, 1 reply; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones Cc: linux-arm-kernel, devicetree, linux-gpio, linux-kernel Move gpio lock as irq from "domain alloc" callback to "domain activate" callback. It will allow to use gpiolib sysfs correctly. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index efc4371..b145431 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -236,6 +236,15 @@ static void stm32_gpio_domain_activate(struct irq_domain *d, struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id); + gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); +} + +static void stm32_gpio_domain_deactivate(struct irq_domain *d, + struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = d->host_data; + + gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); } static int stm32_gpio_domain_alloc(struct irq_domain *d, @@ -243,11 +252,9 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, unsigned int nr_irqs, void *data) { struct stm32_gpio_bank *bank = d->host_data; - struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); struct irq_fwspec *fwspec = data; struct irq_fwspec parent_fwspec; irq_hw_number_t hwirq; - int ret; hwirq = fwspec->param[0]; parent_fwspec.fwnode = d->parent->fwnode; @@ -258,35 +265,15 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, bank); - ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq); - if (ret) { - dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n", - bank->gpio_chip.label, hwirq); - return ret; - } - - ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); - if (ret) - gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq); - - return ret; -} - -static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, - unsigned int nr_irqs) -{ - struct stm32_gpio_bank *bank = d->host_data; - struct irq_data *data = irq_get_irq_data(virq); - - irq_domain_free_irqs_common(d, virq, nr_irqs); - gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq); + return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); } static const struct irq_domain_ops stm32_gpio_domain_ops = { .translate = stm32_gpio_domain_translate, .alloc = stm32_gpio_domain_alloc, - .free = stm32_gpio_domain_free, + .free = irq_domain_free_irqs_common, .activate = stm32_gpio_domain_activate, + .deactivate = stm32_gpio_domain_deactivate, }; /* Pinctrl functions */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq 2017-01-27 16:15 ` [PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq Alexandre TORGUE @ 2017-01-30 15:15 ` Linus Walleij 0 siblings, 0 replies; 21+ messages in thread From: Linus Walleij @ 2017-01-30 15:15 UTC (permalink / raw) To: Alexandre TORGUE Cc: Mark Rutland, devicetree@vger.kernel.org, Arnd Bergmann, linux-kernel@vger.kernel.org, Russell King, Patrice Chotard, linux-gpio@vger.kernel.org, Rob Herring, Maxime Coquelin, Olof Johansson, Lee Jones, linux-arm-kernel@lists.infradead.org On Fri, Jan 27, 2017 at 5:15 PM, Alexandre TORGUE <alexandre.torgue@st.com> wrote: > Move gpio lock as irq from "domain alloc" callback to "domain activate" > callback. It will allow to use gpiolib sysfs correctly. > > Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Patch applied. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>]
* [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range [not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> @ 2017-01-27 16:15 ` Alexandre TORGUE 2017-01-30 15:19 ` Linus Walleij 2017-01-27 16:15 ` [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl Alexandre TORGUE ` (2 subsequent siblings) 3 siblings, 1 reply; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones-QSEj5FYQhm4dnm+yROfE0A Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Use device tree entries to declare gpio range. It will allow to use no contiguous gpio bank and holes inside a bank. Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index b145431..d0a968a 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -589,7 +589,7 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, } range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); - bank = gpio_range_to_bank(range); + bank = gpiochip_get_data(range->gc); pin = stm32_gpio_pin(g->pin); mode = stm32_gpio_get_mode(function); @@ -604,7 +604,7 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned gpio, bool input) { - struct stm32_gpio_bank *bank = gpio_range_to_bank(range); + struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); int pin = stm32_gpio_pin(gpio); stm32_pmx_set_mode(bank, pin, !input, 0); @@ -761,7 +761,7 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, int offset, ret = 0; range = pinctrl_find_gpio_range_from_pin(pctldev, pin); - bank = gpio_range_to_bank(range); + bank = gpiochip_get_data(range->gc); offset = stm32_gpio_pin(pin); switch (param) { @@ -842,7 +842,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, bool val; range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); - bank = gpio_range_to_bank(range); + bank = gpiochip_get_data(range->gc); offset = stm32_gpio_pin(pin); stm32_pmx_get_mode(bank, offset, &mode, &alt); @@ -900,10 +900,12 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, int bank_nr = pctl->nbanks; struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; struct pinctrl_gpio_range *range = &bank->range; + struct of_phandle_args args; struct device *dev = pctl->dev; struct resource res; struct reset_control *rstc; - int err, npins; + unsigned int npins; + int err; rstc = of_reset_control_get(np, NULL); if (!IS_ERR(rstc)) @@ -928,28 +930,32 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, return err; } - npins = pctl->match_data->npins; - npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; - if (npins < 0) - return -EINVAL; - else if (npins > STM32_GPIO_PINS_PER_BANK) + if (of_property_read_u32(np, "ngpios", &npins)) npins = STM32_GPIO_PINS_PER_BANK; bank->gpio_chip = stm32_gpio_template; + + of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); + + if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) + bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; + else { + range->name = bank->gpio_chip.label; + range->id = bank_nr; + range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; + range->base = range->id * STM32_GPIO_PINS_PER_BANK; + range->npins = npins; + range->gc = &bank->gpio_chip; + pinctrl_add_gpio_range(pctl->pctl_dev, + &pctl->banks[bank_nr].range); + } + bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; bank->gpio_chip.ngpio = npins; bank->gpio_chip.of_node = np; bank->gpio_chip.parent = dev; spin_lock_init(&bank->lock); - of_property_read_string(np, "st,bank-name", &range->name); - bank->gpio_chip.label = range->name; - - range->id = bank_nr; - range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; - range->npins = bank->gpio_chip.ngpio; - range->gc = &bank->gpio_chip; - /* create irq hierarchical domain */ bank->fwnode = of_node_to_fwnode(np); @@ -966,7 +972,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, return err; } - dev_info(dev, "%s bank added\n", range->name); + dev_info(dev, "%s bank added\n", bank->gpio_chip.label); return 0; } @@ -1085,30 +1091,6 @@ int stm32_pctl_probe(struct platform_device *pdev) return ret; } - for_each_child_of_node(np, child) - if (of_property_read_bool(child, "gpio-controller")) - banks++; - - if (!banks) { - dev_err(dev, "at least one GPIO bank is required\n"); - return -EINVAL; - } - - pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), - GFP_KERNEL); - if (!pctl->banks) - return -ENOMEM; - - for_each_child_of_node(np, child) { - if (of_property_read_bool(child, "gpio-controller")) { - ret = stm32_gpiolib_register_bank(pctl, child); - if (ret) - return ret; - - pctl->nbanks++; - } - } - pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), GFP_KERNEL); if (!pins) @@ -1133,8 +1115,28 @@ int stm32_pctl_probe(struct platform_device *pdev) return PTR_ERR(pctl->pctl_dev); } - for (i = 0; i < pctl->nbanks; i++) - pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); + for_each_child_of_node(np, child) + if (of_property_read_bool(child, "gpio-controller")) + banks++; + + if (!banks) { + dev_err(dev, "at least one GPIO bank is required\n"); + return -EINVAL; + } + pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), + GFP_KERNEL); + if (!pctl->banks) + return -ENOMEM; + + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + ret = stm32_gpiolib_register_bank(pctl, child); + if (ret) + return ret; + + pctl->nbanks++; + } + } dev_info(dev, "Pinctrl STM32 initialized\n"); -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range 2017-01-27 16:15 ` [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range Alexandre TORGUE @ 2017-01-30 15:19 ` Linus Walleij 2017-01-30 16:29 ` Alexandre Torgue 0 siblings, 1 reply; 21+ messages in thread From: Linus Walleij @ 2017-01-30 15:19 UTC (permalink / raw) To: Alexandre TORGUE Cc: Maxime Coquelin, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, Lee Jones, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org On Fri, Jan 27, 2017 at 5:15 PM, Alexandre TORGUE <alexandre.torgue@st.com> wrote: > Use device tree entries to declare gpio range. It will allow to use > no contiguous gpio bank and holes inside a bank. > > Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> (...) > + of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); > + > + if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) > + bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; > + else { > + range->name = bank->gpio_chip.label; > + range->id = bank_nr; > + range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; > + range->base = range->id * STM32_GPIO_PINS_PER_BANK; > + range->npins = npins; > + range->gc = &bank->gpio_chip; > + pinctrl_add_gpio_range(pctl->pctl_dev, > + &pctl->banks[bank_nr].range); > + } Why are you doing this? There is already code in drivers/gpio/gpiolib-of.c to pick ranges from the device tree and add when you're adding the GPIO chips. Please use that or figure out what is needed to make it work for you instead of reimplementing it. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range 2017-01-30 15:19 ` Linus Walleij @ 2017-01-30 16:29 ` Alexandre Torgue 2017-02-01 15:01 ` Linus Walleij 0 siblings, 1 reply; 21+ messages in thread From: Alexandre Torgue @ 2017-01-30 16:29 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, devicetree@vger.kernel.org, Arnd Bergmann, linux-kernel@vger.kernel.org, Russell King, Patrice Chotard, linux-gpio@vger.kernel.org, Rob Herring, Maxime Coquelin, Olof Johansson, Lee Jones, linux-arm-kernel@lists.infradead.org Hi Linus, On 01/30/2017 04:19 PM, Linus Walleij wrote: > On Fri, Jan 27, 2017 at 5:15 PM, Alexandre TORGUE > <alexandre.torgue@st.com> wrote: > >> Use device tree entries to declare gpio range. It will allow to use >> no contiguous gpio bank and holes inside a bank. >> >> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> > > (...) >> + of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); >> + >> + if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) >> + bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; >> + else { >> + range->name = bank->gpio_chip.label; >> + range->id = bank_nr; >> + range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; >> + range->base = range->id * STM32_GPIO_PINS_PER_BANK; >> + range->npins = npins; >> + range->gc = &bank->gpio_chip; >> + pinctrl_add_gpio_range(pctl->pctl_dev, >> + &pctl->banks[bank_nr].range); >> + } I Keep the old way to get range in order to keep compatibility with older device tree (if no gpio ranges are defined). > > Why are you doing this? > > There is already code in drivers/gpio/gpiolib-of.c to pick ranges > from the device tree and add when you're adding the GPIO chips. Yes, If I declare gpio-ranges inside DT node, the range is well handled by the gpiolib. But in this condition I use gpio-ranges entry to get the pin base offset for the bank we are registering. For example, if there an hole between 2 banks (GPIOA, GPIOD, ...) I need to know at which pin offset the bank D starts. It is the only way I found. The "else" statement is here to get compatibility with older device tree (which don't use gpio-ranges entry). Regards Alex > > Please use that or figure out what is needed to make it work for > you instead of reimplementing it. > > Yours, > Linus Walleij > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range 2017-01-30 16:29 ` Alexandre Torgue @ 2017-02-01 15:01 ` Linus Walleij 2017-03-27 10:23 ` Alexandre Torgue 0 siblings, 1 reply; 21+ messages in thread From: Linus Walleij @ 2017-02-01 15:01 UTC (permalink / raw) To: Alexandre Torgue Cc: Maxime Coquelin, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, Lee Jones, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org On Mon, Jan 30, 2017 at 5:29 PM, Alexandre Torgue <alexandre.torgue@st.com> wrote: > On 01/30/2017 04:19 PM, Linus Walleij wrote: >>> + if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, >>> &args)) >>> + bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; >>> + else { >>> + range->name = bank->gpio_chip.label; >>> + range->id = bank_nr; >>> + range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; >>> + range->base = range->id * STM32_GPIO_PINS_PER_BANK; >>> + range->npins = npins; >>> + range->gc = &bank->gpio_chip; >>> + pinctrl_add_gpio_range(pctl->pctl_dev, >>> + &pctl->banks[bank_nr].range); >>> + } > > > I Keep the old way to get range in order to keep compatibility with older > device tree (if no gpio ranges are defined). Aha I understand. Sorry for my stupidity. Go ahead with this! Yours, Linus Walleij ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range 2017-02-01 15:01 ` Linus Walleij @ 2017-03-27 10:23 ` Alexandre Torgue 0 siblings, 0 replies; 21+ messages in thread From: Alexandre Torgue @ 2017-03-27 10:23 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, devicetree@vger.kernel.org, Arnd Bergmann, linux-kernel@vger.kernel.org, Russell King, Patrice Chotard, linux-gpio@vger.kernel.org, Rob Herring, Maxime Coquelin, Olof Johansson, Lee Jones, linux-arm-kernel@lists.infradead.org Hi Linus On 02/01/2017 04:01 PM, Linus Walleij wrote: > On Mon, Jan 30, 2017 at 5:29 PM, Alexandre Torgue > <alexandre.torgue@st.com> wrote: >> On 01/30/2017 04:19 PM, Linus Walleij wrote: > >>>> + if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, >>>> &args)) >>>> + bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; >>>> + else { >>>> + range->name = bank->gpio_chip.label; >>>> + range->id = bank_nr; >>>> + range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; >>>> + range->base = range->id * STM32_GPIO_PINS_PER_BANK; >>>> + range->npins = npins; >>>> + range->gc = &bank->gpio_chip; >>>> + pinctrl_add_gpio_range(pctl->pctl_dev, >>>> + &pctl->banks[bank_nr].range); >>>> + } >> >> >> I Keep the old way to get range in order to keep compatibility with older >> device tree (if no gpio ranges are defined). > > Aha I understand. Sorry for my stupidity. > > Go ahead with this! I saw an issue about this patch. It doesn't seem to be merged, so I will send a V2 only for this patch. Regards Alex > > Yours, > Linus Walleij > ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl [not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> 2017-01-27 16:15 ` [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range Alexandre TORGUE @ 2017-01-27 16:15 ` Alexandre TORGUE 2017-02-01 15:04 ` Rob Herring 2017-02-06 8:45 ` Linus Walleij 2017-01-27 16:15 ` [PATCH 4/8] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings Alexandre TORGUE 2017-01-27 16:15 ` [PATCH 8/8] ARM: dts: stm32: create dedicated files for pinctrl definitions Alexandre TORGUE 3 siblings, 2 replies; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones-QSEj5FYQhm4dnm+yROfE0A Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Adds "ngpios" and "gpio-ranges" bindings definition. Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index b24583a..25d9809 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -37,8 +37,23 @@ Optional properties: - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node which includes IRQ mux selection register, and the offset of the IRQ mux selection register. + - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less + than 16). + - gpio-ranges: Define a dedicated mapping between a pin-controller and + a gpio controller. Format is <&phandle a b c> with: + -(phandle): phandle of pin-controller. + -(a): gpio base offset in range. + -(b): pin base offset in range. + -(c): gpio count in range + This entry has to be used either if there are holes inside a bank: + GPIOB0/B1/B2/B14/B15 (see example 2) + or if banks are not contiguous: + GPIOA/B/C/E... + NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller + have to use a "gpio-ranges" entry. + More details in Documentation/devicetree/bindings/gpio/gpio.txt. -Example: +Example 1: #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> ... @@ -60,6 +75,43 @@ Example: pin-functions nodes follow... }; +Example 2: +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +... + + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOB"; + ngpios = 4; + gpio-ranges = <&pinctrl 0 16 3>, + <&pinctrl 14 30 2>; + }; + + + ... + pin-functions nodes follow... + }; + + Contents of function subnode node: ---------------------------------- Subnode format -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl 2017-01-27 16:15 ` [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl Alexandre TORGUE @ 2017-02-01 15:04 ` Rob Herring 2017-02-06 8:45 ` Linus Walleij 1 sibling, 0 replies; 21+ messages in thread From: Rob Herring @ 2017-02-01 15:04 UTC (permalink / raw) To: Alexandre TORGUE Cc: Maxime Coquelin, Linus Walleij, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones, linux-arm-kernel, devicetree, linux-gpio, linux-kernel On Fri, Jan 27, 2017 at 05:15:16PM +0100, Alexandre TORGUE wrote: > Adds "ngpios" and "gpio-ranges" bindings definition. > > Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl 2017-01-27 16:15 ` [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl Alexandre TORGUE 2017-02-01 15:04 ` Rob Herring @ 2017-02-06 8:45 ` Linus Walleij 1 sibling, 0 replies; 21+ messages in thread From: Linus Walleij @ 2017-02-06 8:45 UTC (permalink / raw) To: Alexandre TORGUE Cc: Maxime Coquelin, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, Lee Jones, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org On Fri, Jan 27, 2017 at 5:15 PM, Alexandre TORGUE <alexandre.torgue@st.com> wrote: > Adds "ngpios" and "gpio-ranges" bindings definition. > > Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Patch applied with Rob's ACK, amending subject as well. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 4/8] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings [not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> 2017-01-27 16:15 ` [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range Alexandre TORGUE 2017-01-27 16:15 ` [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl Alexandre TORGUE @ 2017-01-27 16:15 ` Alexandre TORGUE 2017-01-27 16:15 ` [PATCH 8/8] ARM: dts: stm32: create dedicated files for pinctrl definitions Alexandre TORGUE 3 siblings, 0 replies; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones-QSEj5FYQhm4dnm+yROfE0A Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA STM32F4 MCU series is composed of several SOC (STM32F429, STM32F469, ...). Most of muxing definition are identical. So to avoid to duplicate bindings definition, this patch create common definitions. Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index e4dae0e..d585288 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -47,7 +47,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +#include <dt-bindings/pinctrl/stm32f4-pinfunc.h> / { clocks { @@ -305,31 +305,31 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + pinmux = <STM32F4_PA9_FUNC_USART1_TX>; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + pinmux = <STM32F4_PA10_FUNC_USART1_RX>; bias-disable; }; }; usbotg_hs_pins_a: usbotg_hs@0 { pins { - pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>, - <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>, - <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>, - <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>, - <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>, - <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>, - <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>, - <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>, - <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>, - <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>, - <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>, - <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>; + pinmux = <STM32F4_PH4_FUNC_OTG_HS_ULPI_NXT>, + <STM32F4_PI11_FUNC_OTG_HS_ULPI_DIR>, + <STM32F4_PC0_FUNC_OTG_HS_ULPI_STP>, + <STM32F4_PA5_FUNC_OTG_HS_ULPI_CK>, + <STM32F4_PA3_FUNC_OTG_HS_ULPI_D0>, + <STM32F4_PB0_FUNC_OTG_HS_ULPI_D1>, + <STM32F4_PB1_FUNC_OTG_HS_ULPI_D2>, + <STM32F4_PB10_FUNC_OTG_HS_ULPI_D3>, + <STM32F4_PB11_FUNC_OTG_HS_ULPI_D4>, + <STM32F4_PB12_FUNC_OTG_HS_ULPI_D5>, + <STM32F4_PB13_FUNC_OTG_HS_ULPI_D6>, + <STM32F4_PB5_FUNC_OTG_HS_ULPI_D7>; bias-disable; drive-push-pull; slew-rate = <2>; @@ -338,20 +338,20 @@ ethernet_mii: mii@0 { pins { - pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, - <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, - <STM32F429_PC2_FUNC_ETH_MII_TXD2>, - <STM32F429_PB8_FUNC_ETH_MII_TXD3>, - <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>, - <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, - <STM32F429_PA2_FUNC_ETH_MDIO>, - <STM32F429_PC1_FUNC_ETH_MDC>, - <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, - <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, - <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, - <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, - <STM32F429_PH6_FUNC_ETH_MII_RXD2>, - <STM32F429_PH7_FUNC_ETH_MII_RXD3>; + pinmux = <STM32F4_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F4_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F4_PC2_FUNC_ETH_MII_TXD2>, + <STM32F4_PB8_FUNC_ETH_MII_TXD3>, + <STM32F4_PC3_FUNC_ETH_MII_TX_CLK>, + <STM32F4_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F4_PA2_FUNC_ETH_MDIO>, + <STM32F4_PC1_FUNC_ETH_MDC>, + <STM32F4_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F4_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F4_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F4_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, + <STM32F4_PH6_FUNC_ETH_MII_RXD2>, + <STM32F4_PH7_FUNC_ETH_MII_RXD3>; slew-rate = <2>; }; }; diff --git a/include/dt-bindings/pinctrl/stm32f4-pinfunc.h b/include/dt-bindings/pinctrl/stm32f4-pinfunc.h new file mode 100644 index 0000000..fae2ccf --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32f4-pinfunc.h @@ -0,0 +1,1302 @@ +#ifndef _DT_BINDINGS_STM32F4_PINFUNC_H +#define _DT_BINDINGS_STM32F4_PINFUNC_H + +#define STM32F4_PA0_FUNC_GPIO 0x0 +#define STM32F4_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 +#define STM32F4_PA0_FUNC_TIM5_CH1 0x3 +#define STM32F4_PA0_FUNC_TIM8_ETR 0x4 +#define STM32F4_PA0_FUNC_USART2_CTS 0x8 +#define STM32F4_PA0_FUNC_UART4_TX 0x9 +#define STM32F4_PA0_FUNC_ETH_MII_CRS 0xc +#define STM32F4_PA0_FUNC_EVENTOUT 0x10 +#define STM32F4_PA0_FUNC_ANALOG 0x11 + +#define STM32F4_PA1_FUNC_GPIO 0x100 +#define STM32F4_PA1_FUNC_TIM2_CH2 0x102 +#define STM32F4_PA1_FUNC_TIM5_CH2 0x103 +#define STM32F4_PA1_FUNC_USART2_RTS 0x108 +#define STM32F4_PA1_FUNC_UART4_RX 0x109 +#define STM32F469_PA1_FUNC_QUADSPI_BK1_IO3 0x10a +#define STM32F4_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c +#define STM32F469_PA1_FUNC_LCD_R2 0x10f +#define STM32F4_PA1_FUNC_EVENTOUT 0x110 +#define STM32F4_PA1_FUNC_ANALOG 0x111 + +#define STM32F4_PA2_FUNC_GPIO 0x200 +#define STM32F4_PA2_FUNC_TIM2_CH3 0x202 +#define STM32F4_PA2_FUNC_TIM5_CH3 0x203 +#define STM32F4_PA2_FUNC_TIM9_CH1 0x204 +#define STM32F4_PA2_FUNC_USART2_TX 0x208 +#define STM32F4_PA2_FUNC_ETH_MDIO 0x20c +#define STM32F469_PA2_FUNC_LCD_R1 0x20f +#define STM32F4_PA2_FUNC_EVENTOUT 0x210 +#define STM32F4_PA2_FUNC_ANALOG 0x211 + +#define STM32F4_PA3_FUNC_GPIO 0x300 +#define STM32F4_PA3_FUNC_TIM2_CH4 0x302 +#define STM32F4_PA3_FUNC_TIM5_CH4 0x303 +#define STM32F4_PA3_FUNC_TIM9_CH2 0x304 +#define STM32F4_PA3_FUNC_USART2_RX 0x308 +#define STM32F469_PA3_FUNC_LCD_B2 0x30a +#define STM32F4_PA3_FUNC_OTG_HS_ULPI_D0 0x30b +#define STM32F4_PA3_FUNC_ETH_MII_COL 0x30c +#define STM32F4_PA3_FUNC_LCD_B5 0x30f +#define STM32F4_PA3_FUNC_EVENTOUT 0x310 +#define STM32F4_PA3_FUNC_ANALOG 0x311 + +#define STM32F4_PA4_FUNC_GPIO 0x400 +#define STM32F4_PA4_FUNC_SPI1_NSS 0x406 +#define STM32F4_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 +#define STM32F4_PA4_FUNC_USART2_CK 0x408 +#define STM32F4_PA4_FUNC_OTG_HS_SOF 0x40d +#define STM32F4_PA4_FUNC_DCMI_HSYNC 0x40e +#define STM32F4_PA4_FUNC_LCD_VSYNC 0x40f +#define STM32F4_PA4_FUNC_EVENTOUT 0x410 +#define STM32F4_PA4_FUNC_ANALOG 0x411 + +#define STM32F4_PA5_FUNC_GPIO 0x500 +#define STM32F4_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 +#define STM32F4_PA5_FUNC_TIM8_CH1N 0x504 +#define STM32F4_PA5_FUNC_SPI1_SCK 0x506 +#define STM32F4_PA5_FUNC_OTG_HS_ULPI_CK 0x50b +#define STM32F469_PA5_FUNC_LCD_R4 0x50f +#define STM32F4_PA5_FUNC_EVENTOUT 0x510 +#define STM32F4_PA5_FUNC_ANALOG 0x511 + +#define STM32F4_PA6_FUNC_GPIO 0x600 +#define STM32F4_PA6_FUNC_TIM1_BKIN 0x602 +#define STM32F4_PA6_FUNC_TIM3_CH1 0x603 +#define STM32F4_PA6_FUNC_TIM8_BKIN 0x604 +#define STM32F4_PA6_FUNC_SPI1_MISO 0x606 +#define STM32F4_PA6_FUNC_TIM13_CH1 0x60a +#define STM32F4_PA6_FUNC_DCMI_PIXCLK 0x60e +#define STM32F4_PA6_FUNC_LCD_G2 0x60f +#define STM32F4_PA6_FUNC_EVENTOUT 0x610 +#define STM32F4_PA6_FUNC_ANALOG 0x611 + +#define STM32F4_PA7_FUNC_GPIO 0x700 +#define STM32F4_PA7_FUNC_TIM1_CH1N 0x702 +#define STM32F4_PA7_FUNC_TIM3_CH2 0x703 +#define STM32F4_PA7_FUNC_TIM8_CH1N 0x704 +#define STM32F4_PA7_FUNC_SPI1_MOSI 0x706 +#define STM32F4_PA7_FUNC_TIM14_CH1 0x70a +#define STM32F469_PA7_FUNC_QUADSPI_CLK 0x70b +#define STM32F4_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c +#define STM32F469_PA7_FUNC_FMC_SDNWE 0x70d +#define STM32F4_PA7_FUNC_EVENTOUT 0x710 +#define STM32F4_PA7_FUNC_ANALOG 0x711 + +#define STM32F4_PA8_FUNC_GPIO 0x800 +#define STM32F4_PA8_FUNC_MCO1 0x801 +#define STM32F4_PA8_FUNC_TIM1_CH1 0x802 +#define STM32F4_PA8_FUNC_I2C3_SCL 0x805 +#define STM32F4_PA8_FUNC_USART1_CK 0x808 +#define STM32F4_PA8_FUNC_OTG_FS_SOF 0x80b +#define STM32F4_PA8_FUNC_LCD_R6 0x80f +#define STM32F4_PA8_FUNC_EVENTOUT 0x810 +#define STM32F4_PA8_FUNC_ANALOG 0x811 + +#define STM32F4_PA9_FUNC_GPIO 0x900 +#define STM32F4_PA9_FUNC_TIM1_CH2 0x902 +#define STM32F4_PA9_FUNC_I2C3_SMBA 0x905 +#define STM32F469_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 +#define STM32F4_PA9_FUNC_USART1_TX 0x908 +#define STM32F4_PA9_FUNC_DCMI_D0 0x90e +#define STM32F4_PA9_FUNC_EVENTOUT 0x910 +#define STM32F4_PA9_FUNC_ANALOG 0x911 + +#define STM32F4_PA10_FUNC_GPIO 0xa00 +#define STM32F4_PA10_FUNC_TIM1_CH3 0xa02 +#define STM32F4_PA10_FUNC_USART1_RX 0xa08 +#define STM32F4_PA10_FUNC_OTG_FS_ID 0xa0b +#define STM32F4_PA10_FUNC_DCMI_D1 0xa0e +#define STM32F4_PA10_FUNC_EVENTOUT 0xa10 +#define STM32F4_PA10_FUNC_ANALOG 0xa11 + +#define STM32F4_PA11_FUNC_GPIO 0xb00 +#define STM32F4_PA11_FUNC_TIM1_CH4 0xb02 +#define STM32F4_PA11_FUNC_USART1_CTS 0xb08 +#define STM32F4_PA11_FUNC_CAN1_RX 0xb0a +#define STM32F4_PA11_FUNC_OTG_FS_DM 0xb0b +#define STM32F4_PA11_FUNC_LCD_R4 0xb0f +#define STM32F4_PA11_FUNC_EVENTOUT 0xb10 +#define STM32F4_PA11_FUNC_ANALOG 0xb11 + +#define STM32F4_PA12_FUNC_GPIO 0xc00 +#define STM32F4_PA12_FUNC_TIM1_ETR 0xc02 +#define STM32F4_PA12_FUNC_USART1_RTS 0xc08 +#define STM32F4_PA12_FUNC_CAN1_TX 0xc0a +#define STM32F4_PA12_FUNC_OTG_FS_DP 0xc0b +#define STM32F4_PA12_FUNC_LCD_R5 0xc0f +#define STM32F4_PA12_FUNC_EVENTOUT 0xc10 +#define STM32F4_PA12_FUNC_ANALOG 0xc11 + +#define STM32F4_PA13_FUNC_GPIO 0xd00 +#define STM32F4_PA13_FUNC_JTMS_SWDIO 0xd01 +#define STM32F4_PA13_FUNC_EVENTOUT 0xd10 +#define STM32F4_PA13_FUNC_ANALOG 0xd11 + +#define STM32F4_PA14_FUNC_GPIO 0xe00 +#define STM32F4_PA14_FUNC_JTCK_SWCLK 0xe01 +#define STM32F4_PA14_FUNC_EVENTOUT 0xe10 +#define STM32F4_PA14_FUNC_ANALOG 0xe11 + +#define STM32F4_PA15_FUNC_GPIO 0xf00 +#define STM32F4_PA15_FUNC_JTDI 0xf01 +#define STM32F4_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 +#define STM32F4_PA15_FUNC_SPI1_NSS 0xf06 +#define STM32F4_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 +#define STM32F4_PA15_FUNC_EVENTOUT 0xf10 +#define STM32F4_PA15_FUNC_ANALOG 0xf11 + + + +#define STM32F4_PB0_FUNC_GPIO 0x1000 +#define STM32F4_PB0_FUNC_TIM1_CH2N 0x1002 +#define STM32F4_PB0_FUNC_TIM3_CH3 0x1003 +#define STM32F4_PB0_FUNC_TIM8_CH2N 0x1004 +#define STM32F4_PB0_FUNC_LCD_R3 0x100a +#define STM32F4_PB0_FUNC_OTG_HS_ULPI_D1 0x100b +#define STM32F4_PB0_FUNC_ETH_MII_RXD2 0x100c +#define STM32F469_PB0_FUNC_LCD_G1 0x100f +#define STM32F4_PB0_FUNC_EVENTOUT 0x1010 +#define STM32F4_PB0_FUNC_ANALOG 0x1011 + +#define STM32F4_PB1_FUNC_GPIO 0x1100 +#define STM32F4_PB1_FUNC_TIM1_CH3N 0x1102 +#define STM32F4_PB1_FUNC_TIM3_CH4 0x1103 +#define STM32F4_PB1_FUNC_TIM8_CH3N 0x1104 +#define STM32F4_PB1_FUNC_LCD_R6 0x110a +#define STM32F4_PB1_FUNC_OTG_HS_ULPI_D2 0x110b +#define STM32F4_PB1_FUNC_ETH_MII_RXD3 0x110c +#define STM32F469_PB1_FUNC_LCD_G0 0x110f +#define STM32F4_PB1_FUNC_EVENTOUT 0x1110 +#define STM32F4_PB1_FUNC_ANALOG 0x1111 + +#define STM32F4_PB2_FUNC_GPIO 0x1200 +#define STM32F4_PB2_FUNC_EVENTOUT 0x1210 +#define STM32F4_PB2_FUNC_ANALOG 0x1211 + +#define STM32F4_PB3_FUNC_GPIO 0x1300 +#define STM32F4_PB3_FUNC_JTDO_TRACESWO 0x1301 +#define STM32F4_PB3_FUNC_TIM2_CH2 0x1302 +#define STM32F4_PB3_FUNC_SPI1_SCK 0x1306 +#define STM32F4_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 +#define STM32F4_PB3_FUNC_EVENTOUT 0x1310 +#define STM32F4_PB3_FUNC_ANALOG 0x1311 + +#define STM32F4_PB4_FUNC_GPIO 0x1400 +#define STM32F4_PB4_FUNC_NJTRST 0x1401 +#define STM32F4_PB4_FUNC_TIM3_CH1 0x1403 +#define STM32F4_PB4_FUNC_SPI1_MISO 0x1406 +#define STM32F4_PB4_FUNC_SPI3_MISO 0x1407 +#define STM32F4_PB4_FUNC_I2S3EXT_SD 0x1408 +#define STM32F4_PB4_FUNC_EVENTOUT 0x1410 +#define STM32F4_PB4_FUNC_ANALOG 0x1411 + +#define STM32F4_PB5_FUNC_GPIO 0x1500 +#define STM32F4_PB5_FUNC_TIM3_CH2 0x1503 +#define STM32F4_PB5_FUNC_I2C1_SMBA 0x1505 +#define STM32F4_PB5_FUNC_SPI1_MOSI 0x1506 +#define STM32F4_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 +#define STM32F4_PB5_FUNC_CAN2_RX 0x150a +#define STM32F4_PB5_FUNC_OTG_HS_ULPI_D7 0x150b +#define STM32F4_PB5_FUNC_ETH_PPS_OUT 0x150c +#define STM32F4_PB5_FUNC_FMC_SDCKE1 0x150d +#define STM32F4_PB5_FUNC_DCMI_D10 0x150e +#define STM32F469_PB5_FUNC_LCD_G7 0x150f +#define STM32F4_PB5_FUNC_EVENTOUT 0x1510 +#define STM32F4_PB5_FUNC_ANALOG 0x1511 + +#define STM32F4_PB6_FUNC_GPIO 0x1600 +#define STM32F4_PB6_FUNC_TIM4_CH1 0x1603 +#define STM32F4_PB6_FUNC_I2C1_SCL 0x1605 +#define STM32F4_PB6_FUNC_USART1_TX 0x1608 +#define STM32F4_PB6_FUNC_CAN2_TX 0x160a +#define STM32F469_PB6_FUNC_QUADSPI_BK1_NCS 0x160b +#define STM32F4_PB6_FUNC_FMC_SDNE1 0x160d +#define STM32F4_PB6_FUNC_DCMI_D5 0x160e +#define STM32F4_PB6_FUNC_EVENTOUT 0x1610 +#define STM32F4_PB6_FUNC_ANALOG 0x1611 + +#define STM32F4_PB7_FUNC_GPIO 0x1700 +#define STM32F4_PB7_FUNC_TIM4_CH2 0x1703 +#define STM32F4_PB7_FUNC_I2C1_SDA 0x1705 +#define STM32F4_PB7_FUNC_USART1_RX 0x1708 +#define STM32F4_PB7_FUNC_FMC_NL 0x170d +#define STM32F4_PB7_FUNC_DCMI_VSYNC 0x170e +#define STM32F4_PB7_FUNC_EVENTOUT 0x1710 +#define STM32F4_PB7_FUNC_ANALOG 0x1711 + +#define STM32F4_PB8_FUNC_GPIO 0x1800 +#define STM32F4_PB8_FUNC_TIM4_CH3 0x1803 +#define STM32F4_PB8_FUNC_TIM10_CH1 0x1804 +#define STM32F4_PB8_FUNC_I2C1_SCL 0x1805 +#define STM32F4_PB8_FUNC_CAN1_RX 0x180a +#define STM32F4_PB8_FUNC_ETH_MII_TXD3 0x180c +#define STM32F4_PB8_FUNC_SDIO_D4 0x180d +#define STM32F4_PB8_FUNC_DCMI_D6 0x180e +#define STM32F4_PB8_FUNC_LCD_B6 0x180f +#define STM32F4_PB8_FUNC_EVENTOUT 0x1810 +#define STM32F4_PB8_FUNC_ANALOG 0x1811 + +#define STM32F4_PB9_FUNC_GPIO 0x1900 +#define STM32F4_PB9_FUNC_TIM4_CH4 0x1903 +#define STM32F4_PB9_FUNC_TIM11_CH1 0x1904 +#define STM32F4_PB9_FUNC_I2C1_SDA 0x1905 +#define STM32F4_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 +#define STM32F4_PB9_FUNC_CAN1_TX 0x190a +#define STM32F4_PB9_FUNC_SDIO_D5 0x190d +#define STM32F4_PB9_FUNC_DCMI_D7 0x190e +#define STM32F4_PB9_FUNC_LCD_B7 0x190f +#define STM32F4_PB9_FUNC_EVENTOUT 0x1910 +#define STM32F4_PB9_FUNC_ANALOG 0x1911 + +#define STM32F4_PB10_FUNC_GPIO 0x1a00 +#define STM32F4_PB10_FUNC_TIM2_CH3 0x1a02 +#define STM32F4_PB10_FUNC_I2C2_SCL 0x1a05 +#define STM32F4_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 +#define STM32F4_PB10_FUNC_USART3_TX 0x1a08 +#define STM32F469_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a +#define STM32F4_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b +#define STM32F4_PB10_FUNC_ETH_MII_RX_ER 0x1a0c +#define STM32F4_PB10_FUNC_LCD_G4 0x1a0f +#define STM32F4_PB10_FUNC_EVENTOUT 0x1a10 +#define STM32F4_PB10_FUNC_ANALOG 0x1a11 + +#define STM32F4_PB11_FUNC_GPIO 0x1b00 +#define STM32F4_PB11_FUNC_TIM2_CH4 0x1b02 +#define STM32F4_PB11_FUNC_I2C2_SDA 0x1b05 +#define STM32F4_PB11_FUNC_USART3_RX 0x1b08 +#define STM32F4_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b +#define STM32F4_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c +#define STM32F469_PB11_FUNC_DSIHOST_TE 0x1b0e +#define STM32F4_PB11_FUNC_LCD_G5 0x1b0f +#define STM32F4_PB11_FUNC_EVENTOUT 0x1b10 +#define STM32F4_PB11_FUNC_ANALOG 0x1b11 + +#define STM32F4_PB12_FUNC_GPIO 0x1c00 +#define STM32F4_PB12_FUNC_TIM1_BKIN 0x1c02 +#define STM32F4_PB12_FUNC_I2C2_SMBA 0x1c05 +#define STM32F4_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 +#define STM32F4_PB12_FUNC_USART3_CK 0x1c08 +#define STM32F4_PB12_FUNC_CAN2_RX 0x1c0a +#define STM32F4_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b +#define STM32F4_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c +#define STM32F4_PB12_FUNC_OTG_HS_ID 0x1c0d +#define STM32F4_PB12_FUNC_EVENTOUT 0x1c10 +#define STM32F4_PB12_FUNC_ANALOG 0x1c11 + +#define STM32F4_PB13_FUNC_GPIO 0x1d00 +#define STM32F4_PB13_FUNC_TIM1_CH1N 0x1d02 +#define STM32F4_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 +#define STM32F4_PB13_FUNC_USART3_CTS 0x1d08 +#define STM32F4_PB13_FUNC_CAN2_TX 0x1d0a +#define STM32F4_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b +#define STM32F4_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c +#define STM32F4_PB13_FUNC_EVENTOUT 0x1d10 +#define STM32F4_PB13_FUNC_ANALOG 0x1d11 + +#define STM32F4_PB14_FUNC_GPIO 0x1e00 +#define STM32F4_PB14_FUNC_TIM1_CH2N 0x1e02 +#define STM32F4_PB14_FUNC_TIM8_CH2N 0x1e04 +#define STM32F4_PB14_FUNC_SPI2_MISO 0x1e06 +#define STM32F4_PB14_FUNC_I2S2EXT_SD 0x1e07 +#define STM32F4_PB14_FUNC_USART3_RTS 0x1e08 +#define STM32F4_PB14_FUNC_TIM12_CH1 0x1e0a +#define STM32F4_PB14_FUNC_OTG_HS_DM 0x1e0d +#define STM32F4_PB14_FUNC_EVENTOUT 0x1e10 +#define STM32F4_PB14_FUNC_ANALOG 0x1e11 + +#define STM32F4_PB15_FUNC_GPIO 0x1f00 +#define STM32F4_PB15_FUNC_RTC_REFIN 0x1f01 +#define STM32F4_PB15_FUNC_TIM1_CH3N 0x1f02 +#define STM32F4_PB15_FUNC_TIM8_CH3N 0x1f04 +#define STM32F4_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 +#define STM32F4_PB15_FUNC_TIM12_CH2 0x1f0a +#define STM32F4_PB15_FUNC_OTG_HS_DP 0x1f0d +#define STM32F4_PB15_FUNC_EVENTOUT 0x1f10 +#define STM32F4_PB15_FUNC_ANALOG 0x1f11 + + + +#define STM32F4_PC0_FUNC_GPIO 0x2000 +#define STM32F4_PC0_FUNC_OTG_HS_ULPI_STP 0x200b +#define STM32F4_PC0_FUNC_FMC_SDNWE 0x200d +#define STM32F469_PC0_FUNC_LCD_R5 0x200f +#define STM32F4_PC0_FUNC_EVENTOUT 0x2010 +#define STM32F4_PC0_FUNC_ANALOG 0x2011 + +#define STM32F4_PC1_FUNC_GPIO 0x2100 +#define STM32F469_PC1_FUNC_TRACED0 0x2101 +#define STM32F469_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106 +#define STM32F469_PC1_FUNC_SAI1_SD_A 0x2107 +#define STM32F4_PC1_FUNC_ETH_MDC 0x210c +#define STM32F4_PC1_FUNC_EVENTOUT 0x2110 +#define STM32F4_PC1_FUNC_ANALOG 0x2111 + +#define STM32F4_PC2_FUNC_GPIO 0x2200 +#define STM32F4_PC2_FUNC_SPI2_MISO 0x2206 +#define STM32F4_PC2_FUNC_I2S2EXT_SD 0x2207 +#define STM32F4_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b +#define STM32F4_PC2_FUNC_ETH_MII_TXD2 0x220c +#define STM32F4_PC2_FUNC_FMC_SDNE0 0x220d +#define STM32F4_PC2_FUNC_EVENTOUT 0x2210 +#define STM32F4_PC2_FUNC_ANALOG 0x2211 + +#define STM32F4_PC3_FUNC_GPIO 0x2300 +#define STM32F4_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 +#define STM32F4_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b +#define STM32F4_PC3_FUNC_ETH_MII_TX_CLK 0x230c +#define STM32F4_PC3_FUNC_FMC_SDCKE0 0x230d +#define STM32F4_PC3_FUNC_EVENTOUT 0x2310 +#define STM32F4_PC3_FUNC_ANALOG 0x2311 + +#define STM32F4_PC4_FUNC_GPIO 0x2400 +#define STM32F4_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c +#define STM32F469_PC4_FUNC_FMC_SDNE0 0x240d +#define STM32F4_PC4_FUNC_EVENTOUT 0x2410 +#define STM32F4_PC4_FUNC_ANALOG 0x2411 + +#define STM32F4_PC5_FUNC_GPIO 0x2500 +#define STM32F4_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c +#define STM32F469_PC5_FUNC_FMC_SDCKE0 0x250d +#define STM32F4_PC5_FUNC_EVENTOUT 0x2510 +#define STM32F4_PC5_FUNC_ANALOG 0x2511 + +#define STM32F4_PC6_FUNC_GPIO 0x2600 +#define STM32F4_PC6_FUNC_TIM3_CH1 0x2603 +#define STM32F4_PC6_FUNC_TIM8_CH1 0x2604 +#define STM32F4_PC6_FUNC_I2S2_MCK 0x2606 +#define STM32F4_PC6_FUNC_USART6_TX 0x2609 +#define STM32F4_PC6_FUNC_SDIO_D6 0x260d +#define STM32F4_PC6_FUNC_DCMI_D0 0x260e +#define STM32F4_PC6_FUNC_LCD_HSYNC 0x260f +#define STM32F4_PC6_FUNC_EVENTOUT 0x2610 +#define STM32F4_PC6_FUNC_ANALOG 0x2611 + +#define STM32F4_PC7_FUNC_GPIO 0x2700 +#define STM32F4_PC7_FUNC_TIM3_CH2 0x2703 +#define STM32F4_PC7_FUNC_TIM8_CH2 0x2704 +#define STM32F4_PC7_FUNC_I2S3_MCK 0x2707 +#define STM32F4_PC7_FUNC_USART6_RX 0x2709 +#define STM32F4_PC7_FUNC_SDIO_D7 0x270d +#define STM32F4_PC7_FUNC_DCMI_D1 0x270e +#define STM32F4_PC7_FUNC_LCD_G6 0x270f +#define STM32F4_PC7_FUNC_EVENTOUT 0x2710 +#define STM32F4_PC7_FUNC_ANALOG 0x2711 + +#define STM32F4_PC8_FUNC_GPIO 0x2800 +#define STM32F469_PC8_FUNC_TRACED1 0x2801 +#define STM32F4_PC8_FUNC_TIM3_CH3 0x2803 +#define STM32F4_PC8_FUNC_TIM8_CH3 0x2804 +#define STM32F4_PC8_FUNC_USART6_CK 0x2809 +#define STM32F4_PC8_FUNC_SDIO_D0 0x280d +#define STM32F4_PC8_FUNC_DCMI_D2 0x280e +#define STM32F4_PC8_FUNC_EVENTOUT 0x2810 +#define STM32F4_PC8_FUNC_ANALOG 0x2811 + +#define STM32F4_PC9_FUNC_GPIO 0x2900 +#define STM32F4_PC9_FUNC_MCO2 0x2901 +#define STM32F4_PC9_FUNC_TIM3_CH4 0x2903 +#define STM32F4_PC9_FUNC_TIM8_CH4 0x2904 +#define STM32F4_PC9_FUNC_I2C3_SDA 0x2905 +#define STM32F4_PC9_FUNC_I2S_CKIN 0x2906 +#define STM32F469_PC9_FUNC_QUADSPI_BK1_IO0 0x290a +#define STM32F4_PC9_FUNC_SDIO_D1 0x290d +#define STM32F4_PC9_FUNC_DCMI_D3 0x290e +#define STM32F4_PC9_FUNC_EVENTOUT 0x2910 +#define STM32F4_PC9_FUNC_ANALOG 0x2911 + +#define STM32F4_PC10_FUNC_GPIO 0x2a00 +#define STM32F4_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 +#define STM32F4_PC10_FUNC_USART3_TX 0x2a08 +#define STM32F4_PC10_FUNC_UART4_TX 0x2a09 +#define STM32F469_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a +#define STM32F4_PC10_FUNC_SDIO_D2 0x2a0d +#define STM32F4_PC10_FUNC_DCMI_D8 0x2a0e +#define STM32F4_PC10_FUNC_LCD_R2 0x2a0f +#define STM32F4_PC10_FUNC_EVENTOUT 0x2a10 +#define STM32F4_PC10_FUNC_ANALOG 0x2a11 + +#define STM32F4_PC11_FUNC_GPIO 0x2b00 +#define STM32F4_PC11_FUNC_I2S3EXT_SD 0x2b06 +#define STM32F4_PC11_FUNC_SPI3_MISO 0x2b07 +#define STM32F4_PC11_FUNC_USART3_RX 0x2b08 +#define STM32F4_PC11_FUNC_UART4_RX 0x2b09 +#define STM32F469_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a +#define STM32F4_PC11_FUNC_SDIO_D3 0x2b0d +#define STM32F4_PC11_FUNC_DCMI_D4 0x2b0e +#define STM32F4_PC11_FUNC_EVENTOUT 0x2b10 +#define STM32F4_PC11_FUNC_ANALOG 0x2b11 + +#define STM32F4_PC12_FUNC_GPIO 0x2c00 +#define STM32F469_PC12_FUNC_TRACED3 0x2c01 +#define STM32F4_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 +#define STM32F4_PC12_FUNC_USART3_CK 0x2c08 +#define STM32F4_PC12_FUNC_UART5_TX 0x2c09 +#define STM32F4_PC12_FUNC_SDIO_CK 0x2c0d +#define STM32F4_PC12_FUNC_DCMI_D9 0x2c0e +#define STM32F4_PC12_FUNC_EVENTOUT 0x2c10 +#define STM32F4_PC12_FUNC_ANALOG 0x2c11 + +#define STM32F4_PC13_FUNC_GPIO 0x2d00 +#define STM32F4_PC13_FUNC_EVENTOUT 0x2d10 +#define STM32F4_PC13_FUNC_ANALOG 0x2d11 + +#define STM32F4_PC14_FUNC_GPIO 0x2e00 +#define STM32F4_PC14_FUNC_EVENTOUT 0x2e10 +#define STM32F4_PC14_FUNC_ANALOG 0x2e11 + +#define STM32F4_PC15_FUNC_GPIO 0x2f00 +#define STM32F4_PC15_FUNC_EVENTOUT 0x2f10 +#define STM32F4_PC15_FUNC_ANALOG 0x2f11 + + + +#define STM32F4_PD0_FUNC_GPIO 0x3000 +#define STM32F4_PD0_FUNC_CAN1_RX 0x300a +#define STM32F4_PD0_FUNC_FMC_D2 0x300d +#define STM32F4_PD0_FUNC_EVENTOUT 0x3010 +#define STM32F4_PD0_FUNC_ANALOG 0x3011 + +#define STM32F4_PD1_FUNC_GPIO 0x3100 +#define STM32F4_PD1_FUNC_CAN1_TX 0x310a +#define STM32F4_PD1_FUNC_FMC_D3 0x310d +#define STM32F4_PD1_FUNC_EVENTOUT 0x3110 +#define STM32F4_PD1_FUNC_ANALOG 0x3111 + +#define STM32F4_PD2_FUNC_GPIO 0x3200 +#define STM32F469_PD2_FUNC_TRACED2 0x3201 +#define STM32F4_PD2_FUNC_TIM3_ETR 0x3203 +#define STM32F4_PD2_FUNC_UART5_RX 0x3209 +#define STM32F4_PD2_FUNC_SDIO_CMD 0x320d +#define STM32F4_PD2_FUNC_DCMI_D11 0x320e +#define STM32F4_PD2_FUNC_EVENTOUT 0x3210 +#define STM32F4_PD2_FUNC_ANALOG 0x3211 + +#define STM32F4_PD3_FUNC_GPIO 0x3300 +#define STM32F4_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 +#define STM32F4_PD3_FUNC_USART2_CTS 0x3308 +#define STM32F4_PD3_FUNC_FMC_CLK 0x330d +#define STM32F4_PD3_FUNC_DCMI_D5 0x330e +#define STM32F4_PD3_FUNC_LCD_G7 0x330f +#define STM32F4_PD3_FUNC_EVENTOUT 0x3310 +#define STM32F4_PD3_FUNC_ANALOG 0x3311 + +#define STM32F4_PD4_FUNC_GPIO 0x3400 +#define STM32F4_PD4_FUNC_USART2_RTS 0x3408 +#define STM32F4_PD4_FUNC_FMC_NOE 0x340d +#define STM32F4_PD4_FUNC_EVENTOUT 0x3410 +#define STM32F4_PD4_FUNC_ANALOG 0x3411 + +#define STM32F4_PD5_FUNC_GPIO 0x3500 +#define STM32F4_PD5_FUNC_USART2_TX 0x3508 +#define STM32F4_PD5_FUNC_FMC_NWE 0x350d +#define STM32F4_PD5_FUNC_EVENTOUT 0x3510 +#define STM32F4_PD5_FUNC_ANALOG 0x3511 + +#define STM32F4_PD6_FUNC_GPIO 0x3600 +#define STM32F4_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 +#define STM32F4_PD6_FUNC_SAI1_SD_A 0x3607 +#define STM32F4_PD6_FUNC_USART2_RX 0x3608 +#define STM32F4_PD6_FUNC_FMC_NWAIT 0x360d +#define STM32F4_PD6_FUNC_DCMI_D10 0x360e +#define STM32F4_PD6_FUNC_LCD_B2 0x360f +#define STM32F4_PD6_FUNC_EVENTOUT 0x3610 +#define STM32F4_PD6_FUNC_ANALOG 0x3611 + +#define STM32F4_PD7_FUNC_GPIO 0x3700 +#define STM32F4_PD7_FUNC_USART2_CK 0x3708 +#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d +#define STM32F469_PD7_FUNC_FMC_NE1 0x370d +#define STM32F4_PD7_FUNC_EVENTOUT 0x3710 +#define STM32F4_PD7_FUNC_ANALOG 0x3711 + +#define STM32F4_PD8_FUNC_GPIO 0x3800 +#define STM32F4_PD8_FUNC_USART3_TX 0x3808 +#define STM32F4_PD8_FUNC_FMC_D13 0x380d +#define STM32F4_PD8_FUNC_EVENTOUT 0x3810 +#define STM32F4_PD8_FUNC_ANALOG 0x3811 + +#define STM32F4_PD9_FUNC_GPIO 0x3900 +#define STM32F4_PD9_FUNC_USART3_RX 0x3908 +#define STM32F4_PD9_FUNC_FMC_D14 0x390d +#define STM32F4_PD9_FUNC_EVENTOUT 0x3910 +#define STM32F4_PD9_FUNC_ANALOG 0x3911 + +#define STM32F4_PD10_FUNC_GPIO 0x3a00 +#define STM32F4_PD10_FUNC_USART3_CK 0x3a08 +#define STM32F4_PD10_FUNC_FMC_D15 0x3a0d +#define STM32F4_PD10_FUNC_LCD_B3 0x3a0f +#define STM32F4_PD10_FUNC_EVENTOUT 0x3a10 +#define STM32F4_PD10_FUNC_ANALOG 0x3a11 + +#define STM32F4_PD11_FUNC_GPIO 0x3b00 +#define STM32F4_PD11_FUNC_USART3_CTS 0x3b08 +#define STM32F469_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a +#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d +#define STM32F469_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d +#define STM32F4_PD11_FUNC_EVENTOUT 0x3b10 +#define STM32F4_PD11_FUNC_ANALOG 0x3b11 + +#define STM32F4_PD12_FUNC_GPIO 0x3c00 +#define STM32F4_PD12_FUNC_TIM4_CH1 0x3c03 +#define STM32F4_PD12_FUNC_USART3_RTS 0x3c08 +#define STM32F469_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a +#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d +#define STM32F469_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d +#define STM32F4_PD12_FUNC_EVENTOUT 0x3c10 +#define STM32F4_PD12_FUNC_ANALOG 0x3c11 + +#define STM32F4_PD13_FUNC_GPIO 0x3d00 +#define STM32F4_PD13_FUNC_TIM4_CH2 0x3d03 +#define STM32F469_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a +#define STM32F4_PD13_FUNC_FMC_A18 0x3d0d +#define STM32F4_PD13_FUNC_EVENTOUT 0x3d10 +#define STM32F4_PD13_FUNC_ANALOG 0x3d11 + +#define STM32F4_PD14_FUNC_GPIO 0x3e00 +#define STM32F4_PD14_FUNC_TIM4_CH3 0x3e03 +#define STM32F4_PD14_FUNC_FMC_D0 0x3e0d +#define STM32F4_PD14_FUNC_EVENTOUT 0x3e10 +#define STM32F4_PD14_FUNC_ANALOG 0x3e11 + +#define STM32F4_PD15_FUNC_GPIO 0x3f00 +#define STM32F4_PD15_FUNC_TIM4_CH4 0x3f03 +#define STM32F4_PD15_FUNC_FMC_D1 0x3f0d +#define STM32F4_PD15_FUNC_EVENTOUT 0x3f10 +#define STM32F4_PD15_FUNC_ANALOG 0x3f11 + + + +#define STM32F4_PE0_FUNC_GPIO 0x4000 +#define STM32F4_PE0_FUNC_TIM4_ETR 0x4003 +#define STM32F4_PE0_FUNC_UART8_RX 0x4009 +#define STM32F4_PE0_FUNC_FMC_NBL0 0x400d +#define STM32F4_PE0_FUNC_DCMI_D2 0x400e +#define STM32F4_PE0_FUNC_EVENTOUT 0x4010 +#define STM32F4_PE0_FUNC_ANALOG 0x4011 + +#define STM32F4_PE1_FUNC_GPIO 0x4100 +#define STM32F4_PE1_FUNC_UART8_TX 0x4109 +#define STM32F4_PE1_FUNC_FMC_NBL1 0x410d +#define STM32F4_PE1_FUNC_DCMI_D3 0x410e +#define STM32F4_PE1_FUNC_EVENTOUT 0x4110 +#define STM32F4_PE1_FUNC_ANALOG 0x4111 + +#define STM32F4_PE2_FUNC_GPIO 0x4200 +#define STM32F4_PE2_FUNC_TRACECLK 0x4201 +#define STM32F4_PE2_FUNC_SPI4_SCK 0x4206 +#define STM32F4_PE2_FUNC_SAI1_MCLK_A 0x4207 +#define STM32F469_PE2_FUNC_QUADSPI_BK1_IO2 0x420a +#define STM32F4_PE2_FUNC_ETH_MII_TXD3 0x420c +#define STM32F4_PE2_FUNC_FMC_A23 0x420d +#define STM32F4_PE2_FUNC_EVENTOUT 0x4210 +#define STM32F4_PE2_FUNC_ANALOG 0x4211 + +#define STM32F4_PE3_FUNC_GPIO 0x4300 +#define STM32F4_PE3_FUNC_TRACED0 0x4301 +#define STM32F4_PE3_FUNC_SAI1_SD_B 0x4307 +#define STM32F4_PE3_FUNC_FMC_A19 0x430d +#define STM32F4_PE3_FUNC_EVENTOUT 0x4310 +#define STM32F4_PE3_FUNC_ANALOG 0x4311 + +#define STM32F4_PE4_FUNC_GPIO 0x4400 +#define STM32F4_PE4_FUNC_TRACED1 0x4401 +#define STM32F4_PE4_FUNC_SPI4_NSS 0x4406 +#define STM32F4_PE4_FUNC_SAI1_FS_A 0x4407 +#define STM32F4_PE4_FUNC_FMC_A20 0x440d +#define STM32F4_PE4_FUNC_DCMI_D4 0x440e +#define STM32F4_PE4_FUNC_LCD_B0 0x440f +#define STM32F4_PE4_FUNC_EVENTOUT 0x4410 +#define STM32F4_PE4_FUNC_ANALOG 0x4411 + +#define STM32F4_PE5_FUNC_GPIO 0x4500 +#define STM32F4_PE5_FUNC_TRACED2 0x4501 +#define STM32F4_PE5_FUNC_TIM9_CH1 0x4504 +#define STM32F4_PE5_FUNC_SPI4_MISO 0x4506 +#define STM32F4_PE5_FUNC_SAI1_SCK_A 0x4507 +#define STM32F4_PE5_FUNC_FMC_A21 0x450d +#define STM32F4_PE5_FUNC_DCMI_D6 0x450e +#define STM32F4_PE5_FUNC_LCD_G0 0x450f +#define STM32F4_PE5_FUNC_EVENTOUT 0x4510 +#define STM32F4_PE5_FUNC_ANALOG 0x4511 + +#define STM32F4_PE6_FUNC_GPIO 0x4600 +#define STM32F4_PE6_FUNC_TRACED3 0x4601 +#define STM32F4_PE6_FUNC_TIM9_CH2 0x4604 +#define STM32F4_PE6_FUNC_SPI4_MOSI 0x4606 +#define STM32F4_PE6_FUNC_SAI1_SD_A 0x4607 +#define STM32F4_PE6_FUNC_FMC_A22 0x460d +#define STM32F4_PE6_FUNC_DCMI_D7 0x460e +#define STM32F4_PE6_FUNC_LCD_G1 0x460f +#define STM32F4_PE6_FUNC_EVENTOUT 0x4610 +#define STM32F4_PE6_FUNC_ANALOG 0x4611 + +#define STM32F4_PE7_FUNC_GPIO 0x4700 +#define STM32F4_PE7_FUNC_TIM1_ETR 0x4702 +#define STM32F4_PE7_FUNC_UART7_RX 0x4709 +#define STM32F469_PE7_FUNC_QUADSPI_BK2_IO0 0x470b +#define STM32F4_PE7_FUNC_FMC_D4 0x470d +#define STM32F4_PE7_FUNC_EVENTOUT 0x4710 +#define STM32F4_PE7_FUNC_ANALOG 0x4711 + +#define STM32F4_PE8_FUNC_GPIO 0x4800 +#define STM32F4_PE8_FUNC_TIM1_CH1N 0x4802 +#define STM32F4_PE8_FUNC_UART7_TX 0x4809 +#define STM32F469_PE8_FUNC_QUADSPI_BK2_IO1 0x480b +#define STM32F4_PE8_FUNC_FMC_D5 0x480d +#define STM32F4_PE8_FUNC_EVENTOUT 0x4810 +#define STM32F4_PE8_FUNC_ANALOG 0x4811 + +#define STM32F4_PE9_FUNC_GPIO 0x4900 +#define STM32F4_PE9_FUNC_TIM1_CH1 0x4902 +#define STM32F469_PE9_FUNC_QUADSPI_BK2_IO2 0x490b +#define STM32F4_PE9_FUNC_FMC_D6 0x490d +#define STM32F4_PE9_FUNC_EVENTOUT 0x4910 +#define STM32F4_PE9_FUNC_ANALOG 0x4911 + +#define STM32F4_PE10_FUNC_GPIO 0x4a00 +#define STM32F4_PE10_FUNC_TIM1_CH2N 0x4a02 +#define STM32F469_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b +#define STM32F4_PE10_FUNC_FMC_D7 0x4a0d +#define STM32F4_PE10_FUNC_EVENTOUT 0x4a10 +#define STM32F4_PE10_FUNC_ANALOG 0x4a11 + +#define STM32F4_PE11_FUNC_GPIO 0x4b00 +#define STM32F4_PE11_FUNC_TIM1_CH2 0x4b02 +#define STM32F4_PE11_FUNC_SPI4_NSS 0x4b06 +#define STM32F4_PE11_FUNC_FMC_D8 0x4b0d +#define STM32F4_PE11_FUNC_LCD_G3 0x4b0f +#define STM32F4_PE11_FUNC_EVENTOUT 0x4b10 +#define STM32F4_PE11_FUNC_ANALOG 0x4b11 + +#define STM32F4_PE12_FUNC_GPIO 0x4c00 +#define STM32F4_PE12_FUNC_TIM1_CH3N 0x4c02 +#define STM32F4_PE12_FUNC_SPI4_SCK 0x4c06 +#define STM32F4_PE12_FUNC_FMC_D9 0x4c0d +#define STM32F4_PE12_FUNC_LCD_B4 0x4c0f +#define STM32F4_PE12_FUNC_EVENTOUT 0x4c10 +#define STM32F4_PE12_FUNC_ANALOG 0x4c11 + +#define STM32F4_PE13_FUNC_GPIO 0x4d00 +#define STM32F4_PE13_FUNC_TIM1_CH3 0x4d02 +#define STM32F4_PE13_FUNC_SPI4_MISO 0x4d06 +#define STM32F4_PE13_FUNC_FMC_D10 0x4d0d +#define STM32F4_PE13_FUNC_LCD_DE 0x4d0f +#define STM32F4_PE13_FUNC_EVENTOUT 0x4d10 +#define STM32F4_PE13_FUNC_ANALOG 0x4d11 + +#define STM32F4_PE14_FUNC_GPIO 0x4e00 +#define STM32F4_PE14_FUNC_TIM1_CH4 0x4e02 +#define STM32F4_PE14_FUNC_SPI4_MOSI 0x4e06 +#define STM32F4_PE14_FUNC_FMC_D11 0x4e0d +#define STM32F4_PE14_FUNC_LCD_CLK 0x4e0f +#define STM32F4_PE14_FUNC_EVENTOUT 0x4e10 +#define STM32F4_PE14_FUNC_ANALOG 0x4e11 + +#define STM32F4_PE15_FUNC_GPIO 0x4f00 +#define STM32F4_PE15_FUNC_TIM1_BKIN 0x4f02 +#define STM32F4_PE15_FUNC_FMC_D12 0x4f0d +#define STM32F4_PE15_FUNC_LCD_R7 0x4f0f +#define STM32F4_PE15_FUNC_EVENTOUT 0x4f10 +#define STM32F4_PE15_FUNC_ANALOG 0x4f11 + + + +#define STM32F4_PF0_FUNC_GPIO 0x5000 +#define STM32F4_PF0_FUNC_I2C2_SDA 0x5005 +#define STM32F4_PF0_FUNC_FMC_A0 0x500d +#define STM32F4_PF0_FUNC_EVENTOUT 0x5010 +#define STM32F4_PF0_FUNC_ANALOG 0x5011 + +#define STM32F4_PF1_FUNC_GPIO 0x5100 +#define STM32F4_PF1_FUNC_I2C2_SCL 0x5105 +#define STM32F4_PF1_FUNC_FMC_A1 0x510d +#define STM32F4_PF1_FUNC_EVENTOUT 0x5110 +#define STM32F4_PF1_FUNC_ANALOG 0x5111 + +#define STM32F4_PF2_FUNC_GPIO 0x5200 +#define STM32F4_PF2_FUNC_I2C2_SMBA 0x5205 +#define STM32F4_PF2_FUNC_FMC_A2 0x520d +#define STM32F4_PF2_FUNC_EVENTOUT 0x5210 +#define STM32F4_PF2_FUNC_ANALOG 0x5211 + +#define STM32F4_PF3_FUNC_GPIO 0x5300 +#define STM32F4_PF3_FUNC_FMC_A3 0x530d +#define STM32F4_PF3_FUNC_EVENTOUT 0x5310 +#define STM32F4_PF3_FUNC_ANALOG 0x5311 + +#define STM32F4_PF4_FUNC_GPIO 0x5400 +#define STM32F4_PF4_FUNC_FMC_A4 0x540d +#define STM32F4_PF4_FUNC_EVENTOUT 0x5410 +#define STM32F4_PF4_FUNC_ANALOG 0x5411 + +#define STM32F4_PF5_FUNC_GPIO 0x5500 +#define STM32F4_PF5_FUNC_FMC_A5 0x550d +#define STM32F4_PF5_FUNC_EVENTOUT 0x5510 +#define STM32F4_PF5_FUNC_ANALOG 0x5511 + +#define STM32F4_PF6_FUNC_GPIO 0x5600 +#define STM32F4_PF6_FUNC_TIM10_CH1 0x5604 +#define STM32F4_PF6_FUNC_SPI5_NSS 0x5606 +#define STM32F4_PF6_FUNC_SAI1_SD_B 0x5607 +#define STM32F4_PF6_FUNC_UART7_RX 0x5609 +#define STM32F469_PF6_FUNC_QUADSPI_BK1_IO3 0x560a +#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d +#define STM32F4_PF6_FUNC_EVENTOUT 0x5610 +#define STM32F4_PF6_FUNC_ANALOG 0x5611 + +#define STM32F4_PF7_FUNC_GPIO 0x5700 +#define STM32F4_PF7_FUNC_TIM11_CH1 0x5704 +#define STM32F4_PF7_FUNC_SPI5_SCK 0x5706 +#define STM32F4_PF7_FUNC_SAI1_MCLK_B 0x5707 +#define STM32F4_PF7_FUNC_UART7_TX 0x5709 +#define STM32F469_PF7_FUNC_QUADSPI_BK1_IO2 0x570a +#define STM32F429_PF7_FUNC_FMC_NREG 0x570d +#define STM32F4_PF7_FUNC_EVENTOUT 0x5710 +#define STM32F4_PF7_FUNC_ANALOG 0x5711 + +#define STM32F4_PF8_FUNC_GPIO 0x5800 +#define STM32F4_PF8_FUNC_SPI5_MISO 0x5806 +#define STM32F4_PF8_FUNC_SAI1_SCK_B 0x5807 +#define STM32F4_PF8_FUNC_TIM13_CH1 0x580a +#define STM32F469_PF8_FUNC_QUADSPI_BK1_IO0 0x580b +#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d +#define STM32F4_PF8_FUNC_EVENTOUT 0x5810 +#define STM32F4_PF8_FUNC_ANALOG 0x5811 + +#define STM32F4_PF9_FUNC_GPIO 0x5900 +#define STM32F4_PF9_FUNC_SPI5_MOSI 0x5906 +#define STM32F4_PF9_FUNC_SAI1_FS_B 0x5907 +#define STM32F4_PF9_FUNC_TIM14_CH1 0x590a +#define STM32F469_PF9_FUNC_QUADSPI_BK1_IO1 0x590b +#define STM32F429_PF9_FUNC_FMC_CD 0x590d +#define STM32F4_PF9_FUNC_EVENTOUT 0x5910 +#define STM32F4_PF9_FUNC_ANALOG 0x5911 + +#define STM32F4_PF10_FUNC_GPIO 0x5a00 +#define STM32F469_PF10_FUNC_QUADSPI_CLK 0x5a0a +#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d +#define STM32F4_PF10_FUNC_DCMI_D11 0x5a0e +#define STM32F4_PF10_FUNC_LCD_DE 0x5a0f +#define STM32F4_PF10_FUNC_EVENTOUT 0x5a10 +#define STM32F4_PF10_FUNC_ANALOG 0x5a11 + +#define STM32F4_PF11_FUNC_GPIO 0x5b00 +#define STM32F4_PF11_FUNC_SPI5_MOSI 0x5b06 +#define STM32F4_PF11_FUNC_FMC_SDNRAS 0x5b0d +#define STM32F4_PF11_FUNC_DCMI_D12 0x5b0e +#define STM32F4_PF11_FUNC_EVENTOUT 0x5b10 +#define STM32F4_PF11_FUNC_ANALOG 0x5b11 + +#define STM32F4_PF12_FUNC_GPIO 0x5c00 +#define STM32F4_PF12_FUNC_FMC_A6 0x5c0d +#define STM32F4_PF12_FUNC_EVENTOUT 0x5c10 +#define STM32F4_PF12_FUNC_ANALOG 0x5c11 + +#define STM32F4_PF13_FUNC_GPIO 0x5d00 +#define STM32F4_PF13_FUNC_FMC_A7 0x5d0d +#define STM32F4_PF13_FUNC_EVENTOUT 0x5d10 +#define STM32F4_PF13_FUNC_ANALOG 0x5d11 + +#define STM32F4_PF14_FUNC_GPIO 0x5e00 +#define STM32F4_PF14_FUNC_FMC_A8 0x5e0d +#define STM32F4_PF14_FUNC_EVENTOUT 0x5e10 +#define STM32F4_PF14_FUNC_ANALOG 0x5e11 + +#define STM32F4_PF15_FUNC_GPIO 0x5f00 +#define STM32F4_PF15_FUNC_FMC_A9 0x5f0d +#define STM32F4_PF15_FUNC_EVENTOUT 0x5f10 +#define STM32F4_PF15_FUNC_ANALOG 0x5f11 + + + +#define STM32F4_PG0_FUNC_GPIO 0x6000 +#define STM32F4_PG0_FUNC_FMC_A10 0x600d +#define STM32F4_PG0_FUNC_EVENTOUT 0x6010 +#define STM32F4_PG0_FUNC_ANALOG 0x6011 + +#define STM32F4_PG1_FUNC_GPIO 0x6100 +#define STM32F4_PG1_FUNC_FMC_A11 0x610d +#define STM32F4_PG1_FUNC_EVENTOUT 0x6110 +#define STM32F4_PG1_FUNC_ANALOG 0x6111 + +#define STM32F4_PG2_FUNC_GPIO 0x6200 +#define STM32F4_PG2_FUNC_FMC_A12 0x620d +#define STM32F4_PG2_FUNC_EVENTOUT 0x6210 +#define STM32F4_PG2_FUNC_ANALOG 0x6211 + +#define STM32F4_PG3_FUNC_GPIO 0x6300 +#define STM32F4_PG3_FUNC_FMC_A13 0x630d +#define STM32F4_PG3_FUNC_EVENTOUT 0x6310 +#define STM32F4_PG3_FUNC_ANALOG 0x6311 + +#define STM32F4_PG4_FUNC_GPIO 0x6400 +#define STM32F4_PG4_FUNC_FMC_A14_FMC_BA0 0x640d +#define STM32F4_PG4_FUNC_EVENTOUT 0x6410 +#define STM32F4_PG4_FUNC_ANALOG 0x6411 + +#define STM32F4_PG5_FUNC_GPIO 0x6500 +#define STM32F4_PG5_FUNC_FMC_A15_FMC_BA1 0x650d +#define STM32F4_PG5_FUNC_EVENTOUT 0x6510 +#define STM32F4_PG5_FUNC_ANALOG 0x6511 + +#define STM32F4_PG6_FUNC_GPIO 0x6600 +#define STM32F429_PG6_FUNC_FMC_INT2 0x660d +#define STM32F4_PG6_FUNC_DCMI_D12 0x660e +#define STM32F4_PG6_FUNC_LCD_R7 0x660f +#define STM32F4_PG6_FUNC_EVENTOUT 0x6610 +#define STM32F4_PG6_FUNC_ANALOG 0x6611 + +#define STM32F4_PG7_FUNC_GPIO 0x6700 +#define STM32F469_PG7_FUNC_SAI1_MCLK_A 0x6707 +#define STM32F4_PG7_FUNC_USART6_CK 0x6709 +#define STM32F429_PG7_FUNC_FMC_INT3 0x670d +#define STM32F469_PG7_FUNC_FMC_INT 0x670d +#define STM32F4_PG7_FUNC_DCMI_D13 0x670e +#define STM32F4_PG7_FUNC_LCD_CLK 0x670f +#define STM32F4_PG7_FUNC_EVENTOUT 0x6710 +#define STM32F4_PG7_FUNC_ANALOG 0x6711 + +#define STM32F4_PG8_FUNC_GPIO 0x6800 +#define STM32F4_PG8_FUNC_SPI6_NSS 0x6806 +#define STM32F4_PG8_FUNC_USART6_RTS 0x6809 +#define STM32F4_PG8_FUNC_ETH_PPS_OUT 0x680c +#define STM32F4_PG8_FUNC_FMC_SDCLK 0x680d +#define STM32F469_PG8_FUNC_LCD_G7 0x680f +#define STM32F4_PG8_FUNC_EVENTOUT 0x6810 +#define STM32F4_PG8_FUNC_ANALOG 0x6811 + +#define STM32F4_PG9_FUNC_GPIO 0x6900 +#define STM32F4_PG9_FUNC_USART6_RX 0x6909 +#define STM32F469_PG9_FUNC_QUADSPI_BK2_IO2 0x690a +#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d +#define STM32F469_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d +#define STM32F4_PG9_FUNC_DCMI_VSYNC 0x690e +#define STM32F4_PG9_FUNC_EVENTOUT 0x6910 +#define STM32F4_PG9_FUNC_ANALOG 0x6911 + +#define STM32F4_PG10_FUNC_GPIO 0x6a00 +#define STM32F4_PG10_FUNC_LCD_G3 0x6a0a +#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d +#define STM32F469_PG10_FUNC_FMC_NE3 0x6a0d +#define STM32F4_PG10_FUNC_DCMI_D2 0x6a0e +#define STM32F4_PG10_FUNC_LCD_B2 0x6a0f +#define STM32F4_PG10_FUNC_EVENTOUT 0x6a10 +#define STM32F4_PG10_FUNC_ANALOG 0x6a11 + +#define STM32F4_PG11_FUNC_GPIO 0x6b00 +#define STM32F4_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c +#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d +#define STM32F4_PG11_FUNC_DCMI_D3 0x6b0e +#define STM32F4_PG11_FUNC_LCD_B3 0x6b0f +#define STM32F4_PG11_FUNC_EVENTOUT 0x6b10 +#define STM32F4_PG11_FUNC_ANALOG 0x6b11 + +#define STM32F4_PG12_FUNC_GPIO 0x6c00 +#define STM32F4_PG12_FUNC_SPI6_MISO 0x6c06 +#define STM32F4_PG12_FUNC_USART6_RTS 0x6c09 +#define STM32F4_PG12_FUNC_LCD_B4 0x6c0a +#define STM32F4_PG12_FUNC_FMC_NE4 0x6c0d +#define STM32F4_PG12_FUNC_LCD_B1 0x6c0f +#define STM32F4_PG12_FUNC_EVENTOUT 0x6c10 +#define STM32F4_PG12_FUNC_ANALOG 0x6c11 + +#define STM32F4_PG13_FUNC_GPIO 0x6d00 +#define STM32F469_PG13_FUNC_TRACED0 0x6d01 +#define STM32F4_PG13_FUNC_SPI6_SCK 0x6d06 +#define STM32F4_PG13_FUNC_USART6_CTS 0x6d09 +#define STM32F4_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c +#define STM32F4_PG13_FUNC_FMC_A24 0x6d0d +#define STM32F469_PG13_FUNC_LCD_R0 0x6d0f +#define STM32F4_PG13_FUNC_EVENTOUT 0x6d10 +#define STM32F4_PG13_FUNC_ANALOG 0x6d11 + +#define STM32F4_PG14_FUNC_GPIO 0x6e00 +#define STM32F469_PG14_FUNC_TRACED1 0x6e01 +#define STM32F4_PG14_FUNC_SPI6_MOSI 0x6e06 +#define STM32F4_PG14_FUNC_USART6_TX 0x6e09 +#define STM32F469_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a +#define STM32F4_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c +#define STM32F4_PG14_FUNC_FMC_A25 0x6e0d +#define STM32F469_PG14_FUNC_LCD_B0 0x6e0f +#define STM32F4_PG14_FUNC_EVENTOUT 0x6e10 +#define STM32F4_PG14_FUNC_ANALOG 0x6e11 + +#define STM32F4_PG15_FUNC_GPIO 0x6f00 +#define STM32F4_PG15_FUNC_USART6_CTS 0x6f09 +#define STM32F4_PG15_FUNC_FMC_SDNCAS 0x6f0d +#define STM32F4_PG15_FUNC_DCMI_D13 0x6f0e +#define STM32F4_PG15_FUNC_EVENTOUT 0x6f10 +#define STM32F4_PG15_FUNC_ANALOG 0x6f11 + + + +#define STM32F4_PH0_FUNC_GPIO 0x7000 +#define STM32F4_PH0_FUNC_EVENTOUT 0x7010 +#define STM32F4_PH0_FUNC_ANALOG 0x7011 + +#define STM32F4_PH1_FUNC_GPIO 0x7100 +#define STM32F4_PH1_FUNC_EVENTOUT 0x7110 +#define STM32F4_PH1_FUNC_ANALOG 0x7111 + +#define STM32F4_PH2_FUNC_GPIO 0x7200 +#define STM32F469_PH2_FUNC_QUADSPI_BK2_IO0 0x720a +#define STM32F4_PH2_FUNC_ETH_MII_CRS 0x720c +#define STM32F4_PH2_FUNC_FMC_SDCKE0 0x720d +#define STM32F4_PH2_FUNC_LCD_R0 0x720f +#define STM32F4_PH2_FUNC_EVENTOUT 0x7210 +#define STM32F4_PH2_FUNC_ANALOG 0x7211 + +#define STM32F4_PH3_FUNC_GPIO 0x7300 +#define STM32F469_PH3_FUNC_QUADSPI_BK2_IO1 0x730a +#define STM32F4_PH3_FUNC_ETH_MII_COL 0x730c +#define STM32F4_PH3_FUNC_FMC_SDNE0 0x730d +#define STM32F4_PH3_FUNC_LCD_R1 0x730f +#define STM32F4_PH3_FUNC_EVENTOUT 0x7310 +#define STM32F4_PH3_FUNC_ANALOG 0x7311 + +#define STM32F4_PH4_FUNC_GPIO 0x7400 +#define STM32F4_PH4_FUNC_I2C2_SCL 0x7405 +#define STM32F469_PH4_FUNC_LCD_G5 0x740a +#define STM32F4_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b +#define STM32F469_PH4_FUNC_LCD_G4 0x740f +#define STM32F4_PH4_FUNC_EVENTOUT 0x7410 +#define STM32F4_PH4_FUNC_ANALOG 0x7411 + +#define STM32F4_PH5_FUNC_GPIO 0x7500 +#define STM32F4_PH5_FUNC_I2C2_SDA 0x7505 +#define STM32F4_PH5_FUNC_SPI5_NSS 0x7506 +#define STM32F4_PH5_FUNC_FMC_SDNWE 0x750d +#define STM32F4_PH5_FUNC_EVENTOUT 0x7510 +#define STM32F4_PH5_FUNC_ANALOG 0x7511 + +#define STM32F4_PH6_FUNC_GPIO 0x7600 +#define STM32F4_PH6_FUNC_I2C2_SMBA 0x7605 +#define STM32F4_PH6_FUNC_SPI5_SCK 0x7606 +#define STM32F4_PH6_FUNC_TIM12_CH1 0x760a +#define STM32F4_PH6_FUNC_ETH_MII_RXD2 0x760c +#define STM32F4_PH6_FUNC_FMC_SDNE1 0x760d +#define STM32F4_PH6_FUNC_DCMI_D8 0x760e +#define STM32F4_PH6_FUNC_EVENTOUT 0x7610 +#define STM32F4_PH6_FUNC_ANALOG 0x7611 + +#define STM32F4_PH7_FUNC_GPIO 0x7700 +#define STM32F4_PH7_FUNC_I2C3_SCL 0x7705 +#define STM32F4_PH7_FUNC_SPI5_MISO 0x7706 +#define STM32F4_PH7_FUNC_ETH_MII_RXD3 0x770c +#define STM32F4_PH7_FUNC_FMC_SDCKE1 0x770d +#define STM32F4_PH7_FUNC_DCMI_D9 0x770e +#define STM32F4_PH7_FUNC_EVENTOUT 0x7710 +#define STM32F4_PH7_FUNC_ANALOG 0x7711 + +#define STM32F4_PH8_FUNC_GPIO 0x7800 +#define STM32F4_PH8_FUNC_I2C3_SDA 0x7805 +#define STM32F4_PH8_FUNC_FMC_D16 0x780d +#define STM32F4_PH8_FUNC_DCMI_HSYNC 0x780e +#define STM32F4_PH8_FUNC_LCD_R2 0x780f +#define STM32F4_PH8_FUNC_EVENTOUT 0x7810 +#define STM32F4_PH8_FUNC_ANALOG 0x7811 + +#define STM32F4_PH9_FUNC_GPIO 0x7900 +#define STM32F4_PH9_FUNC_I2C3_SMBA 0x7905 +#define STM32F4_PH9_FUNC_TIM12_CH2 0x790a +#define STM32F4_PH9_FUNC_FMC_D17 0x790d +#define STM32F4_PH9_FUNC_DCMI_D0 0x790e +#define STM32F4_PH9_FUNC_LCD_R3 0x790f +#define STM32F4_PH9_FUNC_EVENTOUT 0x7910 +#define STM32F4_PH9_FUNC_ANALOG 0x7911 + +#define STM32F4_PH10_FUNC_GPIO 0x7a00 +#define STM32F4_PH10_FUNC_TIM5_CH1 0x7a03 +#define STM32F4_PH10_FUNC_FMC_D18 0x7a0d +#define STM32F4_PH10_FUNC_DCMI_D1 0x7a0e +#define STM32F4_PH10_FUNC_LCD_R4 0x7a0f +#define STM32F4_PH10_FUNC_EVENTOUT 0x7a10 +#define STM32F4_PH10_FUNC_ANALOG 0x7a11 + +#define STM32F4_PH11_FUNC_GPIO 0x7b00 +#define STM32F4_PH11_FUNC_TIM5_CH2 0x7b03 +#define STM32F4_PH11_FUNC_FMC_D19 0x7b0d +#define STM32F4_PH11_FUNC_DCMI_D2 0x7b0e +#define STM32F4_PH11_FUNC_LCD_R5 0x7b0f +#define STM32F4_PH11_FUNC_EVENTOUT 0x7b10 +#define STM32F4_PH11_FUNC_ANALOG 0x7b11 + +#define STM32F4_PH12_FUNC_GPIO 0x7c00 +#define STM32F4_PH12_FUNC_TIM5_CH3 0x7c03 +#define STM32F4_PH12_FUNC_FMC_D20 0x7c0d +#define STM32F4_PH12_FUNC_DCMI_D3 0x7c0e +#define STM32F4_PH12_FUNC_LCD_R6 0x7c0f +#define STM32F4_PH12_FUNC_EVENTOUT 0x7c10 +#define STM32F4_PH12_FUNC_ANALOG 0x7c11 + +#define STM32F4_PH13_FUNC_GPIO 0x7d00 +#define STM32F4_PH13_FUNC_TIM8_CH1N 0x7d04 +#define STM32F4_PH13_FUNC_CAN1_TX 0x7d0a +#define STM32F4_PH13_FUNC_FMC_D21 0x7d0d +#define STM32F4_PH13_FUNC_LCD_G2 0x7d0f +#define STM32F4_PH13_FUNC_EVENTOUT 0x7d10 +#define STM32F4_PH13_FUNC_ANALOG 0x7d11 + +#define STM32F4_PH14_FUNC_GPIO 0x7e00 +#define STM32F4_PH14_FUNC_TIM8_CH2N 0x7e04 +#define STM32F4_PH14_FUNC_FMC_D22 0x7e0d +#define STM32F4_PH14_FUNC_DCMI_D4 0x7e0e +#define STM32F4_PH14_FUNC_LCD_G3 0x7e0f +#define STM32F4_PH14_FUNC_EVENTOUT 0x7e10 +#define STM32F4_PH14_FUNC_ANALOG 0x7e11 + +#define STM32F4_PH15_FUNC_GPIO 0x7f00 +#define STM32F4_PH15_FUNC_TIM8_CH3N 0x7f04 +#define STM32F4_PH15_FUNC_FMC_D23 0x7f0d +#define STM32F4_PH15_FUNC_DCMI_D11 0x7f0e +#define STM32F4_PH15_FUNC_LCD_G4 0x7f0f +#define STM32F4_PH15_FUNC_EVENTOUT 0x7f10 +#define STM32F4_PH15_FUNC_ANALOG 0x7f11 + + + +#define STM32F4_PI0_FUNC_GPIO 0x8000 +#define STM32F4_PI0_FUNC_TIM5_CH4 0x8003 +#define STM32F4_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 +#define STM32F4_PI0_FUNC_FMC_D24 0x800d +#define STM32F4_PI0_FUNC_DCMI_D13 0x800e +#define STM32F4_PI0_FUNC_LCD_G5 0x800f +#define STM32F4_PI0_FUNC_EVENTOUT 0x8010 +#define STM32F4_PI0_FUNC_ANALOG 0x8011 + +#define STM32F4_PI1_FUNC_GPIO 0x8100 +#define STM32F4_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 +#define STM32F4_PI1_FUNC_FMC_D25 0x810d +#define STM32F4_PI1_FUNC_DCMI_D8 0x810e +#define STM32F4_PI1_FUNC_LCD_G6 0x810f +#define STM32F4_PI1_FUNC_EVENTOUT 0x8110 +#define STM32F4_PI1_FUNC_ANALOG 0x8111 + +#define STM32F4_PI2_FUNC_GPIO 0x8200 +#define STM32F4_PI2_FUNC_TIM8_CH4 0x8204 +#define STM32F4_PI2_FUNC_SPI2_MISO 0x8206 +#define STM32F4_PI2_FUNC_I2S2EXT_SD 0x8207 +#define STM32F4_PI2_FUNC_FMC_D26 0x820d +#define STM32F4_PI2_FUNC_DCMI_D9 0x820e +#define STM32F4_PI2_FUNC_LCD_G7 0x820f +#define STM32F4_PI2_FUNC_EVENTOUT 0x8210 +#define STM32F4_PI2_FUNC_ANALOG 0x8211 + +#define STM32F4_PI3_FUNC_GPIO 0x8300 +#define STM32F4_PI3_FUNC_TIM8_ETR 0x8304 +#define STM32F4_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 +#define STM32F4_PI3_FUNC_FMC_D27 0x830d +#define STM32F4_PI3_FUNC_DCMI_D10 0x830e +#define STM32F4_PI3_FUNC_EVENTOUT 0x8310 +#define STM32F4_PI3_FUNC_ANALOG 0x8311 + +#define STM32F4_PI4_FUNC_GPIO 0x8400 +#define STM32F4_PI4_FUNC_TIM8_BKIN 0x8404 +#define STM32F4_PI4_FUNC_FMC_NBL2 0x840d +#define STM32F4_PI4_FUNC_DCMI_D5 0x840e +#define STM32F4_PI4_FUNC_LCD_B4 0x840f +#define STM32F4_PI4_FUNC_EVENTOUT 0x8410 +#define STM32F4_PI4_FUNC_ANALOG 0x8411 + +#define STM32F4_PI5_FUNC_GPIO 0x8500 +#define STM32F4_PI5_FUNC_TIM8_CH1 0x8504 +#define STM32F4_PI5_FUNC_FMC_NBL3 0x850d +#define STM32F4_PI5_FUNC_DCMI_VSYNC 0x850e +#define STM32F4_PI5_FUNC_LCD_B5 0x850f +#define STM32F4_PI5_FUNC_EVENTOUT 0x8510 +#define STM32F4_PI5_FUNC_ANALOG 0x8511 + +#define STM32F4_PI6_FUNC_GPIO 0x8600 +#define STM32F4_PI6_FUNC_TIM8_CH2 0x8604 +#define STM32F4_PI6_FUNC_FMC_D28 0x860d +#define STM32F4_PI6_FUNC_DCMI_D6 0x860e +#define STM32F4_PI6_FUNC_LCD_B6 0x860f +#define STM32F4_PI6_FUNC_EVENTOUT 0x8610 +#define STM32F4_PI6_FUNC_ANALOG 0x8611 + +#define STM32F4_PI7_FUNC_GPIO 0x8700 +#define STM32F4_PI7_FUNC_TIM8_CH3 0x8704 +#define STM32F4_PI7_FUNC_FMC_D29 0x870d +#define STM32F4_PI7_FUNC_DCMI_D7 0x870e +#define STM32F4_PI7_FUNC_LCD_B7 0x870f +#define STM32F4_PI7_FUNC_EVENTOUT 0x8710 +#define STM32F4_PI7_FUNC_ANALOG 0x8711 + +#define STM32F4_PI8_FUNC_GPIO 0x8800 +#define STM32F4_PI8_FUNC_EVENTOUT 0x8810 +#define STM32F4_PI8_FUNC_ANALOG 0x8811 + +#define STM32F4_PI9_FUNC_GPIO 0x8900 +#define STM32F4_PI9_FUNC_CAN1_RX 0x890a +#define STM32F4_PI9_FUNC_FMC_D30 0x890d +#define STM32F4_PI9_FUNC_LCD_VSYNC 0x890f +#define STM32F4_PI9_FUNC_EVENTOUT 0x8910 +#define STM32F4_PI9_FUNC_ANALOG 0x8911 + +#define STM32F4_PI10_FUNC_GPIO 0x8a00 +#define STM32F4_PI10_FUNC_ETH_MII_RX_ER 0x8a0c +#define STM32F4_PI10_FUNC_FMC_D31 0x8a0d +#define STM32F4_PI10_FUNC_LCD_HSYNC 0x8a0f +#define STM32F4_PI10_FUNC_EVENTOUT 0x8a10 +#define STM32F4_PI10_FUNC_ANALOG 0x8a11 + +#define STM32F4_PI11_FUNC_GPIO 0x8b00 +#define STM32F469_PI11_FUNC_LCD_G6 0x8b0a +#define STM32F4_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b +#define STM32F4_PI11_FUNC_EVENTOUT 0x8b10 +#define STM32F4_PI11_FUNC_ANALOG 0x8b11 + +#define STM32F4_PI12_FUNC_GPIO 0x8c00 +#define STM32F4_PI12_FUNC_LCD_HSYNC 0x8c0f +#define STM32F4_PI12_FUNC_EVENTOUT 0x8c10 +#define STM32F4_PI12_FUNC_ANALOG 0x8c11 + +#define STM32F4_PI13_FUNC_GPIO 0x8d00 +#define STM32F4_PI13_FUNC_LCD_VSYNC 0x8d0f +#define STM32F4_PI13_FUNC_EVENTOUT 0x8d10 +#define STM32F4_PI13_FUNC_ANALOG 0x8d11 + +#define STM32F4_PI14_FUNC_GPIO 0x8e00 +#define STM32F4_PI14_FUNC_LCD_CLK 0x8e0f +#define STM32F4_PI14_FUNC_EVENTOUT 0x8e10 +#define STM32F4_PI14_FUNC_ANALOG 0x8e11 + +#define STM32F4_PI15_FUNC_GPIO 0x8f00 +#define STM32F469_PI15_FUNC_LCD_G2 0x8f0a +#define STM32F4_PI15_FUNC_LCD_R0 0x8f0f +#define STM32F4_PI15_FUNC_EVENTOUT 0x8f10 +#define STM32F4_PI15_FUNC_ANALOG 0x8f11 + + + +#define STM32F4_PJ0_FUNC_GPIO 0x9000 +#define STM32F469_PJ0_FUNC_LCD_R7 0x900a +#define STM32F4_PJ0_FUNC_LCD_R1 0x900f +#define STM32F4_PJ0_FUNC_EVENTOUT 0x9010 +#define STM32F4_PJ0_FUNC_ANALOG 0x9011 + +#define STM32F4_PJ1_FUNC_GPIO 0x9100 +#define STM32F4_PJ1_FUNC_LCD_R2 0x910f +#define STM32F4_PJ1_FUNC_EVENTOUT 0x9110 +#define STM32F4_PJ1_FUNC_ANALOG 0x9111 + +#define STM32F4_PJ2_FUNC_GPIO 0x9200 +#define STM32F469_PJ2_FUNC_DSIHOST_TE 0x920e +#define STM32F4_PJ2_FUNC_LCD_R3 0x920f +#define STM32F4_PJ2_FUNC_EVENTOUT 0x9210 +#define STM32F4_PJ2_FUNC_ANALOG 0x9211 + +#define STM32F4_PJ3_FUNC_GPIO 0x9300 +#define STM32F4_PJ3_FUNC_LCD_R4 0x930f +#define STM32F4_PJ3_FUNC_EVENTOUT 0x9310 +#define STM32F4_PJ3_FUNC_ANALOG 0x9311 + +#define STM32F4_PJ4_FUNC_GPIO 0x9400 +#define STM32F4_PJ4_FUNC_LCD_R5 0x940f +#define STM32F4_PJ4_FUNC_EVENTOUT 0x9410 +#define STM32F4_PJ4_FUNC_ANALOG 0x9411 + +#define STM32F4_PJ5_FUNC_GPIO 0x9500 +#define STM32F4_PJ5_FUNC_LCD_R6 0x950f +#define STM32F4_PJ5_FUNC_EVENTOUT 0x9510 +#define STM32F4_PJ5_FUNC_ANALOG 0x9511 + +#define STM32F429_PJ6_FUNC_GPIO 0x9600 +#define STM32F429_PJ6_FUNC_LCD_R7 0x960f +#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 +#define STM32F429_PJ6_FUNC_ANALOG 0x9611 + +#define STM32F429_PJ7_FUNC_GPIO 0x9700 +#define STM32F429_PJ7_FUNC_LCD_G0 0x970f +#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 +#define STM32F429_PJ7_FUNC_ANALOG 0x9711 + +#define STM32F429_PJ8_FUNC_GPIO 0x9800 +#define STM32F429_PJ8_FUNC_LCD_G1 0x980f +#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 +#define STM32F429_PJ8_FUNC_ANALOG 0x9811 + +#define STM32F429_PJ9_FUNC_GPIO 0x9900 +#define STM32F429_PJ9_FUNC_LCD_G2 0x990f +#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 +#define STM32F429_PJ9_FUNC_ANALOG 0x9911 + +#define STM32F429_PJ10_FUNC_GPIO 0x9a00 +#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f +#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 +#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 + +#define STM32F429_PJ11_FUNC_GPIO 0x9b00 +#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f +#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 +#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 + +#define STM32F4_PJ12_FUNC_GPIO 0x9c00 +#define STM32F469_PJ12_FUNC_LCD_G3 0x9c0a +#define STM32F4_PJ12_FUNC_LCD_B0 0x9c0f +#define STM32F4_PJ12_FUNC_EVENTOUT 0x9c10 +#define STM32F4_PJ12_FUNC_ANALOG 0x9c11 + +#define STM32F4_PJ13_FUNC_GPIO 0x9d00 +#define STM32F469_PJ13_FUNC_LCD_G4 0x9d0a +#define STM32F4_PJ13_FUNC_LCD_B1 0x9d0f +#define STM32F4_PJ13_FUNC_EVENTOUT 0x9d10 +#define STM32F4_PJ13_FUNC_ANALOG 0x9d11 + +#define STM32F4_PJ14_FUNC_GPIO 0x9e00 +#define STM32F4_PJ14_FUNC_LCD_B2 0x9e0f +#define STM32F4_PJ14_FUNC_EVENTOUT 0x9e10 +#define STM32F4_PJ14_FUNC_ANALOG 0x9e11 + +#define STM32F4_PJ15_FUNC_GPIO 0x9f00 +#define STM32F4_PJ15_FUNC_LCD_B3 0x9f0f +#define STM32F4_PJ15_FUNC_EVENTOUT 0x9f10 +#define STM32F4_PJ15_FUNC_ANALOG 0x9f11 + + + +#define STM32F429_PK0_FUNC_GPIO 0xa000 +#define STM32F429_PK0_FUNC_LCD_G5 0xa00f +#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 +#define STM32F429_PK0_FUNC_ANALOG 0xa011 + +#define STM32F429_PK1_FUNC_GPIO 0xa100 +#define STM32F429_PK1_FUNC_LCD_G6 0xa10f +#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 +#define STM32F429_PK1_FUNC_ANALOG 0xa111 + +#define STM32F429_PK2_FUNC_GPIO 0xa200 +#define STM32F429_PK2_FUNC_LCD_G7 0xa20f +#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 +#define STM32F429_PK2_FUNC_ANALOG 0xa211 + +#define STM32F4_PK3_FUNC_GPIO 0xa300 +#define STM32F4_PK3_FUNC_LCD_B4 0xa30f +#define STM32F4_PK3_FUNC_EVENTOUT 0xa310 +#define STM32F4_PK3_FUNC_ANALOG 0xa311 + +#define STM32F4_PK4_FUNC_GPIO 0xa400 +#define STM32F4_PK4_FUNC_LCD_B5 0xa40f +#define STM32F4_PK4_FUNC_EVENTOUT 0xa410 +#define STM32F4_PK4_FUNC_ANALOG 0xa411 + +#define STM32F4_PK5_FUNC_GPIO 0xa500 +#define STM32F4_PK5_FUNC_LCD_B6 0xa50f +#define STM32F4_PK5_FUNC_EVENTOUT 0xa510 +#define STM32F4_PK5_FUNC_ANALOG 0xa511 + +#define STM32F4_PK6_FUNC_GPIO 0xa600 +#define STM32F4_PK6_FUNC_LCD_B7 0xa60f +#define STM32F4_PK6_FUNC_EVENTOUT 0xa610 +#define STM32F4_PK6_FUNC_ANALOG 0xa611 + +#define STM32F4_PK7_FUNC_GPIO 0xa700 +#define STM32F4_PK7_FUNC_LCD_DE 0xa70f +#define STM32F4_PK7_FUNC_EVENTOUT 0xa710 +#define STM32F4_PK7_FUNC_ANALOG 0xa711 + +#endif /* _DT_BINDINGS_STM32F4_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h deleted file mode 100644 index 26f1879..0000000 --- a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h +++ /dev/null @@ -1,1239 +0,0 @@ -#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H -#define _DT_BINDINGS_STM32F429_PINFUNC_H - -#define STM32F429_PA0_FUNC_GPIO 0x0 -#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F429_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F429_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F429_PA0_FUNC_USART2_CTS 0x8 -#define STM32F429_PA0_FUNC_UART4_TX 0x9 -#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F429_PA0_FUNC_EVENTOUT 0x10 -#define STM32F429_PA0_FUNC_ANALOG 0x11 - -#define STM32F429_PA1_FUNC_GPIO 0x100 -#define STM32F429_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F429_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F429_PA1_FUNC_USART2_RTS 0x108 -#define STM32F429_PA1_FUNC_UART4_RX 0x109 -#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F429_PA1_FUNC_EVENTOUT 0x110 -#define STM32F429_PA1_FUNC_ANALOG 0x111 - -#define STM32F429_PA2_FUNC_GPIO 0x200 -#define STM32F429_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F429_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F429_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F429_PA2_FUNC_USART2_TX 0x208 -#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F429_PA2_FUNC_EVENTOUT 0x210 -#define STM32F429_PA2_FUNC_ANALOG 0x211 - -#define STM32F429_PA3_FUNC_GPIO 0x300 -#define STM32F429_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F429_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F429_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F429_PA3_FUNC_USART2_RX 0x308 -#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F429_PA3_FUNC_LCD_B5 0x30f -#define STM32F429_PA3_FUNC_EVENTOUT 0x310 -#define STM32F429_PA3_FUNC_ANALOG 0x311 - -#define STM32F429_PA4_FUNC_GPIO 0x400 -#define STM32F429_PA4_FUNC_SPI1_NSS 0x406 -#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F429_PA4_FUNC_USART2_CK 0x408 -#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F429_PA4_FUNC_EVENTOUT 0x410 -#define STM32F429_PA4_FUNC_ANALOG 0x411 - -#define STM32F429_PA5_FUNC_GPIO 0x500 -#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F429_PA5_FUNC_SPI1_SCK 0x506 -#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F429_PA5_FUNC_EVENTOUT 0x510 -#define STM32F429_PA5_FUNC_ANALOG 0x511 - -#define STM32F429_PA6_FUNC_GPIO 0x600 -#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F429_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F429_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F429_PA6_FUNC_LCD_G2 0x60f -#define STM32F429_PA6_FUNC_EVENTOUT 0x610 -#define STM32F429_PA6_FUNC_ANALOG 0x611 - -#define STM32F429_PA7_FUNC_GPIO 0x700 -#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F429_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706 -#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F429_PA7_FUNC_EVENTOUT 0x710 -#define STM32F429_PA7_FUNC_ANALOG 0x711 - -#define STM32F429_PA8_FUNC_GPIO 0x800 -#define STM32F429_PA8_FUNC_MCO1 0x801 -#define STM32F429_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F429_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F429_PA8_FUNC_USART1_CK 0x808 -#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F429_PA8_FUNC_LCD_R6 0x80f -#define STM32F429_PA8_FUNC_EVENTOUT 0x810 -#define STM32F429_PA8_FUNC_ANALOG 0x811 - -#define STM32F429_PA9_FUNC_GPIO 0x900 -#define STM32F429_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F429_PA9_FUNC_USART1_TX 0x908 -#define STM32F429_PA9_FUNC_DCMI_D0 0x90e -#define STM32F429_PA9_FUNC_EVENTOUT 0x910 -#define STM32F429_PA9_FUNC_ANALOG 0x911 - -#define STM32F429_PA10_FUNC_GPIO 0xa00 -#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F429_PA10_FUNC_USART1_RX 0xa08 -#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F429_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F429_PA10_FUNC_ANALOG 0xa11 - -#define STM32F429_PA11_FUNC_GPIO 0xb00 -#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F429_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F429_PA11_FUNC_LCD_R4 0xb0f -#define STM32F429_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F429_PA11_FUNC_ANALOG 0xb11 - -#define STM32F429_PA12_FUNC_GPIO 0xc00 -#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F429_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F429_PA12_FUNC_LCD_R5 0xc0f -#define STM32F429_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F429_PA12_FUNC_ANALOG 0xc11 - -#define STM32F429_PA13_FUNC_GPIO 0xd00 -#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F429_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F429_PA13_FUNC_ANALOG 0xd11 - -#define STM32F429_PA14_FUNC_GPIO 0xe00 -#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F429_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F429_PA14_FUNC_ANALOG 0xe11 - -#define STM32F429_PA15_FUNC_GPIO 0xf00 -#define STM32F429_PA15_FUNC_JTDI 0xf01 -#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06 -#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F429_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F429_PA15_FUNC_ANALOG 0xf11 - - - -#define STM32F429_PB0_FUNC_GPIO 0x1000 -#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F429_PB0_FUNC_LCD_R3 0x100a -#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F429_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F429_PB0_FUNC_ANALOG 0x1011 - -#define STM32F429_PB1_FUNC_GPIO 0x1100 -#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F429_PB1_FUNC_LCD_R6 0x110a -#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F429_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F429_PB1_FUNC_ANALOG 0x1111 - -#define STM32F429_PB2_FUNC_GPIO 0x1200 -#define STM32F429_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F429_PB2_FUNC_ANALOG 0x1211 - -#define STM32F429_PB3_FUNC_GPIO 0x1300 -#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306 -#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F429_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F429_PB3_FUNC_ANALOG 0x1311 - -#define STM32F429_PB4_FUNC_GPIO 0x1400 -#define STM32F429_PB4_FUNC_NJTRST 0x1401 -#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408 -#define STM32F429_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F429_PB4_FUNC_ANALOG 0x1411 - -#define STM32F429_PB5_FUNC_GPIO 0x1500 -#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506 -#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F429_PB5_FUNC_CAN2_RX 0x150a -#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F429_PB5_FUNC_DCMI_D10 0x150e -#define STM32F429_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F429_PB5_FUNC_ANALOG 0x1511 - -#define STM32F429_PB6_FUNC_GPIO 0x1600 -#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F429_PB6_FUNC_USART1_TX 0x1608 -#define STM32F429_PB6_FUNC_CAN2_TX 0x160a -#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F429_PB6_FUNC_DCMI_D5 0x160e -#define STM32F429_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F429_PB6_FUNC_ANALOG 0x1611 - -#define STM32F429_PB7_FUNC_GPIO 0x1700 -#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F429_PB7_FUNC_USART1_RX 0x1708 -#define STM32F429_PB7_FUNC_FMC_NL 0x170d -#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F429_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F429_PB7_FUNC_ANALOG 0x1711 - -#define STM32F429_PB8_FUNC_GPIO 0x1800 -#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F429_PB8_FUNC_CAN1_RX 0x180a -#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F429_PB8_FUNC_SDIO_D4 0x180d -#define STM32F429_PB8_FUNC_DCMI_D6 0x180e -#define STM32F429_PB8_FUNC_LCD_B6 0x180f -#define STM32F429_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F429_PB8_FUNC_ANALOG 0x1811 - -#define STM32F429_PB9_FUNC_GPIO 0x1900 -#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F429_PB9_FUNC_CAN1_TX 0x190a -#define STM32F429_PB9_FUNC_SDIO_D5 0x190d -#define STM32F429_PB9_FUNC_DCMI_D7 0x190e -#define STM32F429_PB9_FUNC_LCD_B7 0x190f -#define STM32F429_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F429_PB9_FUNC_ANALOG 0x1911 - -#define STM32F429_PB10_FUNC_GPIO 0x1a00 -#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F429_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F429_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F429_PB11_FUNC_GPIO 0x1b00 -#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F429_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F429_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F429_PB12_FUNC_GPIO 0x1c00 -#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F429_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F429_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F429_PB13_FUNC_GPIO 0x1d00 -#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F429_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F429_PB14_FUNC_GPIO 0x1e00 -#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07 -#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F429_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F429_PB15_FUNC_GPIO 0x1f00 -#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F429_PB15_FUNC_ANALOG 0x1f11 - - - -#define STM32F429_PC0_FUNC_GPIO 0x2000 -#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F429_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F429_PC0_FUNC_ANALOG 0x2011 - -#define STM32F429_PC1_FUNC_GPIO 0x2100 -#define STM32F429_PC1_FUNC_ETH_MDC 0x210c -#define STM32F429_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F429_PC1_FUNC_ANALOG 0x2111 - -#define STM32F429_PC2_FUNC_GPIO 0x2200 -#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207 -#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F429_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F429_PC2_FUNC_ANALOG 0x2211 - -#define STM32F429_PC3_FUNC_GPIO 0x2300 -#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F429_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F429_PC3_FUNC_ANALOG 0x2311 - -#define STM32F429_PC4_FUNC_GPIO 0x2400 -#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F429_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F429_PC4_FUNC_ANALOG 0x2411 - -#define STM32F429_PC5_FUNC_GPIO 0x2500 -#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F429_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F429_PC5_FUNC_ANALOG 0x2511 - -#define STM32F429_PC6_FUNC_GPIO 0x2600 -#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F429_PC6_FUNC_USART6_TX 0x2609 -#define STM32F429_PC6_FUNC_SDIO_D6 0x260d -#define STM32F429_PC6_FUNC_DCMI_D0 0x260e -#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F429_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F429_PC6_FUNC_ANALOG 0x2611 - -#define STM32F429_PC7_FUNC_GPIO 0x2700 -#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F429_PC7_FUNC_USART6_RX 0x2709 -#define STM32F429_PC7_FUNC_SDIO_D7 0x270d -#define STM32F429_PC7_FUNC_DCMI_D1 0x270e -#define STM32F429_PC7_FUNC_LCD_G6 0x270f -#define STM32F429_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F429_PC7_FUNC_ANALOG 0x2711 - -#define STM32F429_PC8_FUNC_GPIO 0x2800 -#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F429_PC8_FUNC_USART6_CK 0x2809 -#define STM32F429_PC8_FUNC_SDIO_D0 0x280d -#define STM32F429_PC8_FUNC_DCMI_D2 0x280e -#define STM32F429_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F429_PC8_FUNC_ANALOG 0x2811 - -#define STM32F429_PC9_FUNC_GPIO 0x2900 -#define STM32F429_PC9_FUNC_MCO2 0x2901 -#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F429_PC9_FUNC_SDIO_D1 0x290d -#define STM32F429_PC9_FUNC_DCMI_D3 0x290e -#define STM32F429_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F429_PC9_FUNC_ANALOG 0x2911 - -#define STM32F429_PC10_FUNC_GPIO 0x2a00 -#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F429_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F429_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d -#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F429_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F429_PC11_FUNC_GPIO 0x2b00 -#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06 -#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F429_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F429_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d -#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F429_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F429_PC12_FUNC_GPIO 0x2c00 -#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F429_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F429_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d -#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F429_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F429_PC13_FUNC_GPIO 0x2d00 -#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F429_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F429_PC14_FUNC_GPIO 0x2e00 -#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F429_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F429_PC15_FUNC_GPIO 0x2f00 -#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F429_PC15_FUNC_ANALOG 0x2f11 - - - -#define STM32F429_PD0_FUNC_GPIO 0x3000 -#define STM32F429_PD0_FUNC_CAN1_RX 0x300a -#define STM32F429_PD0_FUNC_FMC_D2 0x300d -#define STM32F429_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F429_PD0_FUNC_ANALOG 0x3011 - -#define STM32F429_PD1_FUNC_GPIO 0x3100 -#define STM32F429_PD1_FUNC_CAN1_TX 0x310a -#define STM32F429_PD1_FUNC_FMC_D3 0x310d -#define STM32F429_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F429_PD1_FUNC_ANALOG 0x3111 - -#define STM32F429_PD2_FUNC_GPIO 0x3200 -#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F429_PD2_FUNC_UART5_RX 0x3209 -#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d -#define STM32F429_PD2_FUNC_DCMI_D11 0x320e -#define STM32F429_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F429_PD2_FUNC_ANALOG 0x3211 - -#define STM32F429_PD3_FUNC_GPIO 0x3300 -#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F429_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F429_PD3_FUNC_FMC_CLK 0x330d -#define STM32F429_PD3_FUNC_DCMI_D5 0x330e -#define STM32F429_PD3_FUNC_LCD_G7 0x330f -#define STM32F429_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F429_PD3_FUNC_ANALOG 0x3311 - -#define STM32F429_PD4_FUNC_GPIO 0x3400 -#define STM32F429_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F429_PD4_FUNC_FMC_NOE 0x340d -#define STM32F429_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F429_PD4_FUNC_ANALOG 0x3411 - -#define STM32F429_PD5_FUNC_GPIO 0x3500 -#define STM32F429_PD5_FUNC_USART2_TX 0x3508 -#define STM32F429_PD5_FUNC_FMC_NWE 0x350d -#define STM32F429_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F429_PD5_FUNC_ANALOG 0x3511 - -#define STM32F429_PD6_FUNC_GPIO 0x3600 -#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F429_PD6_FUNC_USART2_RX 0x3608 -#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F429_PD6_FUNC_DCMI_D10 0x360e -#define STM32F429_PD6_FUNC_LCD_B2 0x360f -#define STM32F429_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F429_PD6_FUNC_ANALOG 0x3611 - -#define STM32F429_PD7_FUNC_GPIO 0x3700 -#define STM32F429_PD7_FUNC_USART2_CK 0x3708 -#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d -#define STM32F429_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F429_PD7_FUNC_ANALOG 0x3711 - -#define STM32F429_PD8_FUNC_GPIO 0x3800 -#define STM32F429_PD8_FUNC_USART3_TX 0x3808 -#define STM32F429_PD8_FUNC_FMC_D13 0x380d -#define STM32F429_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F429_PD8_FUNC_ANALOG 0x3811 - -#define STM32F429_PD9_FUNC_GPIO 0x3900 -#define STM32F429_PD9_FUNC_USART3_RX 0x3908 -#define STM32F429_PD9_FUNC_FMC_D14 0x390d -#define STM32F429_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F429_PD9_FUNC_ANALOG 0x3911 - -#define STM32F429_PD10_FUNC_GPIO 0x3a00 -#define STM32F429_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F429_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F429_PD11_FUNC_GPIO 0x3b00 -#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d -#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F429_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F429_PD12_FUNC_GPIO 0x3c00 -#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d -#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F429_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F429_PD13_FUNC_GPIO 0x3d00 -#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F429_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F429_PD14_FUNC_GPIO 0x3e00 -#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F429_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F429_PD15_FUNC_GPIO 0x3f00 -#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F429_PD15_FUNC_ANALOG 0x3f11 - - - -#define STM32F429_PE0_FUNC_GPIO 0x4000 -#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F429_PE0_FUNC_UART8_RX 0x4009 -#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F429_PE0_FUNC_DCMI_D2 0x400e -#define STM32F429_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F429_PE0_FUNC_ANALOG 0x4011 - -#define STM32F429_PE1_FUNC_GPIO 0x4100 -#define STM32F429_PE1_FUNC_UART8_TX 0x4109 -#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F429_PE1_FUNC_DCMI_D3 0x410e -#define STM32F429_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F429_PE1_FUNC_ANALOG 0x4111 - -#define STM32F429_PE2_FUNC_GPIO 0x4200 -#define STM32F429_PE2_FUNC_TRACECLK 0x4201 -#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F429_PE2_FUNC_FMC_A23 0x420d -#define STM32F429_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F429_PE2_FUNC_ANALOG 0x4211 - -#define STM32F429_PE3_FUNC_GPIO 0x4300 -#define STM32F429_PE3_FUNC_TRACED0 0x4301 -#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F429_PE3_FUNC_FMC_A19 0x430d -#define STM32F429_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F429_PE3_FUNC_ANALOG 0x4311 - -#define STM32F429_PE4_FUNC_GPIO 0x4400 -#define STM32F429_PE4_FUNC_TRACED1 0x4401 -#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F429_PE4_FUNC_FMC_A20 0x440d -#define STM32F429_PE4_FUNC_DCMI_D4 0x440e -#define STM32F429_PE4_FUNC_LCD_B0 0x440f -#define STM32F429_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F429_PE4_FUNC_ANALOG 0x4411 - -#define STM32F429_PE5_FUNC_GPIO 0x4500 -#define STM32F429_PE5_FUNC_TRACED2 0x4501 -#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F429_PE5_FUNC_FMC_A21 0x450d -#define STM32F429_PE5_FUNC_DCMI_D6 0x450e -#define STM32F429_PE5_FUNC_LCD_G0 0x450f -#define STM32F429_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F429_PE5_FUNC_ANALOG 0x4511 - -#define STM32F429_PE6_FUNC_GPIO 0x4600 -#define STM32F429_PE6_FUNC_TRACED3 0x4601 -#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F429_PE6_FUNC_FMC_A22 0x460d -#define STM32F429_PE6_FUNC_DCMI_D7 0x460e -#define STM32F429_PE6_FUNC_LCD_G1 0x460f -#define STM32F429_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F429_PE6_FUNC_ANALOG 0x4611 - -#define STM32F429_PE7_FUNC_GPIO 0x4700 -#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F429_PE7_FUNC_UART7_RX 0x4709 -#define STM32F429_PE7_FUNC_FMC_D4 0x470d -#define STM32F429_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F429_PE7_FUNC_ANALOG 0x4711 - -#define STM32F429_PE8_FUNC_GPIO 0x4800 -#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F429_PE8_FUNC_UART7_TX 0x4809 -#define STM32F429_PE8_FUNC_FMC_D5 0x480d -#define STM32F429_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F429_PE8_FUNC_ANALOG 0x4811 - -#define STM32F429_PE9_FUNC_GPIO 0x4900 -#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F429_PE9_FUNC_FMC_D6 0x490d -#define STM32F429_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F429_PE9_FUNC_ANALOG 0x4911 - -#define STM32F429_PE10_FUNC_GPIO 0x4a00 -#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F429_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F429_PE11_FUNC_GPIO 0x4b00 -#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F429_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F429_PE12_FUNC_GPIO 0x4c00 -#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F429_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F429_PE13_FUNC_GPIO 0x4d00 -#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F429_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F429_PE14_FUNC_GPIO 0x4e00 -#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F429_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F429_PE15_FUNC_GPIO 0x4f00 -#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F429_PE15_FUNC_ANALOG 0x4f11 - - - -#define STM32F429_PF0_FUNC_GPIO 0x5000 -#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F429_PF0_FUNC_FMC_A0 0x500d -#define STM32F429_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F429_PF0_FUNC_ANALOG 0x5011 - -#define STM32F429_PF1_FUNC_GPIO 0x5100 -#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F429_PF1_FUNC_FMC_A1 0x510d -#define STM32F429_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F429_PF1_FUNC_ANALOG 0x5111 - -#define STM32F429_PF2_FUNC_GPIO 0x5200 -#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F429_PF2_FUNC_FMC_A2 0x520d -#define STM32F429_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F429_PF2_FUNC_ANALOG 0x5211 - -#define STM32F429_PF3_FUNC_GPIO 0x5300 -#define STM32F429_PF3_FUNC_FMC_A3 0x530d -#define STM32F429_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F429_PF3_FUNC_ANALOG 0x5311 - -#define STM32F429_PF4_FUNC_GPIO 0x5400 -#define STM32F429_PF4_FUNC_FMC_A4 0x540d -#define STM32F429_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F429_PF4_FUNC_ANALOG 0x5411 - -#define STM32F429_PF5_FUNC_GPIO 0x5500 -#define STM32F429_PF5_FUNC_FMC_A5 0x550d -#define STM32F429_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F429_PF5_FUNC_ANALOG 0x5511 - -#define STM32F429_PF6_FUNC_GPIO 0x5600 -#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F429_PF6_FUNC_UART7_RX 0x5609 -#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d -#define STM32F429_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F429_PF6_FUNC_ANALOG 0x5611 - -#define STM32F429_PF7_FUNC_GPIO 0x5700 -#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F429_PF7_FUNC_UART7_TX 0x5709 -#define STM32F429_PF7_FUNC_FMC_NREG 0x570d -#define STM32F429_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F429_PF7_FUNC_ANALOG 0x5711 - -#define STM32F429_PF8_FUNC_GPIO 0x5800 -#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d -#define STM32F429_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F429_PF8_FUNC_ANALOG 0x5811 - -#define STM32F429_PF9_FUNC_GPIO 0x5900 -#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F429_PF9_FUNC_FMC_CD 0x590d -#define STM32F429_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F429_PF9_FUNC_ANALOG 0x5911 - -#define STM32F429_PF10_FUNC_GPIO 0x5a00 -#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d -#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F429_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F429_PF11_FUNC_GPIO 0x5b00 -#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F429_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F429_PF12_FUNC_GPIO 0x5c00 -#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F429_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F429_PF13_FUNC_GPIO 0x5d00 -#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F429_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F429_PF14_FUNC_GPIO 0x5e00 -#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F429_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F429_PF15_FUNC_GPIO 0x5f00 -#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F429_PF15_FUNC_ANALOG 0x5f11 - - - -#define STM32F429_PG0_FUNC_GPIO 0x6000 -#define STM32F429_PG0_FUNC_FMC_A10 0x600d -#define STM32F429_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F429_PG0_FUNC_ANALOG 0x6011 - -#define STM32F429_PG1_FUNC_GPIO 0x6100 -#define STM32F429_PG1_FUNC_FMC_A11 0x610d -#define STM32F429_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F429_PG1_FUNC_ANALOG 0x6111 - -#define STM32F429_PG2_FUNC_GPIO 0x6200 -#define STM32F429_PG2_FUNC_FMC_A12 0x620d -#define STM32F429_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F429_PG2_FUNC_ANALOG 0x6211 - -#define STM32F429_PG3_FUNC_GPIO 0x6300 -#define STM32F429_PG3_FUNC_FMC_A13 0x630d -#define STM32F429_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F429_PG3_FUNC_ANALOG 0x6311 - -#define STM32F429_PG4_FUNC_GPIO 0x6400 -#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F429_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F429_PG4_FUNC_ANALOG 0x6411 - -#define STM32F429_PG5_FUNC_GPIO 0x6500 -#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F429_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F429_PG5_FUNC_ANALOG 0x6511 - -#define STM32F429_PG6_FUNC_GPIO 0x6600 -#define STM32F429_PG6_FUNC_FMC_INT2 0x660d -#define STM32F429_PG6_FUNC_DCMI_D12 0x660e -#define STM32F429_PG6_FUNC_LCD_R7 0x660f -#define STM32F429_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F429_PG6_FUNC_ANALOG 0x6611 - -#define STM32F429_PG7_FUNC_GPIO 0x6700 -#define STM32F429_PG7_FUNC_USART6_CK 0x6709 -#define STM32F429_PG7_FUNC_FMC_INT3 0x670d -#define STM32F429_PG7_FUNC_DCMI_D13 0x670e -#define STM32F429_PG7_FUNC_LCD_CLK 0x670f -#define STM32F429_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F429_PG7_FUNC_ANALOG 0x6711 - -#define STM32F429_PG8_FUNC_GPIO 0x6800 -#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F429_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F429_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F429_PG8_FUNC_ANALOG 0x6811 - -#define STM32F429_PG9_FUNC_GPIO 0x6900 -#define STM32F429_PG9_FUNC_USART6_RX 0x6909 -#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d -#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F429_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F429_PG9_FUNC_ANALOG 0x6911 - -#define STM32F429_PG10_FUNC_GPIO 0x6a00 -#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d -#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F429_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F429_PG11_FUNC_GPIO 0x6b00 -#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d -#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F429_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F429_PG12_FUNC_GPIO 0x6c00 -#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F429_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F429_PG13_FUNC_GPIO 0x6d00 -#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F429_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F429_PG14_FUNC_GPIO 0x6e00 -#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F429_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F429_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F429_PG15_FUNC_GPIO 0x6f00 -#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F429_PG15_FUNC_ANALOG 0x6f11 - - - -#define STM32F429_PH0_FUNC_GPIO 0x7000 -#define STM32F429_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F429_PH0_FUNC_ANALOG 0x7011 - -#define STM32F429_PH1_FUNC_GPIO 0x7100 -#define STM32F429_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F429_PH1_FUNC_ANALOG 0x7111 - -#define STM32F429_PH2_FUNC_GPIO 0x7200 -#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F429_PH2_FUNC_LCD_R0 0x720f -#define STM32F429_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F429_PH2_FUNC_ANALOG 0x7211 - -#define STM32F429_PH3_FUNC_GPIO 0x7300 -#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F429_PH3_FUNC_LCD_R1 0x730f -#define STM32F429_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F429_PH3_FUNC_ANALOG 0x7311 - -#define STM32F429_PH4_FUNC_GPIO 0x7400 -#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F429_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F429_PH4_FUNC_ANALOG 0x7411 - -#define STM32F429_PH5_FUNC_GPIO 0x7500 -#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F429_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F429_PH5_FUNC_ANALOG 0x7511 - -#define STM32F429_PH6_FUNC_GPIO 0x7600 -#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F429_PH6_FUNC_DCMI_D8 0x760e -#define STM32F429_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F429_PH6_FUNC_ANALOG 0x7611 - -#define STM32F429_PH7_FUNC_GPIO 0x7700 -#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F429_PH7_FUNC_DCMI_D9 0x770e -#define STM32F429_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F429_PH7_FUNC_ANALOG 0x7711 - -#define STM32F429_PH8_FUNC_GPIO 0x7800 -#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F429_PH8_FUNC_FMC_D16 0x780d -#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F429_PH8_FUNC_LCD_R2 0x780f -#define STM32F429_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F429_PH8_FUNC_ANALOG 0x7811 - -#define STM32F429_PH9_FUNC_GPIO 0x7900 -#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F429_PH9_FUNC_FMC_D17 0x790d -#define STM32F429_PH9_FUNC_DCMI_D0 0x790e -#define STM32F429_PH9_FUNC_LCD_R3 0x790f -#define STM32F429_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F429_PH9_FUNC_ANALOG 0x7911 - -#define STM32F429_PH10_FUNC_GPIO 0x7a00 -#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F429_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F429_PH11_FUNC_GPIO 0x7b00 -#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F429_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F429_PH12_FUNC_GPIO 0x7c00 -#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F429_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F429_PH13_FUNC_GPIO 0x7d00 -#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F429_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F429_PH14_FUNC_GPIO 0x7e00 -#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F429_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F429_PH15_FUNC_GPIO 0x7f00 -#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F429_PH15_FUNC_ANALOG 0x7f11 - - - -#define STM32F429_PI0_FUNC_GPIO 0x8000 -#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F429_PI0_FUNC_FMC_D24 0x800d -#define STM32F429_PI0_FUNC_DCMI_D13 0x800e -#define STM32F429_PI0_FUNC_LCD_G5 0x800f -#define STM32F429_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F429_PI0_FUNC_ANALOG 0x8011 - -#define STM32F429_PI1_FUNC_GPIO 0x8100 -#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F429_PI1_FUNC_FMC_D25 0x810d -#define STM32F429_PI1_FUNC_DCMI_D8 0x810e -#define STM32F429_PI1_FUNC_LCD_G6 0x810f -#define STM32F429_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F429_PI1_FUNC_ANALOG 0x8111 - -#define STM32F429_PI2_FUNC_GPIO 0x8200 -#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207 -#define STM32F429_PI2_FUNC_FMC_D26 0x820d -#define STM32F429_PI2_FUNC_DCMI_D9 0x820e -#define STM32F429_PI2_FUNC_LCD_G7 0x820f -#define STM32F429_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F429_PI2_FUNC_ANALOG 0x8211 - -#define STM32F429_PI3_FUNC_GPIO 0x8300 -#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F429_PI3_FUNC_FMC_D27 0x830d -#define STM32F429_PI3_FUNC_DCMI_D10 0x830e -#define STM32F429_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F429_PI3_FUNC_ANALOG 0x8311 - -#define STM32F429_PI4_FUNC_GPIO 0x8400 -#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F429_PI4_FUNC_DCMI_D5 0x840e -#define STM32F429_PI4_FUNC_LCD_B4 0x840f -#define STM32F429_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F429_PI4_FUNC_ANALOG 0x8411 - -#define STM32F429_PI5_FUNC_GPIO 0x8500 -#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F429_PI5_FUNC_LCD_B5 0x850f -#define STM32F429_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F429_PI5_FUNC_ANALOG 0x8511 - -#define STM32F429_PI6_FUNC_GPIO 0x8600 -#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F429_PI6_FUNC_FMC_D28 0x860d -#define STM32F429_PI6_FUNC_DCMI_D6 0x860e -#define STM32F429_PI6_FUNC_LCD_B6 0x860f -#define STM32F429_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F429_PI6_FUNC_ANALOG 0x8611 - -#define STM32F429_PI7_FUNC_GPIO 0x8700 -#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F429_PI7_FUNC_FMC_D29 0x870d -#define STM32F429_PI7_FUNC_DCMI_D7 0x870e -#define STM32F429_PI7_FUNC_LCD_B7 0x870f -#define STM32F429_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F429_PI7_FUNC_ANALOG 0x8711 - -#define STM32F429_PI8_FUNC_GPIO 0x8800 -#define STM32F429_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F429_PI8_FUNC_ANALOG 0x8811 - -#define STM32F429_PI9_FUNC_GPIO 0x8900 -#define STM32F429_PI9_FUNC_CAN1_RX 0x890a -#define STM32F429_PI9_FUNC_FMC_D30 0x890d -#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F429_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F429_PI9_FUNC_ANALOG 0x8911 - -#define STM32F429_PI10_FUNC_GPIO 0x8a00 -#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F429_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F429_PI11_FUNC_GPIO 0x8b00 -#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F429_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F429_PI12_FUNC_GPIO 0x8c00 -#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F429_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F429_PI13_FUNC_GPIO 0x8d00 -#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F429_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F429_PI14_FUNC_GPIO 0x8e00 -#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F429_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F429_PI15_FUNC_GPIO 0x8f00 -#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F429_PI15_FUNC_ANALOG 0x8f11 - - - -#define STM32F429_PJ0_FUNC_GPIO 0x9000 -#define STM32F429_PJ0_FUNC_LCD_R1 0x900f -#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F429_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F429_PJ1_FUNC_GPIO 0x9100 -#define STM32F429_PJ1_FUNC_LCD_R2 0x910f -#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F429_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F429_PJ2_FUNC_GPIO 0x9200 -#define STM32F429_PJ2_FUNC_LCD_R3 0x920f -#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F429_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F429_PJ3_FUNC_GPIO 0x9300 -#define STM32F429_PJ3_FUNC_LCD_R4 0x930f -#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F429_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F429_PJ4_FUNC_GPIO 0x9400 -#define STM32F429_PJ4_FUNC_LCD_R5 0x940f -#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F429_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F429_PJ5_FUNC_GPIO 0x9500 -#define STM32F429_PJ5_FUNC_LCD_R6 0x950f -#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F429_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F429_PJ6_FUNC_GPIO 0x9600 -#define STM32F429_PJ6_FUNC_LCD_R7 0x960f -#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F429_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F429_PJ7_FUNC_GPIO 0x9700 -#define STM32F429_PJ7_FUNC_LCD_G0 0x970f -#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F429_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F429_PJ8_FUNC_GPIO 0x9800 -#define STM32F429_PJ8_FUNC_LCD_G1 0x980f -#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F429_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F429_PJ9_FUNC_GPIO 0x9900 -#define STM32F429_PJ9_FUNC_LCD_G2 0x990f -#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F429_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F429_PJ10_FUNC_GPIO 0x9a00 -#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F429_PJ11_FUNC_GPIO 0x9b00 -#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F429_PJ12_FUNC_GPIO 0x9c00 -#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F429_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F429_PJ13_FUNC_GPIO 0x9d00 -#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F429_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F429_PJ14_FUNC_GPIO 0x9e00 -#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F429_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F429_PJ15_FUNC_GPIO 0x9f00 -#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F429_PJ15_FUNC_ANALOG 0x9f11 - - - -#define STM32F429_PK0_FUNC_GPIO 0xa000 -#define STM32F429_PK0_FUNC_LCD_G5 0xa00f -#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F429_PK0_FUNC_ANALOG 0xa011 - -#define STM32F429_PK1_FUNC_GPIO 0xa100 -#define STM32F429_PK1_FUNC_LCD_G6 0xa10f -#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F429_PK1_FUNC_ANALOG 0xa111 - -#define STM32F429_PK2_FUNC_GPIO 0xa200 -#define STM32F429_PK2_FUNC_LCD_G7 0xa20f -#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F429_PK2_FUNC_ANALOG 0xa211 - -#define STM32F429_PK3_FUNC_GPIO 0xa300 -#define STM32F429_PK3_FUNC_LCD_B4 0xa30f -#define STM32F429_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F429_PK3_FUNC_ANALOG 0xa311 - -#define STM32F429_PK4_FUNC_GPIO 0xa400 -#define STM32F429_PK4_FUNC_LCD_B5 0xa40f -#define STM32F429_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F429_PK4_FUNC_ANALOG 0xa411 - -#define STM32F429_PK5_FUNC_GPIO 0xa500 -#define STM32F429_PK5_FUNC_LCD_B6 0xa50f -#define STM32F429_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F429_PK5_FUNC_ANALOG 0xa511 - -#define STM32F429_PK6_FUNC_GPIO 0xa600 -#define STM32F429_PK6_FUNC_LCD_B7 0xa60f -#define STM32F429_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F429_PK6_FUNC_ANALOG 0xa611 - -#define STM32F429_PK7_FUNC_GPIO 0xa700 -#define STM32F429_PK7_FUNC_LCD_DE 0xa70f -#define STM32F429_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F429_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */ -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 8/8] ARM: dts: stm32: create dedicated files for pinctrl definitions [not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> ` (2 preceding siblings ...) 2017-01-27 16:15 ` [PATCH 4/8] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings Alexandre TORGUE @ 2017-01-27 16:15 ` Alexandre TORGUE 3 siblings, 0 replies; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones-QSEj5FYQhm4dnm+yROfE0A Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Create dedicated file by MCU for pinmuxing and gpio definitions. Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 5436e88..7f22385 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -46,6 +46,7 @@ */ /dts-v1/; +#include "stm32f429-pinctrl.dtsi" #include "stm32f429.dtsi" #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi new file mode 100644 index 0000000..d349c59 --- /dev/null +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -0,0 +1,196 @@ +/* + * Copyright 2016 - Alexandre Torgue <alexandre.torgue-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/pinctrl/stm32f4-pinfunc.h> +/ { + soc { + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 0>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 1>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 2>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 3>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 4>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 5>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 6>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 7>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 8>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 9>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 10>; + st,bank-name = "GPIOK"; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F4_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F4_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg_hs@0 { + pins { + pinmux = <STM32F4_PH4_FUNC_OTG_HS_ULPI_NXT>, + <STM32F4_PI11_FUNC_OTG_HS_ULPI_DIR>, + <STM32F4_PC0_FUNC_OTG_HS_ULPI_STP>, + <STM32F4_PA5_FUNC_OTG_HS_ULPI_CK>, + <STM32F4_PA3_FUNC_OTG_HS_ULPI_D0>, + <STM32F4_PB0_FUNC_OTG_HS_ULPI_D1>, + <STM32F4_PB1_FUNC_OTG_HS_ULPI_D2>, + <STM32F4_PB10_FUNC_OTG_HS_ULPI_D3>, + <STM32F4_PB11_FUNC_OTG_HS_ULPI_D4>, + <STM32F4_PB12_FUNC_OTG_HS_ULPI_D5>, + <STM32F4_PB13_FUNC_OTG_HS_ULPI_D6>, + <STM32F4_PB5_FUNC_OTG_HS_ULPI_D7>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F4_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F4_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F4_PC2_FUNC_ETH_MII_TXD2>, + <STM32F4_PB8_FUNC_ETH_MII_TXD3>, + <STM32F4_PC3_FUNC_ETH_MII_TX_CLK>, + <STM32F4_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F4_PA2_FUNC_ETH_MDIO>, + <STM32F4_PC1_FUNC_ETH_MDC>, + <STM32F4_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F4_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F4_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F4_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, + <STM32F4_PH6_FUNC_ETH_MII_RXD2>, + <STM32F4_PH7_FUNC_ETH_MII_RXD3>; + slew-rate = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 7d0415e..ddff78c 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -46,6 +46,7 @@ */ /dts-v1/; +#include "stm32f429-pinctrl.dtsi" #include "stm32f429.dtsi" #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi new file mode 100644 index 0000000..54aa8e5 --- /dev/null +++ b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi @@ -0,0 +1,106 @@ +/* + * Copyright 2016 - Alexandre Torgue <alexandre.torgue-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "stm32f4-pinctrl.dtsi" + +/ { + soc { + pinctrl: pin-controller { + compatible = "st,stm32f429-pinctrl"; + + gpioa: gpio@40020000 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index d585288..99ce8bb 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -47,8 +47,6 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include <dt-bindings/pinctrl/stm32f4-pinfunc.h> - / { clocks { clk_hse: clk-hse { @@ -206,157 +204,6 @@ reg = <0x40007000 0x400>; }; - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f429-pinctrl"; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 0>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 1>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 2>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 3>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 4>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 5>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 6>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 7>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 8>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 9>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 10>; - st,bank-name = "GPIOK"; - }; - - usart1_pins_a: usart1@0 { - pins1 { - pinmux = <STM32F4_PA9_FUNC_USART1_TX>; - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32F4_PA10_FUNC_USART1_RX>; - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg_hs@0 { - pins { - pinmux = <STM32F4_PH4_FUNC_OTG_HS_ULPI_NXT>, - <STM32F4_PI11_FUNC_OTG_HS_ULPI_DIR>, - <STM32F4_PC0_FUNC_OTG_HS_ULPI_STP>, - <STM32F4_PA5_FUNC_OTG_HS_ULPI_CK>, - <STM32F4_PA3_FUNC_OTG_HS_ULPI_D0>, - <STM32F4_PB0_FUNC_OTG_HS_ULPI_D1>, - <STM32F4_PB1_FUNC_OTG_HS_ULPI_D2>, - <STM32F4_PB10_FUNC_OTG_HS_ULPI_D3>, - <STM32F4_PB11_FUNC_OTG_HS_ULPI_D4>, - <STM32F4_PB12_FUNC_OTG_HS_ULPI_D5>, - <STM32F4_PB13_FUNC_OTG_HS_ULPI_D6>, - <STM32F4_PB5_FUNC_OTG_HS_ULPI_D7>; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ethernet_mii: mii@0 { - pins { - pinmux = <STM32F4_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, - <STM32F4_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, - <STM32F4_PC2_FUNC_ETH_MII_TXD2>, - <STM32F4_PB8_FUNC_ETH_MII_TXD3>, - <STM32F4_PC3_FUNC_ETH_MII_TX_CLK>, - <STM32F4_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, - <STM32F4_PA2_FUNC_ETH_MDIO>, - <STM32F4_PC1_FUNC_ETH_MDC>, - <STM32F4_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, - <STM32F4_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, - <STM32F4_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, - <STM32F4_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, - <STM32F4_PH6_FUNC_ETH_MII_RXD2>, - <STM32F4_PH7_FUNC_ETH_MII_RXD3>; - slew-rate = <2>; - }; - }; - }; - rcc: rcc@40023810 { #reset-cells = <1>; #clock-cells = <2>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 8877c00..8629a78 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -46,6 +46,7 @@ */ /dts-v1/; +#include "stm32f469-pinctrl.dtsi" #include "stm32f429.dtsi" / { diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi new file mode 100644 index 0000000..523459f --- /dev/null +++ b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi @@ -0,0 +1,107 @@ +/* + * Copyright 2016 - Alexandre Torgue <alexandre.torgue-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "stm32f4-pinctrl.dtsi" + +/ { + soc { + pinctrl: pin-controller { + compatible = "st,stm32f469-pinctrl"; + + gpioa: gpio@40020000 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + ngpios = <10>; + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; + + gpiok: gpio@40022800 { + ngpios = <5>; + gpio-ranges = <&pinctrl 3 163 5>; + }; + }; + }; +}; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/8] pinctrl: stm32: Add STM32F469 MCU support 2017-01-27 16:15 [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre TORGUE 2017-01-27 16:15 ` [PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq Alexandre TORGUE [not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> @ 2017-01-27 16:15 ` Alexandre TORGUE 2017-01-27 16:15 ` [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings Alexandre TORGUE ` (2 subsequent siblings) 5 siblings, 0 replies; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones Cc: linux-arm-kernel, devicetree, linux-gpio, linux-kernel This patch which adds STM32F469 pinctrl and GPIO support, relies on the generic STM32 pinctrl driver. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index c03dce7..a065fe3 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -14,6 +14,12 @@ config PINCTRL_STM32F429 default MACH_STM32F429 select PINCTRL_STM32 +config PINCTRL_STM32F469 + bool "STMicroelectronics STM32F469 pin control" if COMPILE_TEST && !MACH_STM32F469 + depends on OF && IRQ_DOMAIN_HIERARCHY + default MACH_STM32F469 + select PINCTRL_STM32 + config PINCTRL_STM32F746 bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST && !MACH_STM32F746 depends on OF && IRQ_DOMAIN_HIERARCHY diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 4a1ee74..0a9a853 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o # SoC Drivers obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o +obj-$(CONFIG_PINCTRL_STM32F469) += pinctrl-stm32f469.o obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f469.c b/drivers/pinctrl/stm32/pinctrl-stm32f469.c new file mode 100644 index 0000000..4098fde --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32f469.c @@ -0,0 +1,1574 @@ +/* + * Copyright (C) Alexandre Torgue 2016 + * Author: Alexandre Torgue <alexandre.torgue@st.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32f469_pins[] = { + STM32_PIN( + PINCTRL_PIN(0, "PA0"), + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(1, "PA1"), + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(2, "PA2"), + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(12, "ETH_MDIO"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(3, "PA3"), + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(10, "LCD_B2"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D0"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(4, "PA4"), + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "OTG_HS_SOF"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(5, "PA5"), + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(11, "OTG_HS_ULPI_CK"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(6, "PA6"), + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(14, "DCMI_PIXCLK"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(7, "PA7"), + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "QUADSPI_CLK"), + STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(8, "PA8"), + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(1, "MCO1"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(11, "OTG_FS_SOF"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(9, "PA9"), + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(10, "PA10"), + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(11, "OTG_FS_ID"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(11, "PA11"), + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(8, "USART1_CTS"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(11, "OTG_FS_DM"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(12, "PA12"), + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(8, "USART1_RTS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(11, "OTG_FS_DP"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(13, "PA13"), + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(1, "JTMS SWDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(14, "PA14"), + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(1, "JTCK SWCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(15, "PA15"), + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(1, "JTDI"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(16, "PB0"), + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(10, "LCD_R3"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(17, "PB1"), + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(10, "LCD_R6"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D2"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(18, "PB2"), + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(19, "PB3"), + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(1, "JTDO TRACESWO"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(20, "PB4"), + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(1, "NJTRST"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "I2S3EXT_SD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(21, "PB5"), + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(5, "I2C1_SMBA"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D7"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(22, "PB6"), + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(11, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(23, "PB7"), + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(24, "PB8"), + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "SDIO_D4"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(25, "PB9"), + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "SDIO_D5"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(26, "PB10"), + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(10, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D3"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(27, "PB11"), + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D4"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(14, "DSIHOST_TE"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(28, "PB12"), + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D5"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "OTG_HS_ID"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(29, "PB13"), + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D6"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(30, "PB14"), + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(13, "OTG_HS_DM"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(31, "PB15"), + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(1, "RTC_REFIN"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "OTG_HS_DP"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(32, "PC0"), + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(11, "OTG_HS_ULPI_STP"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(33, "PC1"), + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(12, "ETH_MDC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(34, "PC2"), + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(12, "ETH_MII_TXD2"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(35, "PC3"), + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(12, "ETH_MII_TX_CLK"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(36, "PC4"), + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(37, "PC5"), + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(38, "PC6"), + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(6, "I2S2_MCK"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(13, "SDIO_D6"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(39, "PC7"), + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(7, "I2S3_MCK"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "SDIO_D7"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(40, "PC8"), + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "SDIO_D0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(41, "PC9"), + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(1, "MCO2"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO0"), + STM32_FUNCTION(13, "SDIO_D1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(42, "PC10"), + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO1"), + STM32_FUNCTION(13, "SDIO_D2"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(43, "PC11"), + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(6, "I2S3EXT_SD"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(10, "QUADSPI_BK2_NCS"), + STM32_FUNCTION(13, "SDIO_D3"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(44, "PC12"), + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(13, "SDIO_CK"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(45, "PC13"), + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(46, "PC14"), + STM32_FUNCTION(0, "GPIOC14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(47, "PC15"), + STM32_FUNCTION(0, "GPIOC15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(48, "PD0"), + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(49, "PD1"), + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(50, "PD2"), + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(3, "TIM3_ETR"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(13, "SDIO_CMD"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(51, "PD3"), + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(52, "PD4"), + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(53, "PD5"), + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(54, "PD6"), + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(13, "FMC_NWAIT"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(55, "PD7"), + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(56, "PD8"), + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(13, "FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(57, "PD9"), + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(13, "FMC_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(58, "PD10"), + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(13, "FMC_D15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(59, "PD11"), + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO0"), + STM32_FUNCTION(13, "FMC_A16 FMC_CLE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(60, "PD12"), + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO1"), + STM32_FUNCTION(13, "FMC_A17 FMC_ALE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(61, "PD13"), + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(62, "PD14"), + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(13, "FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(63, "PD15"), + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(13, "FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(64, "PE0"), + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(3, "TIM4_ETR"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(65, "PE1"), + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(66, "PE2"), + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO2"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(67, "PE3"), + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(68, "PE4"), + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(69, "PE5"), + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(70, "PE6"), + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(71, "PE7"), + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO0"), + STM32_FUNCTION(13, "FMC_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(72, "PE8"), + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO1"), + STM32_FUNCTION(13, "FMC_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(73, "PE9"), + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO2"), + STM32_FUNCTION(13, "FMC_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(74, "PE10"), + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO3"), + STM32_FUNCTION(13, "FMC_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(75, "PE11"), + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(13, "FMC_D8"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(76, "PE12"), + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(13, "FMC_D9"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(77, "PE13"), + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(13, "FMC_D10"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(78, "PE14"), + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(13, "FMC_D11"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(79, "PE15"), + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(13, "FMC_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(80, "PF0"), + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(81, "PF1"), + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(82, "PF2"), + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(83, "PF3"), + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(84, "PF4"), + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(85, "PF5"), + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(86, "PF6"), + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(87, "PF7"), + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_B"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(88, "PF8"), + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(11, "QUADSPI_BK1_IO0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(89, "PF9"), + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "QUADSPI_BK1_IO1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(90, "PF10"), + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(10, "QUADSPI_CLK"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(91, "PF11"), + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(13, "FMC_SDNRAS"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(92, "PF12"), + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(93, "PF13"), + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(94, "PF14"), + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(95, "PF15"), + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(96, "PG0"), + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(97, "PG1"), + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(98, "PG2"), + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(99, "PG3"), + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(100, "PG4"), + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(13, "FMC_A14 FMC_BA0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(101, "PG5"), + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(13, "FMC_A15 FMC_BA1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(102, "PG6"), + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(103, "PG7"), + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "FMC_INT"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(104, "PG8"), + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(6, "SPI6_NSS"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCLK"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(105, "PG9"), + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO2"), + STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(106, "PG10"), + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(10, "LCD_G3"), + STM32_FUNCTION(13, "FMC_NE3"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(107, "PG11"), + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(108, "PG12"), + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(6, "SPI6_MISO"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(10, "LCD_B4"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(109, "PG13"), + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(6, "SPI6_SCK"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(110, "PG14"), + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(6, "SPI6_MOSI"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO3"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(111, "PG15"), + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(13, "FMC_SDNCAS"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(112, "PH0"), + STM32_FUNCTION(0, "GPIOH0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(113, "PH1"), + STM32_FUNCTION(0, "GPIOH1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(114, "PH2"), + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO0"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(115, "PH3"), + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO1"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(116, "PH4"), + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(10, "LCD_G5"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(117, "PH5"), + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(118, "PH6"), + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(119, "PH7"), + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(120, "PH8"), + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(13, "FMC_D16"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(121, "PH9"), + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "FMC_D17"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(122, "PH10"), + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(13, "FMC_D18"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(123, "PH11"), + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(13, "FMC_D19"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(124, "PH12"), + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(13, "FMC_D20"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(125, "PH13"), + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D21"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(126, "PH14"), + STM32_FUNCTION(0, "GPIOH14"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(13, "FMC_D22"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(127, "PH15"), + STM32_FUNCTION(0, "GPIOH15"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_D23"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(128, "PI0"), + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(13, "FMC_D24"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(129, "PI1"), + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(13, "FMC_D25"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(130, "PI2"), + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(13, "FMC_D26"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(131, "PI3"), + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(13, "FMC_D27"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(132, "PI4"), + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_NBL2"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(133, "PI5"), + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_NBL3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(134, "PI6"), + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_D28"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(135, "PI7"), + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_D29"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(136, "PI8"), + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(137, "PI9"), + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D30"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(138, "PI10"), + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(13, "FMC_D31"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(139, "PI11"), + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(10, "LCD_G6"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(140, "PI12"), + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(141, "PI13"), + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(142, "PI14"), + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(143, "PI15"), + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(10, "LCD_G2"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(144, "PJ0"), + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(10, "LCD_R7"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(145, "PJ1"), + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(146, "PJ2"), + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(14, "DSIHOST_TE"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(147, "PJ3"), + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(148, "PJ4"), + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(149, "PJ5"), + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(156, "PJ12"), + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(10, "LCD_G3"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(157, "PJ13"), + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(10, "LCD_G4"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(158, "PJ14"), + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(159, "PJ15"), + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(163, "PK3"), + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(164, "PK4"), + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(165, "PK5"), + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(166, "PK6"), + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(167, "PK7"), + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32f469_match_data = { + .pins = stm32f469_pins, + .npins = ARRAY_SIZE(stm32f469_pins), +}; + +static const struct of_device_id stm32f469_pctrl_match[] = { + { + .compatible = "st,stm32f469-pinctrl", + .data = &stm32f469_match_data, + }, + { } +}; + +static struct platform_driver stm32f469_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32f469-pinctrl", + .of_match_table = stm32f469_pctrl_match, + }, +}; + +builtin_platform_driver(stm32f469_pinctrl_driver); -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings 2017-01-27 16:15 [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre TORGUE ` (2 preceding siblings ...) 2017-01-27 16:15 ` [PATCH 5/8] pinctrl: stm32: Add STM32F469 MCU support Alexandre TORGUE @ 2017-01-27 16:15 ` Alexandre TORGUE [not found] ` <1485533721-9019-7-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> 2017-01-27 16:15 ` [PATCH 7/8] ARM: Kconfig: Introduce MACH_STM32F469 flag Alexandre TORGUE 2017-01-30 14:55 ` [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre Torgue 5 siblings, 1 reply; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones Cc: linux-arm-kernel, devicetree, linux-gpio, linux-kernel Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 25d9809..4f0487d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,7 +9,8 @@ Pin controller node: Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + (b) "st,stm32f469-pinctrl" + (c) "st,stm32f746-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
[parent not found: <1485533721-9019-7-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>]
* Re: [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings [not found] ` <1485533721-9019-7-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> @ 2017-02-01 15:06 ` Rob Herring 2017-02-01 15:58 ` Alexandre Torgue 0 siblings, 1 reply; 21+ messages in thread From: Rob Herring @ 2017-02-01 15:06 UTC (permalink / raw) To: Alexandre TORGUE Cc: Maxime Coquelin, Linus Walleij, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones-QSEj5FYQhm4dnm+yROfE0A, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Fri, Jan 27, 2017 at 05:15:19PM +0100, Alexandre TORGUE wrote: > Add new compatible for stm32f469 MCU. > > Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> > > diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt > index 25d9809..4f0487d 100644 > --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt > @@ -9,7 +9,8 @@ Pin controller node: > Required properies: > - compatible: value should be one of the following: > (a) "st,stm32f429-pinctrl" > - (b) "st,stm32f746-pinctrl" > + (b) "st,stm32f469-pinctrl" > + (c) "st,stm32f746-pinctrl" Drop the a,b,c. Otherwise, you'll be changing a bunch of lines every time. With that, Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > - #address-cells: The value of this property must be 1 > - #size-cells : The value of this property must be 1 > - ranges : defines mapping between pin controller node (parent) to > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings 2017-02-01 15:06 ` Rob Herring @ 2017-02-01 15:58 ` Alexandre Torgue [not found] ` <abee01c1-da4f-97b4-258a-3ab937f620eb-qxv4g6HH51o@public.gmane.org> 0 siblings, 1 reply; 21+ messages in thread From: Alexandre Torgue @ 2017-02-01 15:58 UTC (permalink / raw) To: Rob Herring Cc: Mark Rutland, devicetree, Arnd Bergmann, linux-kernel, Linus Walleij, Russell King, Patrice Chotard, linux-gpio, Maxime Coquelin, Olof Johansson, lee.jones, linux-arm-kernel On 02/01/2017 04:06 PM, Rob Herring wrote: > On Fri, Jan 27, 2017 at 05:15:19PM +0100, Alexandre TORGUE wrote: >> Add new compatible for stm32f469 MCU. >> >> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >> index 25d9809..4f0487d 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >> @@ -9,7 +9,8 @@ Pin controller node: >> Required properies: >> - compatible: value should be one of the following: >> (a) "st,stm32f429-pinctrl" >> - (b) "st,stm32f746-pinctrl" >> + (b) "st,stm32f469-pinctrl" >> + (c) "st,stm32f746-pinctrl" > > Drop the a,b,c. Otherwise, you'll be changing a bunch of lines every > time. I completely agree. Linus, Do i need to send a v2 for this patch ? > > With that, > > Acked-by: Rob Herring <robh@kernel.org> > > >> - #address-cells: The value of this property must be 1 >> - #size-cells : The value of this property must be 1 >> - ranges : defines mapping between pin controller node (parent) to >> -- >> 1.9.1 >> ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <abee01c1-da4f-97b4-258a-3ab937f620eb-qxv4g6HH51o@public.gmane.org>]
* Re: [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings [not found] ` <abee01c1-da4f-97b4-258a-3ab937f620eb-qxv4g6HH51o@public.gmane.org> @ 2017-02-06 8:46 ` Linus Walleij [not found] ` <CACRpkdb=U+UMRqR2GKGwDzk9X_nLv0tf2dZ8LhDGceAD83LKag-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 21+ messages in thread From: Linus Walleij @ 2017-02-06 8:46 UTC (permalink / raw) To: Alexandre Torgue Cc: Rob Herring, Maxime Coquelin, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, Lee Jones, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On Wed, Feb 1, 2017 at 4:58 PM, Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org> wrote: > On 02/01/2017 04:06 PM, Rob Herring wrote: >> >> On Fri, Jan 27, 2017 at 05:15:19PM +0100, Alexandre TORGUE wrote: >>> >>> Add new compatible for stm32f469 MCU. >>> >>> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> >>> >>> diff --git >>> a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>> b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>> index 25d9809..4f0487d 100644 >>> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>> @@ -9,7 +9,8 @@ Pin controller node: >>> Required properies: >>> - compatible: value should be one of the following: >>> (a) "st,stm32f429-pinctrl" >>> - (b) "st,stm32f746-pinctrl" >>> + (b) "st,stm32f469-pinctrl" >>> + (c) "st,stm32f746-pinctrl" >> >> >> Drop the a,b,c. Otherwise, you'll be changing a bunch of lines every >> time. > > > I completely agree. > > Linus, Do i need to send a v2 for this patch ? Nopes, applied the amended v1 patch already with these changes, check the result. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CACRpkdb=U+UMRqR2GKGwDzk9X_nLv0tf2dZ8LhDGceAD83LKag-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings [not found] ` <CACRpkdb=U+UMRqR2GKGwDzk9X_nLv0tf2dZ8LhDGceAD83LKag-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2017-02-06 11:21 ` Alexandre Torgue 0 siblings, 0 replies; 21+ messages in thread From: Alexandre Torgue @ 2017-02-06 11:21 UTC (permalink / raw) To: Linus Walleij Cc: Rob Herring, Maxime Coquelin, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, Lee Jones, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On 02/06/2017 09:46 AM, Linus Walleij wrote: > On Wed, Feb 1, 2017 at 4:58 PM, Alexandre Torgue > <alexandre.torgue-qxv4g6HH51o@public.gmane.org> wrote: >> On 02/01/2017 04:06 PM, Rob Herring wrote: >>> >>> On Fri, Jan 27, 2017 at 05:15:19PM +0100, Alexandre TORGUE wrote: >>>> >>>> Add new compatible for stm32f469 MCU. >>>> >>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org> >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>>> b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>>> index 25d9809..4f0487d 100644 >>>> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt >>>> @@ -9,7 +9,8 @@ Pin controller node: >>>> Required properies: >>>> - compatible: value should be one of the following: >>>> (a) "st,stm32f429-pinctrl" >>>> - (b) "st,stm32f746-pinctrl" >>>> + (b) "st,stm32f469-pinctrl" >>>> + (c) "st,stm32f746-pinctrl" >>> >>> >>> Drop the a,b,c. Otherwise, you'll be changing a bunch of lines every >>> time. >> >> >> I completely agree. >> >> Linus, Do i need to send a v2 for this patch ? > > Nopes, applied the amended v1 patch already with these > changes, check the result. Thanks Linus! > > Yours, > Linus Walleij > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 7/8] ARM: Kconfig: Introduce MACH_STM32F469 flag 2017-01-27 16:15 [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre TORGUE ` (3 preceding siblings ...) 2017-01-27 16:15 ` [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings Alexandre TORGUE @ 2017-01-27 16:15 ` Alexandre TORGUE 2017-01-30 14:55 ` [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre Torgue 5 siblings, 0 replies; 21+ messages in thread From: Alexandre TORGUE @ 2017-01-27 16:15 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones Cc: linux-arm-kernel, devicetree, linux-gpio, linux-kernel This patch introduces the MACH_STM32F469 to make possible to only select STM32F469 pinctrl driver By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5fab553..f54402c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -888,6 +888,11 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config MACH_STM32F469 + bool "STMicrolectronics STM32F469" + depends on ARCH_STM32 + default y + config MACH_STM32F746 bool "STMicrolectronics STM32F746" depends on ARCH_STM32 -- 1.9.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl 2017-01-27 16:15 [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre TORGUE ` (4 preceding siblings ...) 2017-01-27 16:15 ` [PATCH 7/8] ARM: Kconfig: Introduce MACH_STM32F469 flag Alexandre TORGUE @ 2017-01-30 14:55 ` Alexandre Torgue 5 siblings, 0 replies; 21+ messages in thread From: Alexandre Torgue @ 2017-01-30 14:55 UTC (permalink / raw) To: Maxime Coquelin, Linus Walleij, Rob Herring, Mark Rutland, Arnd Bergmann, Russell King, Olof Johansson, Patrice Chotard, lee.jones Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio Hi, On 01/27/2017 05:15 PM, Alexandre TORGUE wrote: > This series adds support of a dedicated driver for STM32F469 MCU pinctroller. > This add generates some changes inside STM32 pinctrl driver and inside STM32 > device tree. > > Changes in STM32 pinctrl driver: > ------------------------------- > > - Add STM32F469 driver. > > - Change STM32 pinctrl core in order to use "gpio-ranges" devicetree definitions. > Indeed, on STM32F469 there an hole in BANK J. We need to declare a gpio-ranges > in gpioj controller node to handle this hole. > > Changes in STM32 device tree: > ---------------------------- > I propose a new architecture (a new file split) for pinmux definition: > > - Create a common stm32f4-pinctrl.dtsi for pinmuxing definitions > which are common between STM32F429 and STM32F469 MCU. > > - Create dedicated stm32fxxx-pinctrl.dtsi file for each MCU > (stm32f429-pinctrl.dtsi and stm32f469-pinctrl.dtsi) each one will > include stm32f4-pinctrl.dtsi. All differences (pinmuxing or GPIO > bank holes) will be put inside the dedicated files. > > This series fix a locking issue when a gpio is used as IRQ. > > Regards > Alex > > Alexandre TORGUE (8): > pinctrl: stm32: fix bad location of gpiochip_lock_as_irq > pinctrl: stm32: use gpio-ranges to declare bank range I just see typo issue in patch 1&2. I will send a V2 when more review will be done. Regards Alex > Documentation: dt: Add bindings for STM32 pinctrl > includes: dt-bindings: Rename STM32F429 pinctrl DT bindings > pinctrl: stm32: Add STM32F469 MCU support > Documentation: dt: Add new compatible to STM32 pinctrl driver bindings > ARM: Kconfig: Introduce MACH_STM32F469 flag > ARM: dts: stm32: create dedicated files for pinctrl definitions > > .../bindings/pinctrl/st,stm32-pinctrl.txt | 57 +- > arch/arm/Kconfig | 5 + > arch/arm/boot/dts/stm32429i-eval.dts | 1 + > arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 196 +++ > arch/arm/boot/dts/stm32f429-disco.dts | 1 + > arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 106 ++ > arch/arm/boot/dts/stm32f429.dtsi | 153 -- > arch/arm/boot/dts/stm32f469-disco.dts | 1 + > arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 107 ++ > drivers/pinctrl/stm32/Kconfig | 6 + > drivers/pinctrl/stm32/Makefile | 1 + > drivers/pinctrl/stm32/pinctrl-stm32.c | 129 +- > drivers/pinctrl/stm32/pinctrl-stm32f469.c | 1574 ++++++++++++++++++++ > include/dt-bindings/pinctrl/stm32f4-pinfunc.h | 1302 ++++++++++++++++ > include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1239 --------------- > 15 files changed, 3414 insertions(+), 1464 deletions(-) > create mode 100644 arch/arm/boot/dts/stm32f4-pinctrl.dtsi > create mode 100644 arch/arm/boot/dts/stm32f429-pinctrl.dtsi > create mode 100644 arch/arm/boot/dts/stm32f469-pinctrl.dtsi > create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f469.c > create mode 100644 include/dt-bindings/pinctrl/stm32f4-pinfunc.h > delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h > ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2017-03-27 10:23 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
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2017-01-27 16:15 [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre TORGUE
2017-01-27 16:15 ` [PATCH 1/8] pinctrl: stm32: fix bad location of gpiochip_lock_as_irq Alexandre TORGUE
2017-01-30 15:15 ` Linus Walleij
[not found] ` <1485533721-9019-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
2017-01-27 16:15 ` [PATCH 2/8] pinctrl: stm32: use gpio-ranges to declare bank range Alexandre TORGUE
2017-01-30 15:19 ` Linus Walleij
2017-01-30 16:29 ` Alexandre Torgue
2017-02-01 15:01 ` Linus Walleij
2017-03-27 10:23 ` Alexandre Torgue
2017-01-27 16:15 ` [PATCH 3/8] Documentation: dt: Add bindings for STM32 pinctrl Alexandre TORGUE
2017-02-01 15:04 ` Rob Herring
2017-02-06 8:45 ` Linus Walleij
2017-01-27 16:15 ` [PATCH 4/8] includes: dt-bindings: Rename STM32F429 pinctrl DT bindings Alexandre TORGUE
2017-01-27 16:15 ` [PATCH 8/8] ARM: dts: stm32: create dedicated files for pinctrl definitions Alexandre TORGUE
2017-01-27 16:15 ` [PATCH 5/8] pinctrl: stm32: Add STM32F469 MCU support Alexandre TORGUE
2017-01-27 16:15 ` [PATCH 6/8] Documentation: dt: Add new compatible to STM32 pinctrl driver bindings Alexandre TORGUE
[not found] ` <1485533721-9019-7-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
2017-02-01 15:06 ` Rob Herring
2017-02-01 15:58 ` Alexandre Torgue
[not found] ` <abee01c1-da4f-97b4-258a-3ab937f620eb-qxv4g6HH51o@public.gmane.org>
2017-02-06 8:46 ` Linus Walleij
[not found] ` <CACRpkdb=U+UMRqR2GKGwDzk9X_nLv0tf2dZ8LhDGceAD83LKag-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-02-06 11:21 ` Alexandre Torgue
2017-01-27 16:15 ` [PATCH 7/8] ARM: Kconfig: Introduce MACH_STM32F469 flag Alexandre TORGUE
2017-01-30 14:55 ` [PATCH 0/8] Add STM32F469 pinctrl and fix issues in STM32 pinctrl Alexandre Torgue
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