From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21533C433EF for ; Thu, 16 Sep 2021 21:42:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF8F16120C for ; Thu, 16 Sep 2021 21:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235717AbhIPVnj (ORCPT ); Thu, 16 Sep 2021 17:43:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233725AbhIPVni (ORCPT ); Thu, 16 Sep 2021 17:43:38 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76CEBC061574 for ; Thu, 16 Sep 2021 14:42:17 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id x27so24192917lfu.5 for ; Thu, 16 Sep 2021 14:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ngsmooqXNsHgBKfkElGn8tQBGgJkqsh0GOhjTmfiKjs=; b=Kj9Y8gcTt4TgGUzYJFJ2xQFSkgUMMob94bgC1CKrrISQc/ZSgNlmv+sU681xqDsY9r Vwr2bEDqT4PrrP6NGXbI6Q6hxkGHLgXD+s5jnc8DEjWnPw9wsqsHMrCxxcYEKh8GzUJL +DPg40KBstQlzyJnALmo5nNGSDc73CSMDqayIMQKLpz79awy/N2BZe7+6NM2rVYXH7nK IX1v5ScwZvAdt0W6wT8BvHgVja6ZNrNpHFuEUy9w8PPKzRYMAYJuXznsbmI2uZUVfZkv iq79DmuCJVmruIvZjE4/I++5RjQckQuo6GeO+jAit+ESWIQe8n7O5SzLuipGCAi1UM9E ObSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ngsmooqXNsHgBKfkElGn8tQBGgJkqsh0GOhjTmfiKjs=; b=R7YCDy3mTRAUhDBlIPg9zCSspBdggljULGVxJiYtbidfBdwRFlGXmWLlZvlTiaucS6 MCmjl5xC1UV8dJ7Y3JLgxkuQXjx6E/JqTm0FG6n0a0PuFIzmc+wdzds3/YXTiFGqbaMh hJbQM2r26DLLex9X7NeYHwRkEIkzgQBYDYHd9AIZoLlOvlICn6/qLtb28E++J9FYiHBR y611VQmuZfkBKEirmTTJo2etdSklBaNbD5duFwQX6ImHx74mgjeEZGhtyYSCVuq8pc41 CCgCHvrH1/eYr1ksjJQJais4BlfNti/YRs0MGuVMdm1XgWi9Sp5rtUNnrgtdLDcwy4II QFwg== X-Gm-Message-State: AOAM530S+yUMpu+iCPst55q5024eqCXRTCG7fPLvW3zS+gzJreAcKy0g HpOeOzNVDhTmjmkNc58fCIBY3qA9fJsbozLY6tQdXQ== X-Google-Smtp-Source: ABdhPJx10db8eaZ+I8ehLsyREKhLW1AoewhBK0s2SWPdi0X7r9/ZilW0iCTr41ebckupWObS1/ifTUFd4TeyT/L6S/g= X-Received: by 2002:a05:6512:3c92:: with SMTP id h18mr5542169lfv.656.1631828535849; Thu, 16 Sep 2021 14:42:15 -0700 (PDT) MIME-Version: 1.0 References: <20210824164801.28896-1-lakshmi.sowjanya.d@intel.com> <20210824164801.28896-8-lakshmi.sowjanya.d@intel.com> In-Reply-To: <20210824164801.28896-8-lakshmi.sowjanya.d@intel.com> From: Linus Walleij Date: Thu, 16 Sep 2021 23:42:04 +0200 Message-ID: Subject: Re: [RFC PATCH v1 07/20] gpio: Add output event generation method to GPIOLIB and PMC Driver To: "D, Lakshmi Sowjanya" , "thierry.reding@gmail.com" , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Lee Jones , "open list:PWM SUBSYSTEM" Cc: "open list:GPIO SUBSYSTEM" , Bartosz Golaszewski , linux-kernel , Mark Gross , Andy Shevchenko , "Saha, Tamal" , bala.senthil@intel.com, Dipen Patel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Lakshmi, On Tue, Aug 24, 2021 at 6:48 PM wrote: > From: Lakshmi Sowjanya D > > Intel Timed I/O hardware supports output scheduled in hardware. Enable > this functionality using GPIOlib > > Adds GPIOlib generate_output() hook into the driver. The driver is > supplied with a timestamp in terms of realtime system clock (the same > used for input timestamping). The driver must know how to translate this > into a timebase meaningful for the hardware. > > Adds userspace write() interface. Output can be selected using the line > event create ioctl. The write() interface takes a single timestamp > event request parameter. An output edge rising or falling is generated > for each event request. > > The user application supplies a trigger time in terms of the realtime > clock the driver converts this into the corresponding ART clock value > that is used to 'arm' the output. > > Work around device quirk that doesn't allow the output to be explicitly > set. Instead, count the output edges and insert an additional edge as > needed to reset the output to zero. > > Co-developed-by: Christopher Hall > Signed-off-by: Christopher Hall > Signed-off-by: Tamal Saha > Signed-off-by: Lakshmi Sowjanya D > Reviewed-by: Mark Gross So this is some street organ machine that generates sequences with determined timing between positive and negative edges right? I can't see how this hardware is different from a PWM, or well I do to some extent, you can control the period of several subsequent waves, but that is really just an elaborate version of PWM in my book. It seems to me that this part of the functionality belongs in the PWM subsystem which already has interfaces for similar things, and you should probably extend PWM to handle random waveforms rather than trying to shoehorn this into the GPIO subsystem. Yours, Linus Walleij