From: Linus Walleij <linus.walleij@linaro.org>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>
Subject: Re: [PATCH 2/3] pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs
Date: Tue, 27 Oct 2015 13:31:25 +0100 [thread overview]
Message-ID: <CACRpkdYRc96HEAsUSryMu3v2-p9siN+3WR3oTXK1N9ExXRUuYA@mail.gmail.com> (raw)
In-Reply-To: <1445422125-72075-3-git-send-email-mika.westerberg@linux.intel.com>
On Wed, Oct 21, 2015 at 12:08 PM, Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:
> Reserved for ACPI actually means that in such case the GPIO hardware will
> not update the interrupt status register (GPI_IS) even if the pin is
> configured to trigger an interrupt. It will update GPI_GPE_STS instead and
> does not trigger an interrupt.
>
> Allow using such pins as GPIOs, only prevent their usage as interrupts.
>
> We also rename function intel_pad_reserved_for_acpi() to be
> intel_pad_acpi_mode() which reflects the actual meaning better.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Patch applied.
Yours,
Linus Walleij
next prev parent reply other threads:[~2015-10-27 12:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-21 10:08 [PATCH 0/3] pinctrl: Add support for Intel Broxton SoC Mika Westerberg
2015-10-21 10:08 ` [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt Mika Westerberg
2015-10-27 12:29 ` Linus Walleij
2015-10-21 10:08 ` [PATCH 2/3] pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs Mika Westerberg
2015-10-27 12:31 ` Linus Walleij [this message]
2015-10-21 10:08 ` [PATCH 3/3] pinctrl: intel: Add Intel Broxton pin controller support Mika Westerberg
2015-10-27 12:33 ` Linus Walleij
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