* [PATCH] pinctrl: mediatek: Fix the drive register definition of some Pins
@ 2023-01-18 6:21 Guodong Liu
2023-01-26 13:42 ` Linus Walleij
0 siblings, 1 reply; 2+ messages in thread
From: Guodong Liu @ 2023-01-18 6:21 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Matthias Brugger, Light Hsieh,
Rob Herring, AngeloGioacchino Del Regno
Cc: linux-mediatek, linux-gpio, linux-kernel, linux-arm-kernel,
Zhiyong Tao, Guodong Liu
The drive adjustment register definition of gpio13 and gpio81 is wrong:
"the start address for the range" of gpio18 is corrected to 0x000,
"the start bit for the first register within the range" of gpio81 is
corrected to 24.
Fixes: 6cf5e9ef362a ("pinctrl: add pinctrl driver on mt8195")
Signed-off-by: Guodong Liu <Guodong.Liu@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mt8195.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
index 563693d3d4c2..c21ca33b2d59 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
@@ -659,7 +659,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3),
PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3),
- PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3),
+ PIN_FIELD_BASE(13, 13, 4, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3),
@@ -708,7 +708,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3),
- PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3),
+ PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3),
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] pinctrl: mediatek: Fix the drive register definition of some Pins
2023-01-18 6:21 [PATCH] pinctrl: mediatek: Fix the drive register definition of some Pins Guodong Liu
@ 2023-01-26 13:42 ` Linus Walleij
0 siblings, 0 replies; 2+ messages in thread
From: Linus Walleij @ 2023-01-26 13:42 UTC (permalink / raw)
To: Guodong Liu
Cc: Sean Wang, Matthias Brugger, Light Hsieh, Rob Herring,
AngeloGioacchino Del Regno, linux-mediatek, linux-gpio,
linux-kernel, linux-arm-kernel, Zhiyong Tao
On Wed, Jan 18, 2023 at 7:21 AM Guodong Liu <Guodong.Liu@mediatek.com> wrote:
> The drive adjustment register definition of gpio13 and gpio81 is wrong:
> "the start address for the range" of gpio18 is corrected to 0x000,
> "the start bit for the first register within the range" of gpio81 is
> corrected to 24.
>
> Fixes: 6cf5e9ef362a ("pinctrl: add pinctrl driver on mt8195")
> Signed-off-by: Guodong Liu <Guodong.Liu@mediatek.com>
Patch applied for fixes.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 2+ messages in thread
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