* [PATCH v3 0/3] Add pinctrl support for Sky1
@ 2025-10-14 1:57 Gary Yang
2025-10-14 1:57 ` [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Gary Yang
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Gary Yang @ 2025-10-14 1:57 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt, conor+dt
Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
cix-kernel-upstream, Gary Yang
Patch 1: Add dt-binding doc for pinctrl on Sky1
Patch 2: Add pin-controller driver for sky1
Patch 3: Add pinctrl nodes for sky1
Changes for v3:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-pinctrl.yaml
scripts/checkpatch.pl 000*.patch
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
- Re-order the patch set, and move dt-bindings to the 1st patch.
- Refine the pinctrl driver with SKY_PINFUNCTION macro
- Fix warnings when make dt_binding_check
Changes for v2:
- restructure the pinctrl driver to support pinmux=<..>
- redefine pinmux macros
- move header file from dt-bindings to dts
- fix the code-style issues
Gary Yang (3):
dt-bindings: pinctrl: Add cix,sky1-pinctrl
pinctrl: cix: Add pin-controller support for sky1
arm64: dts: cix: Add pinctrl nodes for sky1
.../bindings/pinctrl/cix,sky1-pinctrl.yaml | 84 +++
arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 32 +
arch/arm64/boot/dts/cix/sky1-pinfunc.h | 417 +++++++++++++
arch/arm64/boot/dts/cix/sky1.dtsi | 10 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/cix/Kconfig | 14 +
drivers/pinctrl/cix/Makefile | 4 +
drivers/pinctrl/cix/pinctrl-sky1-base.c | 558 +++++++++++++++++
drivers/pinctrl/cix/pinctrl-sky1.c | 559 ++++++++++++++++++
drivers/pinctrl/cix/pinctrl-sky1.h | 48 ++
11 files changed, 1728 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
create mode 100644 arch/arm64/boot/dts/cix/sky1-pinfunc.h
create mode 100644 drivers/pinctrl/cix/Kconfig
create mode 100644 drivers/pinctrl/cix/Makefile
create mode 100644 drivers/pinctrl/cix/pinctrl-sky1-base.c
create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.c
create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.h
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl
2025-10-14 1:57 [PATCH v3 0/3] Add pinctrl support for Sky1 Gary Yang
@ 2025-10-14 1:57 ` Gary Yang
2025-10-14 10:44 ` Linus Walleij
2025-10-14 1:57 ` [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1 Gary Yang
2025-10-14 1:57 ` [PATCH v3 3/3] arm64: dts: cix: Add pinctrl nodes " Gary Yang
2 siblings, 1 reply; 11+ messages in thread
From: Gary Yang @ 2025-10-14 1:57 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt, conor+dt
Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
cix-kernel-upstream, Gary Yang
The pin-controller is used to control the Soc pins.
There are two pin-controllers on Cix Sky1 platform.
One is used under S0 state, the other is used under
S0 and S5 state.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
.../bindings/pinctrl/cix,sky1-pinctrl.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
new file mode 100644
index 000000000000..6c83eb47f974
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 Pin Controller
+
+maintainers:
+ - Gary Yang <gary.yang@cixtech.com>
+
+description:
+ The pin-controller is used to control Soc pins. There are two pin-controllers
+ on Cix Sky1 platform. one is used under S0 state, the other one is used under
+ S0 and S5 state.
+
+properties:
+ compatible:
+ enum:
+ - cix,sky1-iomuxc
+ - cix,sky1-iomuxc-s5
+
+ reg:
+ items:
+ - description: gpio base
+
+required:
+ - compatible
+ - reg
+
+# Client device subnode's properties
+patternProperties:
+ 'pins$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '(^pins|pins?$)':
+ type: object
+ additionalProperties: false
+ description:
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, and drive strength.
+
+ properties:
+ pinmux:
+ description:
+ Values are constructed from pin number and mux setting and are
+ defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly.
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ drive-strength:
+ description:
+ Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
+ defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h.
+
+ required:
+ - pinmux
+
+additionalProperties: false
+
+examples:
+ # Pinmux controller node
+ - |
+ #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
+ #define DS_LEVEL4 (4)
+ iomuxc: pinctrl@4170000 {
+ compatible = "cix,sky1-iomuxc";
+ reg = <0x4170000 0x1000>;
+
+ wifi_vbat_gpio: wifi-vbat-gpio-pins {
+ pins {
+ pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
+ bias-pull-up;
+ drive-strength = <DS_LEVEL4>;
+ };
+ };
+ };
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1
2025-10-14 1:57 [PATCH v3 0/3] Add pinctrl support for Sky1 Gary Yang
2025-10-14 1:57 ` [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Gary Yang
@ 2025-10-14 1:57 ` Gary Yang
2025-10-14 10:57 ` Linus Walleij
2025-10-14 1:57 ` [PATCH v3 3/3] arm64: dts: cix: Add pinctrl nodes " Gary Yang
2 siblings, 1 reply; 11+ messages in thread
From: Gary Yang @ 2025-10-14 1:57 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt, conor+dt
Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
cix-kernel-upstream, Gary Yang
There are two pin-controllers on Cix Sky1 platform.
one is used under S0 state, the other is used under S0 and S5 state.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/cix/Kconfig | 14 +
drivers/pinctrl/cix/Makefile | 4 +
drivers/pinctrl/cix/pinctrl-sky1-base.c | 558 +++++++++++++++++++++++
drivers/pinctrl/cix/pinctrl-sky1.c | 559 ++++++++++++++++++++++++
drivers/pinctrl/cix/pinctrl-sky1.h | 48 ++
7 files changed, 1185 insertions(+)
create mode 100644 drivers/pinctrl/cix/Kconfig
create mode 100644 drivers/pinctrl/cix/Makefile
create mode 100644 drivers/pinctrl/cix/pinctrl-sky1-base.c
create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.c
create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ddd11668457c..a5b7177be115 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -653,6 +653,7 @@ source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
+source "drivers/pinctrl/cix/Kconfig"
source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 909ab89a56d2..8f353fc38e0e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-y += bcm/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += cirrus/
+obj-y += cix/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
obj-y += mediatek/
diff --git a/drivers/pinctrl/cix/Kconfig b/drivers/pinctrl/cix/Kconfig
new file mode 100644
index 000000000000..42e064b6e7a2
--- /dev/null
+++ b/drivers/pinctrl/cix/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config PINCTRL_SKY1_BASE
+ tristate
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select REGMAP
+
+config PINCTRL_SKY1
+ tristate "Cix Sky1 pinctrl driver"
+ depends on ARCH_CIX
+ select PINCTRL_SKY1_BASE
+ help
+ Say Y here to enable the sky1 pinctrl driver
diff --git a/drivers/pinctrl/cix/Makefile b/drivers/pinctrl/cix/Makefile
new file mode 100644
index 000000000000..22685d6a107b
--- /dev/null
+++ b/drivers/pinctrl/cix/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+# Cix Sky1 pin control drivers
+obj-$(CONFIG_PINCTRL_SKY1_BASE) += pinctrl-sky1-base.o
+obj-$(CONFIG_PINCTRL_SKY1) += pinctrl-sky1.o
diff --git a/drivers/pinctrl/cix/pinctrl-sky1-base.c b/drivers/pinctrl/cix/pinctrl-sky1-base.c
new file mode 100644
index 000000000000..5ce5c40c8d54
--- /dev/null
+++ b/drivers/pinctrl/cix/pinctrl-sky1-base.c
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Author: Jerry Zhu <Jerry.Zhu@cixtech.com>
+// Author: Gary Yang <gary.yang@cixtech.com>
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "pinctrl-sky1.h"
+
+#define SKY1_PIN_SIZE (4)
+#define SKY1_MUX_MASK GENMASK(8, 7)
+#define SKY1_MUX_SHIFT (7)
+#define SKY1_PULLCONF_MASK GENMASK(6, 5)
+#define SKY1_PULLUP_BIT (6)
+#define SKY1_PULLDN_BIT (5)
+#define SKY1_DS_MASK GENMASK(3, 0)
+
+#define CIX_PIN_NO_SHIFT (8)
+#define CIX_PIN_FUN_MASK GENMASK(1, 0)
+#define CIX_GET_PIN_NO(x) ((x) >> CIX_PIN_NO_SHIFT)
+#define CIX_GET_PIN_FUNC(x) ((x) & CIX_PIN_FUN_MASK)
+
+static const char * const sky1_gpio_functions[] = {
+ "func0", "func1", "func2", "func3",
+};
+
+static bool sky1_pctrl_is_function_valid(struct sky1_pinctrl *spctl,
+ u32 pin_num, u32 fnum)
+{
+ int i;
+
+ for (i = 0; i < spctl->info->npins; i++) {
+ const struct sky1_pin_desc *pin = spctl->info->pins + i;
+
+ if (pin->pin.number == pin_num) {
+ if (fnum < pin->nfunc)
+ return true;
+
+ break;
+ }
+ }
+
+ return false;
+}
+
+static int sky1_pctrl_dt_node_to_map_func(struct sky1_pinctrl *spctl,
+ u32 pin, u32 fnum, struct sky1_pinctrl_group *grp,
+ struct pinctrl_map **map, unsigned int *reserved_maps,
+ unsigned int *num_maps)
+{
+ bool ret;
+
+ if (*num_maps == *reserved_maps)
+ return -ENOSPC;
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[*num_maps].data.mux.group = grp->name;
+
+ ret = sky1_pctrl_is_function_valid(spctl, pin, fnum);
+ if (!ret) {
+ dev_err(spctl->dev, "invalid function %d on pin %d .\n",
+ fnum, pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].data.mux.function = sky1_gpio_functions[fnum];
+ (*num_maps)++;
+
+ return 0;
+}
+
+static struct sky1_pinctrl_group *
+sky1_pctrl_find_group_by_pin(struct sky1_pinctrl *spctl, u32 pin)
+{
+ int i;
+
+ for (i = 0; i < spctl->info->npins; i++) {
+ struct sky1_pinctrl_group *grp =
+ (struct sky1_pinctrl_group *)spctl->groups + i;
+
+ if (grp->pin == pin)
+ return grp;
+ }
+
+ return NULL;
+}
+
+static int sky1_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *node,
+ struct pinctrl_map **map,
+ unsigned int *reserved_maps,
+ unsigned int *num_maps)
+{
+ struct property *pins;
+ u32 pinfunc, pin, func;
+ int num_pins, num_funcs, maps_per_pin;
+ unsigned long *configs;
+ unsigned int num_configs;
+ bool has_config = false;
+ int i, err;
+ unsigned int reserve = 0;
+ struct sky1_pinctrl_group *grp;
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+
+ pins = of_find_property(node, "pinmux", NULL);
+ if (!pins) {
+ dev_err(spctl->dev, "missing pins property in node %pOFn .\n",
+ node);
+ return -EINVAL;
+ }
+
+ err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
+ &num_configs);
+ if (err)
+ return err;
+
+ if (num_configs)
+ has_config = true;
+
+ num_pins = pins->length / sizeof(u32);
+ num_funcs = num_pins;
+ maps_per_pin = 0;
+ if (num_funcs)
+ maps_per_pin++;
+ if (has_config && num_pins >= 1)
+ maps_per_pin++;
+
+ if (!num_pins || !maps_per_pin) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ reserve = num_pins * maps_per_pin;
+
+ err = pinctrl_utils_reserve_map(pctldev, map,
+ reserved_maps, num_maps, reserve);
+ if (err < 0)
+ goto exit;
+
+ for (i = 0; i < num_pins; i++) {
+ err = of_property_read_u32_index(node, "pinmux",
+ i, &pinfunc);
+ if (err)
+ goto exit;
+
+ pin = CIX_GET_PIN_NO(pinfunc);
+ func = CIX_GET_PIN_FUNC(pinfunc);
+ pctldev->num_functions = ARRAY_SIZE(sky1_gpio_functions);
+
+ if (pin >= pctldev->desc->npins ||
+ func >= pctldev->num_functions) {
+ dev_err(spctl->dev, "invalid pins value.\n");
+ err = -EINVAL;
+ goto exit;
+ }
+
+ grp = sky1_pctrl_find_group_by_pin(spctl, pin);
+ if (!grp) {
+ dev_err(spctl->dev, "unable to match pin %d to group\n",
+ pin);
+ err = -EINVAL;
+ goto exit;
+ }
+
+ err = sky1_pctrl_dt_node_to_map_func(spctl, pin, func, grp,
+ map, reserved_maps, num_maps);
+ if (err < 0)
+ goto exit;
+
+ if (has_config) {
+ err = pinctrl_utils_add_map_configs(pctldev, map,
+ reserved_maps, num_maps, grp->name,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (err < 0)
+ goto exit;
+ }
+ }
+
+ err = 0;
+
+exit:
+ kfree(configs);
+ return err;
+}
+
+static int sky1_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map, unsigned int *num_maps)
+{
+ unsigned int reserved_maps;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+ reserved_maps = 0;
+
+ for_each_child_of_node_scoped(np_config, np) {
+ ret = sky1_pctrl_dt_subnode_to_map(pctldev, np, map,
+ &reserved_maps, num_maps);
+ if (ret < 0) {
+ pinctrl_utils_free_map(pctldev, *map, *num_maps);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void sky1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map,
+ unsigned int num_maps)
+{
+ kfree(map);
+}
+
+static int sky1_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return spctl->info->npins;
+}
+
+static const char *sky1_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return spctl->groups[group].name;
+}
+
+static int sky1_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = (unsigned int *)&spctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static void sky1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned int offset)
+{
+ seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static const struct pinctrl_ops sky1_pctrl_ops = {
+ .dt_node_to_map = sky1_pctrl_dt_node_to_map,
+ .dt_free_map = sky1_dt_free_map,
+ .get_groups_count = sky1_pctrl_get_groups_count,
+ .get_group_name = sky1_pctrl_get_group_name,
+ .get_group_pins = sky1_pctrl_get_group_pins,
+ .pin_dbg_show = sky1_pin_dbg_show,
+};
+
+static int sky1_pmx_set_one_pin(struct sky1_pinctrl *spctl,
+ unsigned int pin, unsigned char muxval)
+{
+ u32 reg_val;
+ u32 *pin_reg;
+
+ pin_reg = spctl->base + pin * SKY1_PIN_SIZE;
+ reg_val = readl(pin_reg);
+ reg_val &= ~SKY1_MUX_MASK;
+ reg_val |= muxval << SKY1_MUX_SHIFT;
+ writel(reg_val, pin_reg);
+
+ dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin * SKY1_PIN_SIZE, reg_val);
+ return 0;
+}
+
+static int sky1_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ bool ret;
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+ struct sky1_pinctrl_group *g =
+ (struct sky1_pinctrl_group *)spctl->groups + group;
+
+ ret = sky1_pctrl_is_function_valid(spctl, g->pin, function);
+ if (!ret) {
+ dev_err(spctl->dev, "invalid function %d on group %d .\n",
+ function, group);
+ return -EINVAL;
+ }
+
+ sky1_pmx_set_one_pin(spctl, g->pin, function);
+ return 0;
+}
+
+static int sky1_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(sky1_gpio_functions);
+}
+
+static const char *sky1_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return sky1_gpio_functions[selector];
+}
+
+static int sky1_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct sky1_pinctrl_soc_info *info = spctl->info;
+
+ *groups = spctl->grp_names;
+ *num_groups = info->npins;
+
+ return 0;
+}
+
+static const struct pinmux_ops sky1_pmx_ops = {
+ .get_functions_count = sky1_pmx_get_funcs_cnt,
+ .get_function_groups = sky1_pmx_get_func_groups,
+ .get_function_name = sky1_pmx_get_func_name,
+ .set_mux = sky1_pmx_set_mux,
+};
+
+static int sky1_pconf_set_pull_select(struct sky1_pinctrl *spctl,
+ unsigned int pin, bool enable, bool isup)
+{
+ u32 reg_val, reg_pullsel = 0;
+ u32 *pin_reg;
+
+ pin_reg = spctl->base + pin * SKY1_PIN_SIZE;
+ reg_val = readl(pin_reg);
+ reg_val &= ~SKY1_PULLCONF_MASK;
+
+ if (!enable)
+ goto update;
+
+ if (isup)
+ reg_pullsel = BIT(SKY1_PULLUP_BIT);
+ else
+ reg_pullsel = BIT(SKY1_PULLDN_BIT);
+
+update:
+ reg_val |= reg_pullsel;
+ writel(reg_val, pin_reg);
+
+ dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin * SKY1_PIN_SIZE, reg_val);
+ return 0;
+}
+
+static int sky1_pconf_set_driving(struct sky1_pinctrl *spctl,
+ unsigned int pin, unsigned char driving)
+{
+ unsigned int reg_val;
+ u32 *pin_reg;
+
+ if (pin >= spctl->info->npins)
+ return -EINVAL;
+
+ pin_reg = spctl->base + pin * SKY1_PIN_SIZE;
+ reg_val = readl(pin_reg);
+ reg_val &= ~SKY1_DS_MASK;
+ reg_val |= (driving & SKY1_DS_MASK);
+ writel(reg_val, pin_reg);
+
+ dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin * SKY1_PIN_SIZE, reg_val);
+
+ return 0;
+}
+
+static int sky1_pconf_parse_conf(struct pinctrl_dev *pctldev,
+ unsigned int pin, enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ int ret = 0;
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ ret = sky1_pconf_set_pull_select(spctl, pin, false, false);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = sky1_pconf_set_pull_select(spctl, pin, true, true);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = sky1_pconf_set_pull_select(spctl, pin, true, false);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ ret = sky1_pconf_set_driving(spctl, pin, arg);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int sky1_pconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ unsigned long *config)
+{
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+ struct sky1_pinctrl_group *g = &spctl->groups[group];
+
+ *config = g->config;
+
+ return 0;
+}
+
+static int sky1_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int group,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
+ struct sky1_pinctrl_group *g = &spctl->groups[group];
+ int i, ret;
+
+ for (i = 0; i < num_configs; i++) {
+ ret = sky1_pconf_parse_conf(pctldev, g->pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ if (ret < 0)
+ return ret;
+
+ g->config = configs[i];
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops sky1_pinconf_ops = {
+ .pin_config_group_get = sky1_pconf_group_get,
+ .pin_config_group_set = sky1_pconf_group_set,
+};
+
+static int sky1_pctrl_build_state(struct platform_device *pdev)
+{
+ struct sky1_pinctrl *spctl = platform_get_drvdata(pdev);
+ const struct sky1_pinctrl_soc_info *info = spctl->info;
+ int i;
+
+ /* Allocate groups */
+ spctl->groups = devm_kcalloc(&pdev->dev, info->npins,
+ sizeof(*spctl->groups), GFP_KERNEL);
+ if (!spctl->groups)
+ return -ENOMEM;
+
+ /* We assume that one pin is one group, use pin name as group name. */
+ spctl->grp_names = devm_kcalloc(&pdev->dev, info->npins,
+ sizeof(*spctl->grp_names), GFP_KERNEL);
+ if (!spctl->grp_names)
+ return -ENOMEM;
+
+ for (i = 0; i < info->npins; i++) {
+ const struct sky1_pin_desc *pin = spctl->info->pins + i;
+ struct sky1_pinctrl_group *group =
+ (struct sky1_pinctrl_group *)spctl->groups + i;
+
+ group->name = pin->pin.name;
+ group->pin = pin->pin.number;
+ spctl->grp_names[i] = pin->pin.name;
+ }
+
+ return 0;
+}
+
+int sky1_base_pinctrl_probe(struct platform_device *pdev,
+ const struct sky1_pinctrl_soc_info *info)
+{
+ struct pinctrl_desc *sky1_pinctrl_desc;
+ struct sky1_pinctrl *spctl;
+ struct pinctrl_pin_desc *pins;
+ int ret, i;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+
+ /* Create state holders etc for this driver */
+ spctl = devm_kzalloc(&pdev->dev, sizeof(*spctl), GFP_KERNEL);
+ if (!spctl)
+ return -ENOMEM;
+
+ spctl->info = info;
+ platform_set_drvdata(pdev, spctl);
+
+ spctl->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(spctl->base))
+ return PTR_ERR(spctl->base);
+
+ sky1_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*sky1_pinctrl_desc),
+ GFP_KERNEL);
+ if (!sky1_pinctrl_desc)
+ return -ENOMEM;
+
+ pins = devm_kcalloc(&pdev->dev, info->npins, sizeof(*pins),
+ GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+ for (i = 0; i < info->npins; i++)
+ pins[i] = info->pins[i].pin;
+
+ ret = sky1_pctrl_build_state(pdev);
+ if (ret)
+ return ret;
+
+ sky1_pinctrl_desc->name = dev_name(&pdev->dev);
+ sky1_pinctrl_desc->pins = pins;
+ sky1_pinctrl_desc->npins = info->npins;
+ sky1_pinctrl_desc->pctlops = &sky1_pctrl_ops;
+ sky1_pinctrl_desc->pmxops = &sky1_pmx_ops;
+ sky1_pinctrl_desc->confops = &sky1_pinconf_ops;
+ sky1_pinctrl_desc->owner = THIS_MODULE;
+ spctl->dev = &pdev->dev;
+ ret = devm_pinctrl_register_and_init(&pdev->dev,
+ sky1_pinctrl_desc, spctl,
+ &spctl->pctl);
+ if (ret) {
+ dev_err(&pdev->dev, "could not register SKY1 pinctrl driver\n");
+ return ret;
+ }
+
+ pinctrl_provide_dummies();
+ dev_dbg(&pdev->dev, "initialized SKY1 pinctrl driver\n");
+
+ return pinctrl_enable(spctl->pctl);
+}
+EXPORT_SYMBOL_GPL(sky1_base_pinctrl_probe);
+
+
+MODULE_AUTHOR("Jerry Zhu <Jerry.Zhu@cixtech.com>");
+MODULE_DESCRIPTION("Cix SKy1 pinctrl base driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/cix/pinctrl-sky1.c b/drivers/pinctrl/cix/pinctrl-sky1.c
new file mode 100644
index 000000000000..7864c66593c6
--- /dev/null
+++ b/drivers/pinctrl/cix/pinctrl-sky1.c
@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Author: Jerry Zhu <Jerry.Zhu@cixtech.com>
+// Author: Gary Yang <gary.yang@cixtech.com>
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include "linux/stddef.h"
+
+#include "../core.h"
+#include "pinctrl-sky1.h"
+
+/* Pad names for the s5 domain pinmux subsystem */
+static const char * const gpio1_group[] = {"GPIO1"};
+static const char * const gpio2_group[] = {"GPIO2"};
+static const char * const gpio3_group[] = {"GPIO3"};
+static const char * const gpio4_group[] = {"GPIO4"};
+static const char * const gpio5_group[] = {"GPIO5"};
+static const char * const gpio6_group[] = {"GPIO6"};
+static const char * const gpio7_group[] = {"GPIO7"};
+static const char * const gpio8_group[] = {"GPIO8"};
+static const char * const gpio9_group[] = {"GPIO9"};
+static const char * const gpio10_group[] = {"GPIO10"};
+static const char * const gpio11_group[] = {"GPIO11"};
+static const char * const gpio12_group[] = {"GPIO12"};
+static const char * const gpio13_group[] = {"GPIO13"};
+static const char * const gpio14_group[] = {"GPIO14"};
+static const char * const rsmrst_group[] = { };
+static const char * const srst_group[] = { };
+static const char * const slp_s3_group[] = { };
+static const char * const slp_s5_group[] = { };
+static const char * const pwrgd_group[] = { };
+static const char * const pwrok_group[] = { };
+static const char * const pwrbtn_group[] = { };
+static const char * const ddrio_gate_group[] = { };
+static const char * const jtag_gpio_group[] = { };
+static const char * const jtag_tck_group[] = { };
+static const char * const jtag_tdi_group[] = { };
+static const char * const jtag_tdo_group[] = { };
+static const char * const tms_group[] = { };
+static const char * const trsl_group[] = { };
+static const char * const sfi_i2c0_scl_group[] = {"SFI_I2C0_SCL",
+ "SFI_I3C0_SCL"};
+static const char * const sfi_i2c0_sda_group[] = {"SFI_I2C0_SDA",
+ "SFI_I3C0_SDA"};
+static const char * const sfi_i2c1_scl_group[] = {"SFI_I2C1_SCL",
+ "SFI_I3C1_SCL", "SFI_SPI_CS0"};
+static const char * const sfi_i2c1_sda_group[] = {"SFI_I2C1_SDA",
+ "SFI_I3C1_SDA", "SFI_SPI_CS1"};
+static const char * const sfi_gpio0_group[] = {"GPIO15", "SFI_SPI_SCK",
+ "SFI_GPIO0"};
+static const char * const sfi_gpio1_group[] = {"GPIO16", "SFI_SPI_MOSI",
+ "SFI_GPIO1"};
+static const char * const sfi_gpio2_group[] = {"GPIO17", "SFI_SPI_MISO",
+ "SFI_GPIO2"};
+static const char * const gpio18_group[] = {"SFI_GPIO3", "GPIO18"};
+static const char * const gpio19_group[] = {"SFI_GPIO4", "GPIO19"};
+static const char * const gpio20_group[] = {"SFI_GPIO5", "GPIO20"};
+static const char * const gpio21_group[] = {"SFI_GPIO6", "GPIO21"};
+static const char * const gpio22_group[] = {"SFI_GPIO7", "GPIO22"};
+static const char * const gpio23_group[] = {"SFI_GPIO8", "GPIO23",
+ "SFI_I3C0_PUR_EN_L"};
+static const char * const gpio24_group[] = {"SFI_GPIO9", "GPIO24",
+ "SFI_I3C1_PUR_EN_L"};
+static const char * const spi1_miso_group[] = {"SPI1_MISO", "GPIO25"};
+static const char * const spi1_cs0_group[] = {"SPI1_CS0", "GPIO26"};
+static const char * const spi1_cs1_group[] = {"SPI1_CS1", "GPIO27"};
+static const char * const spi1_mosi_group[] = {"SPI1_MOSI", "GPIO28"};
+static const char * const spi1_clk_group[] = {"SPI1_CLK", "GPIO29"};
+static const char * const gpio30_group[] = {"GPIO30", "USB_0C0_L"};
+static const char * const gpio31_group[] = {"GPIO31", "USB_0C1_L"};
+static const char * const gpio32_group[] = {"GPIO32", "USB_0C2_L"};
+static const char * const gpio33_group[] = {"GPIO33", "USB_0C3_L"};
+static const char * const gpio34_group[] = {"GPIO34", "USB_0C4_L"};
+static const char * const gpio35_group[] = {"GPIO35", "USB_0C5_L"};
+static const char * const gpio36_group[] = {"GPIO36", "USB_0C6_L"};
+static const char * const gpio37_group[] = {"GPIO37", "USB_0C7_L"};
+static const char * const gpio38_group[] = {"GPIO38", "USB_0C8_L"};
+static const char * const gpio39_group[] = {"GPIO39", "USB_0C9_L"};
+static const char * const gpio40_group[] = {"GPIO40", "USB_DRIVE_VBUS0"};
+static const char * const gpio41_group[] = {"GPIO41", "USB_DRIVE_VBUS4"};
+static const char * const gpio42_group[] = {"GPIO42", "USB_DRIVE_VBUS5"};
+static const char * const se_qspi_clk_group[] = {"SE_QSPI_CLK", "QSPI_CLK"};
+static const char * const se_qspi_cs_group[] = {"SE_QSPI_CS_L", "QSPI_CS_L"};
+static const char * const se_qspi_data0_group[] = {"SE_QSPI_DATA0",
+ "QSPI_DATA0"};
+static const char * const se_qspi_data1_group[] = {"SE_QSPI_DATA1",
+ "QSPI_DATA1"};
+static const char * const se_qspi_data2_group[] = {"SE_QSPI_DATA2",
+ "QSPI_DATA2"};
+static const char * const se_qspi_data3_group[] = {"SE_QSPI_DATA3",
+ "QSPI_DATA3"};
+static const struct sky1_pin_desc sky1_pinctrl_s5_pads[] = {
+ SKY_PINFUNCTION(PINCTRL_PIN(0, "GPIO1"), gpio1),
+ SKY_PINFUNCTION(PINCTRL_PIN(1, "GPIO2"), gpio2),
+ SKY_PINFUNCTION(PINCTRL_PIN(2, "GPIO3"), gpio3),
+ SKY_PINFUNCTION(PINCTRL_PIN(3, "GPIO4"), gpio4),
+ SKY_PINFUNCTION(PINCTRL_PIN(4, "GPIO5"), gpio5),
+ SKY_PINFUNCTION(PINCTRL_PIN(5, "GPIO6"), gpio6),
+ SKY_PINFUNCTION(PINCTRL_PIN(6, "GPIO7"), gpio7),
+ SKY_PINFUNCTION(PINCTRL_PIN(7, "GPIO8"), gpio8),
+ SKY_PINFUNCTION(PINCTRL_PIN(8, "GPIO9"), gpio9),
+ SKY_PINFUNCTION(PINCTRL_PIN(9, "GPIO10"), gpio10),
+ SKY_PINFUNCTION(PINCTRL_PIN(10, "GPIO11"), gpio11),
+ SKY_PINFUNCTION(PINCTRL_PIN(11, "GPIO12"), gpio12),
+ SKY_PINFUNCTION(PINCTRL_PIN(12, "GPIO13"), gpio13),
+ SKY_PINFUNCTION(PINCTRL_PIN(13, "GPIO14"), gpio14),
+ SKY_PINFUNCTION(PINCTRL_PIN(14, "RSMRST_L"), rsmrst),
+ SKY_PINFUNCTION(PINCTRL_PIN(15, "SRST_L"), srst),
+ SKY_PINFUNCTION(PINCTRL_PIN(16, "SLP_S3_L"), slp_s3),
+ SKY_PINFUNCTION(PINCTRL_PIN(17, "SLP_S5_L"), slp_s5),
+ SKY_PINFUNCTION(PINCTRL_PIN(18, "PWRGD"), pwrgd),
+ SKY_PINFUNCTION(PINCTRL_PIN(19, "PWROK"), pwrok),
+ SKY_PINFUNCTION(PINCTRL_PIN(20, "PWRBTN_L"), pwrbtn),
+ SKY_PINFUNCTION(PINCTRL_PIN(21, "VDD_DDRIO_GATE"), ddrio_gate),
+ SKY_PINFUNCTION(PINCTRL_PIN(22, "JTAG_GPIO_L"), jtag_gpio),
+ SKY_PINFUNCTION(PINCTRL_PIN(23, "JTAG_TCK"), jtag_tck),
+ SKY_PINFUNCTION(PINCTRL_PIN(24, "JTAG_TDI"), jtag_tdi),
+ SKY_PINFUNCTION(PINCTRL_PIN(25, "JTAG_TDO"), jtag_tdo),
+ SKY_PINFUNCTION(PINCTRL_PIN(26, "TMS"), tms),
+ SKY_PINFUNCTION(PINCTRL_PIN(27, "TRSL_L"), trsl),
+ SKY_PINFUNCTION(PINCTRL_PIN(28, "SFI_I2C0_SCL"), sfi_i2c0_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(29, "SFI_I2C0_SDA"), sfi_i2c0_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(30, "SFI_I2C1_SCL"), sfi_i2c1_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(31, "SFI_I2C1_SDA"), sfi_i2c1_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(32, "SFI_GPIO0"), sfi_gpio0),
+ SKY_PINFUNCTION(PINCTRL_PIN(33, "SFI_GPIO1"), sfi_gpio1),
+ SKY_PINFUNCTION(PINCTRL_PIN(34, "SFI_GPIO2"), sfi_gpio2),
+ SKY_PINFUNCTION(PINCTRL_PIN(35, "GPIO18"), gpio18),
+ SKY_PINFUNCTION(PINCTRL_PIN(36, "GPIO19"), gpio19),
+ SKY_PINFUNCTION(PINCTRL_PIN(37, "GPIO20"), gpio20),
+ SKY_PINFUNCTION(PINCTRL_PIN(38, "GPIO21"), gpio21),
+ SKY_PINFUNCTION(PINCTRL_PIN(39, "GPIO22"), gpio22),
+ SKY_PINFUNCTION(PINCTRL_PIN(40, "GPIO23"), gpio23),
+ SKY_PINFUNCTION(PINCTRL_PIN(41, "GPIO24"), gpio24),
+ SKY_PINFUNCTION(PINCTRL_PIN(42, "SPI1_MISO"), spi1_miso),
+ SKY_PINFUNCTION(PINCTRL_PIN(43, "SPI1_CS0"), spi1_cs0),
+ SKY_PINFUNCTION(PINCTRL_PIN(44, "SPI1_CS1"), spi1_cs1),
+ SKY_PINFUNCTION(PINCTRL_PIN(45, "SPI1_MOSI"), spi1_mosi),
+ SKY_PINFUNCTION(PINCTRL_PIN(46, "SPI1_CLK"), spi1_clk),
+ SKY_PINFUNCTION(PINCTRL_PIN(47, "GPIO30"), gpio30),
+ SKY_PINFUNCTION(PINCTRL_PIN(48, "GPIO31"), gpio31),
+ SKY_PINFUNCTION(PINCTRL_PIN(49, "GPIO32"), gpio32),
+ SKY_PINFUNCTION(PINCTRL_PIN(50, "GPIO33"), gpio33),
+ SKY_PINFUNCTION(PINCTRL_PIN(51, "GPIO34"), gpio34),
+ SKY_PINFUNCTION(PINCTRL_PIN(52, "GPIO35"), gpio35),
+ SKY_PINFUNCTION(PINCTRL_PIN(53, "GPIO36"), gpio36),
+ SKY_PINFUNCTION(PINCTRL_PIN(54, "GPIO37"), gpio37),
+ SKY_PINFUNCTION(PINCTRL_PIN(55, "GPIO38"), gpio38),
+ SKY_PINFUNCTION(PINCTRL_PIN(56, "GPIO39"), gpio39),
+ SKY_PINFUNCTION(PINCTRL_PIN(57, "GPIO40"), gpio40),
+ SKY_PINFUNCTION(PINCTRL_PIN(58, "GPIO41"), gpio41),
+ SKY_PINFUNCTION(PINCTRL_PIN(59, "GPIO42"), gpio42),
+ SKY_PINFUNCTION(PINCTRL_PIN(60, "SE_QSPI_CLK"), se_qspi_clk),
+ SKY_PINFUNCTION(PINCTRL_PIN(61, "SE_QSPI_CS_L"), se_qspi_cs),
+ SKY_PINFUNCTION(PINCTRL_PIN(62, "SE_QSPI_DATA0"), se_qspi_data0),
+ SKY_PINFUNCTION(PINCTRL_PIN(63, "SE_QSPI_DATA1"), se_qspi_data1),
+ SKY_PINFUNCTION(PINCTRL_PIN(64, "SE_QSPI_DATA2"), se_qspi_data2),
+ SKY_PINFUNCTION(PINCTRL_PIN(65, "SE_QSPI_DATA3"), se_qspi_data3),
+};
+
+/* Pad names for the s0 domain pinmux subsystem */
+static const char * const gpio43_group[] = {"GPIO43"};
+static const char * const gpio44_group[] = {"GPIO44"};
+static const char * const gpio45_group[] = {"GPIO45"};
+static const char * const gpio46_group[] = {"GPIO46"};
+static const char * const reset_in_group[] = { };
+static const char * const plt_reset_group[] = { };
+static const char * const thermtrip_group[] = { };
+static const char * const prochot_group[] = { };
+static const char * const pm_i2c0_clk_group[] = { };
+static const char * const pm_i2c0_data_group[] = { };
+static const char * const pm_i2c1_clk_group[] = { };
+static const char * const pm_i2c1_data_group[] = { };
+static const char * const pm_i2c2_clk_group[] = { };
+static const char * const pm_i2c2_data_group[] = { };
+static const char * const pm_i2c3_clk_group[] = { };
+static const char * const pm_i2c3_data_group[] = { };
+static const char * const strap0_group[] = { };
+static const char * const strap1_group[] = { };
+static const char * const dp2_digon_group[] = {"DP2_DIGON"};
+static const char * const dp2_blon_group[] = {"DP2_BLON"};
+static const char * const dp2_vary_bl_group[] = {"DP2_VARY_BL"};
+static const char * const i2c7_scl_group[] = {"I2C7_SCL"};
+static const char * const i2c7_sda_group[] = {"I2C7_SDA"};
+static const char * const uart6_csu_se_txd_group[] = { };
+static const char * const clk_req1_group[] = { };
+static const char * const clk_req3_group[] = { };
+static const char * const i2c5_scl_group[] = {"I2C5_SCL", "GPIO47"};
+static const char * const i2c5_sda_group[] = {"I2C5_SDA", "GPIO48"};
+static const char * const i2c6_scl_group[] = {"I2C6_SCL", "GPIO49"};
+static const char * const i2c6_sda_group[] = {"I2C6_SDA", "GPIO50"};
+static const char * const i2c0_scl_group[] = {"I2C0_SCL", "GPIO51"};
+static const char * const i2c0_sda_group[] = {"I2C0_SDA", "GPIO52"};
+static const char * const i2c1_scl_group[] = {"I2C1_SCL", "GPIO53"};
+static const char * const i2c1_sda_group[] = {"I2C1_SDA", "GPIO54"};
+static const char * const i2c2_scl_group[] = {"I2C2_SCL", "I3C0_SCL",
+ "GPIO55"};
+static const char * const i2c2_sda_group[] = {"I2C2_SDA", "I3C0_SDA",
+ "GPIO56"};
+static const char * const gpio57_group[] = {"GPIO57", "I3C0_PUR_EN_L"};
+static const char * const i2c3_scl_group[] = {"I2C3_SCL", "I3C1_SCL",
+ "GPIO58"};
+static const char * const i2c3_sda_group[] = {"I2C3_SDA", "I3C1_SDA",
+ "GPIO59"};
+static const char * const gpio60_group[] = {"GPIO60", "I3C1_PUR_EN_L"};
+static const char * const i2c4_scl_group[] = {"I2C4_SCL", "GPIO61"};
+static const char * const i2c4_sda_group[] = {"I2C4_SDA", "GPIO62"};
+static const char * const hda_bitclk_group[] = {"HDA_BITCLK", "I2S0_SCK",
+ "I2S9_RSCK_DBG"};
+static const char * const hda_rst_group[] = {"HDA_RST_L", "I2S0_DATA_IN",
+ "I2S9_DATA_IN_DBG"};
+static const char * const hda_sdin0_group[] = {"HDA_SDIN0", "I2S0_MCLK",
+ "I2S9_TSCK_DBG"};
+static const char * const hda_sdout0_group[] = {"HDA_SDOUT0", "I2S0_DATA_OUT",
+ "I2S9_TWS_DBG"};
+static const char * const hda_sync_group[] = {"HDA_SYNC", "I2S0_WS",
+ "I2S9_RWS_DBG"};
+static const char * const hda_sdin1_group[] = {"HDA_SDIN1", "GPIO63",
+ "I2S9_DATA_IN1_DBG"};
+static const char * const hda_sdout1_group[] = {"HDA_SDOUT1", "GPIO64",
+ "I2S9_DATA_OUT0_DBG"};
+static const char * const i2s1_mclk_group[] = {"I2S1_MCLK", "GPIO65"};
+static const char * const i2s1_sck_group[] = {"I2S1_SCK", "GPIO66"};
+static const char * const i2s1_ws_group[] = {"I2S1_WS", "GPIO67"};
+static const char * const i2s1_data_in_group[] = {"I2S1_DATA_IN", "GPIO68"};
+static const char * const i2s1_data_out_group[] = {"I2S1_DATA_OUT", "GPIO69"};
+static const char * const i2s2_mck_group[] = {"I2S2_MCLK", "GPIO70"};
+static const char * const i2s2_rsck_group[] = {"I2S2_RSCK", "GPIO71",
+ "I2S5_RSCK_DBG", "I2S6_RSCK_DBG"};
+static const char * const i2s2_rws_group[] = {"I2S2_RWS", "GPIO72",
+ "I2S5_RWS_DBG", "I2S6_RWS_DBG"};
+static const char * const i2s2_tsck_group[] = {"I2S2_TSCK", "GPIO73",
+ "I2S5_TSCK_DBG", "I2S6_TSCK_DBG"};
+static const char * const i2s2_tws_group[] = {"I2S2_TWS", "GPIO74",
+ "I2S5_TWS_DBG", "I2S6_TWS_DBG"};
+static const char * const i2s2_data_in0_group[] = {"I2S2_DATA_IN0", "GPIO75",
+ "I2S5_DATA_IN0_DBG", "I2S6_DATA_IN0_DBG"};
+static const char * const i2s2_data_in1_group[] = {"I2S2_DATA_IN1", "GPIO76",
+ "I2S5_DATA_IN1_DBG", "I2S6_DATA_IN1_DBG"};
+static const char * const i2s2_data_out0_group[] = {"I2S2_DATA_OUT0", "GPIO77",
+ "I2S5_DATA_OUT0_DBG", "I2S6_DATA_OUT0_DBG"};
+static const char * const i2s2_data_out1_group[] = {"I2S2_DATA_OUT1", "GPIO78",
+ "I2S5_DATA_OUT1_DBG", "I2S6_DATA_OUT1_DBG"};
+static const char * const i2s2_data_out2_group[] = {"I2S2_DATA_OUT2",
+ "GPIO79"};
+static const char * const i2s2_data_out3_group[] = {"I2S2_DATA_OUT3", "GPIO80",
+ "I2S9_DATA_OUT1_DBG"};
+static const char * const i2s3_mclk_group[] = {"I2S3_MCLK", "GPIO81"};
+static const char * const i2s3_rsck_group[] = {"I2S3_RSCK", "GPIO82",
+ "I2S7_RSCK_DBG", "I2S8_RSCK_DBG"};
+static const char * const i2s3_rws_group[] = {"I2S3_RWS", "GPIO83",
+ "I2S7_RWS_DBG", "I2S8_RWS_DBG"};
+static const char * const i2s3_tsck_group[] = {"I2S3_TSCK", "GPIO84",
+ "I2S7_TSCK_DBG", "I2S8_TSCK_DBG"};
+static const char * const i2s3_tws_group[] = {"I2S3_TWS", "GPIO85",
+ "I2S7_TWS_DBG", "I2S8_TWS_DBG"};
+static const char * const i2s3_data_in0_group[] = {"I2S3_DATA_IN0", "GPIO86",
+ "I2S7_DATA_IN0_DBG", "I2S8_DATA_IN0_DBG"};
+static const char * const i2s3_data_in1_group[] = {"I2S3_DATA_IN1", "GPIO87",
+ "I2S7_DATA_IN1_DBG", "I2S8_DATA_IN1_DBG"};
+static const char * const i2s3_data_out0_group[] = {"I2S3_DATA_OUT0", "GPIO88",
+ "I2S7_DATA_OUT0_DBG", "I2S8_DATA_OUT0_DBG"};
+static const char * const i2s3_data_out1_group[] = {"I2S3_DATA_OUT1", "GPIO89",
+ "I2S7_DATA_OUT1_DBG", "I2S8_DATA_OUT1_DBG"};
+static const char * const gpio90_group[] = {"GPIO90", "I2S4_MCLK_LB"};
+static const char * const gpio91_group[] = {"GPIO91", "I2S4_SCK_LB"};
+static const char * const gpio92_group[] = {"GPIO92", "I2S4_WS_LB"};
+static const char * const gpio93_group[] = {"GPIO93", "I2S4_DATA_IN_LB"};
+static const char * const gpio94_group[] = {"GPIO94", "I2S4_DATA_OUT_LB"};
+static const char * const uart0_txd_group[] = {"UART0_TXD", "PWM0", "GPIO95"};
+static const char * const uart0_rxd_group[] = {"UART0_RXD", "PWM1", "GPIO96"};
+static const char * const uart0_cts_group[] = {"UART0_CTS", "FAN_OUT2",
+ "GPIO97"};
+static const char * const uart0_rts_group[] = {"UART0_RTS", "FAN_TACH2",
+ "GPIO98"};
+static const char * const uart1_txd_group[] = {"UART1_TXD", "FAN_OUT0",
+ "GPIO99"};
+static const char * const uart1_rxd_group[] = {"UART1_RXD", "FAN_TACH0",
+ "GPIO100"};
+static const char * const uart1_cts_group[] = {"UART1_CTS", "FAN_OUT1",
+ "GPIO101"};
+static const char * const uart1_rts_group[] = {"UART1_RTS", "FAN_TACH1",
+ "GPIO102"};
+static const char * const uart2_txd_group[] = {"UART2_TXD", "GPIO103"};
+static const char * const uart2_rxd_group[] = {"UART2_RXD", "GPIO104"};
+static const char * const uart3_txd_group[] = {"UART3_TXD", "GPIO105"};
+static const char * const uart3_rxd_group[] = {"UART3_RXD", "GPIO106"};
+static const char * const uart3_cts_group[] = {"UART3_CTS", "GPIO107",
+ "TRIGIN0"};
+static const char * const uart3_rts_group[] = {"UART3_RTS", "GPIO108",
+ "TRIGIN1"};
+static const char * const uart4_csu_pm_txd_group[] = {"UART4_CSU_PM_TXD",
+ "GPIO109"};
+static const char * const uart4_csu_pm_rxd_group[] = {"UART4_CSU_PM_RXD",
+ "GPIO110"};
+static const char * const uart5_csu_se_txd_group[] = {"UART5_CSU_SE_TXD",
+ "GPIO111"};
+static const char * const uart5_csu_se_rxd_group[] = {"UART5_CSU_SE_RXD",
+ "GPIO112"};
+static const char * const uart6_csu_se_rxd_group[] = {"UART6_CSU_SE_RXD",
+ "GPIO113"};
+static const char * const clk_req0_group[] = {"CLK_REQ0_L", "GPIO114"};
+static const char * const clk_req2_group[] = {"CLK_REQ2_L", "GPIO115"};
+static const char * const clk_req4_group[] = {"CLK_REQ4_L", "GPIO116"};
+static const char * const csi0_mclk0_group[] = {"CSI0_MCLK0", "GPIO117"};
+static const char * const csi0_mclk1_group[] = {"CSI0_MCLK1", "GPIO118"};
+static const char * const csi1_mclk0_group[] = {"CSI1_MCLK0", "GPIO119"};
+static const char * const csi1_mclk1_group[] = {"CSI1_MCLK1", "GPIO120"};
+static const char * const gpio121_group[] = {"GPIO121", "GMAC0_REFCLK_25M"};
+static const char * const gpio122_group[] = {"GPIO122", "GMAC0_TX_CTL"};
+static const char * const gpio123_group[] = {"GPIO123", "GMAC0_TXD0"};
+static const char * const gpio124_group[] = {"GPIO124", "GMAC0_TXD1"};
+static const char * const gpio125_group[] = {"GPIO125", "GMAC0_TXD2"};
+static const char * const gpio126_group[] = {"GPIO126", "GMAC0_TXD3"};
+static const char * const gpio127_group[] = {"GPIO127", "GMAC0_TX_CLK"};
+static const char * const gpio128_group[] = {"GPIO128", "GMAC0_RX_CTL"};
+static const char * const gpio129_group[] = {"GPIO129", "GMAC0_RXD0"};
+static const char * const gpio130_group[] = {"GPIO130", "GMAC0_RXD1"};
+static const char * const gpio131_group[] = {"GPIO131", "GMAC0_RXD2"};
+static const char * const gpio132_group[] = {"GPIO132", "GMAC0_RXD3"};
+static const char * const gpio133_group[] = {"GPIO133", "GMAC0_RX_CLK"};
+static const char * const gpio134_group[] = {"GPIO134", "GMAC0_MDC"};
+static const char * const gpio135_group[] = {"GPIO135", "GMAC0_MDIO"};
+static const char * const gpio136_group[] = {"GPIO136", "GMAC1_REFCLK_25M"};
+static const char * const gpio137_group[] = {"GPIO137", "GMAC1_TX_CTL"};
+static const char * const gpio138_group[] = {"GPIO138", "GMAC1_TXD0",
+ "SPI2_MISO"};
+static const char * const gpio139_group[] = {"GPIO139", "GMAC1_TXD1",
+ "SPI2_CS0"};
+static const char * const gpio140_group[] = {"GPIO140", "GMAC1_TXD2",
+ "SPI2_CS1"};
+static const char * const gpio141_group[] = {"GPIO141", "GMAC1_TXD3",
+ "SPI2_MOSI"};
+static const char * const gpio142_group[] = {"GPIO142", "GMAC1_TX_CLK",
+ "SPI2_CLK"};
+static const char * const gpio143_group[] = {"GPIO143", "GMAC1_RX_CTL"};
+static const char * const gpio144_group[] = {"GPIO144", "GMAC1_RXD0"};
+static const char * const gpio145_group[] = {"GPIO145", "GMAC1_RXD1"};
+static const char * const gpio146_group[] = {"GPIO146", "GMAC1_RXD2"};
+static const char * const gpio147_group[] = {"GPIO147", "GMAC1_RXD3"};
+static const char * const gpio148_group[] = {"GPIO148", "GMAC1_RX_CLK"};
+static const char * const gpio149_group[] = {"GPIO149", "GMAC1_MDC"};
+static const char * const gpio150_group[] = {"GPIO150", "GMAC1_MDIO"};
+static const char * const gpio151_group[] = {"GPIO151", "PM_GPIO0"};
+static const char * const gpio152_group[] = {"GPIO152", "PM_GPIO1"};
+static const char * const gpio153_group[] = {"GPIO153", "PM_GPIO2"};
+static const struct sky1_pin_desc sky1_pinctrl_pads[] = {
+ SKY_PINFUNCTION(PINCTRL_PIN(0, "GPIO43"), gpio43),
+ SKY_PINFUNCTION(PINCTRL_PIN(1, "GPIO44"), gpio44),
+ SKY_PINFUNCTION(PINCTRL_PIN(2, "GPIO45"), gpio45),
+ SKY_PINFUNCTION(PINCTRL_PIN(3, "GPIO46"), gpio46),
+ SKY_PINFUNCTION(PINCTRL_PIN(4, "RESET_IN_L"), reset_in),
+ SKY_PINFUNCTION(PINCTRL_PIN(5, "PLT_RESET_L"), plt_reset),
+ SKY_PINFUNCTION(PINCTRL_PIN(6, "THERMTRIP_L"), thermtrip),
+ SKY_PINFUNCTION(PINCTRL_PIN(7, "PROCHOT_L"), prochot),
+ SKY_PINFUNCTION(PINCTRL_PIN(8, "PM_I2C0_CLK"), pm_i2c0_clk),
+ SKY_PINFUNCTION(PINCTRL_PIN(9, "PM_I2C0_DATA"), pm_i2c0_data),
+ SKY_PINFUNCTION(PINCTRL_PIN(10, "PM_I2C1_CLK"), pm_i2c1_clk),
+ SKY_PINFUNCTION(PINCTRL_PIN(11, "PM_I2C1_DATA"), pm_i2c1_data),
+ SKY_PINFUNCTION(PINCTRL_PIN(12, "PM_I2C2_CLK"), pm_i2c2_clk),
+ SKY_PINFUNCTION(PINCTRL_PIN(13, "PM_I2C2_DATA"), pm_i2c2_data),
+ SKY_PINFUNCTION(PINCTRL_PIN(14, "PM_I2C3_CLK"), pm_i2c3_clk),
+ SKY_PINFUNCTION(PINCTRL_PIN(15, "PM_I2C3_DATA"), pm_i2c3_data),
+ SKY_PINFUNCTION(PINCTRL_PIN(16, "STRAP0"), strap0),
+ SKY_PINFUNCTION(PINCTRL_PIN(17, "STRAP1"), strap1),
+ SKY_PINFUNCTION(PINCTRL_PIN(18, "DP2_DIGON"), dp2_digon),
+ SKY_PINFUNCTION(PINCTRL_PIN(19, "DP2_BLON"), dp2_blon),
+ SKY_PINFUNCTION(PINCTRL_PIN(20, "DP2_VARY_BL"), dp2_vary_bl),
+ SKY_PINFUNCTION(PINCTRL_PIN(21, "I2C7_SCL"), i2c7_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(22, "I2C7_SDA"), i2c7_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(23, "UART6_CSU_SE_TXD"), uart6_csu_se_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(24, "CLK_REQ1_L"), clk_req1),
+ SKY_PINFUNCTION(PINCTRL_PIN(25, "CLK_REQ3_L"), clk_req3),
+ SKY_PINFUNCTION(PINCTRL_PIN(26, "I2C5_SCL"), i2c5_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(27, "I2C5_SDA"), i2c5_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(28, "I2C6_SCL"), i2c6_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(29, "I2C6_SDA"), i2c6_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(30, "I2C0_CLK"), i2c0_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(31, "I2C0_SDA"), i2c0_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(32, "I2C1_CLK"), i2c1_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(33, "I2C1_SDA"), i2c1_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(34, "I2C2_SCL"), i2c2_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(35, "I2C2_SDA"), i2c2_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(36, "GPIO57"), gpio57),
+ SKY_PINFUNCTION(PINCTRL_PIN(37, "I2C3_SCL"), i2c3_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(38, "I2C3_SDA"), i2c3_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(39, "GPIO60"), gpio60),
+ SKY_PINFUNCTION(PINCTRL_PIN(40, "I2C4_SCL"), i2c4_scl),
+ SKY_PINFUNCTION(PINCTRL_PIN(41, "I2C4_SDA"), i2c4_sda),
+ SKY_PINFUNCTION(PINCTRL_PIN(42, "HDA_BITCLK"), hda_bitclk),
+ SKY_PINFUNCTION(PINCTRL_PIN(43, "HDA_RST_L"), hda_rst),
+ SKY_PINFUNCTION(PINCTRL_PIN(44, "HDA_SDIN0"), hda_sdin0),
+ SKY_PINFUNCTION(PINCTRL_PIN(45, "HDA_SDOUT0"), hda_sdout0),
+ SKY_PINFUNCTION(PINCTRL_PIN(46, "HDA_SYNC"), hda_sync),
+ SKY_PINFUNCTION(PINCTRL_PIN(47, "HDA_SDIN1"), hda_sdin1),
+ SKY_PINFUNCTION(PINCTRL_PIN(48, "HDA_SDOUT1"), hda_sdout1),
+ SKY_PINFUNCTION(PINCTRL_PIN(49, "I2S1_MCLK"), i2s1_mclk),
+ SKY_PINFUNCTION(PINCTRL_PIN(50, "I2S1_SCK"), i2s1_sck),
+ SKY_PINFUNCTION(PINCTRL_PIN(51, "I2S1_WS"), i2s1_ws),
+ SKY_PINFUNCTION(PINCTRL_PIN(52, "I2S1_DATA_IN"), i2s1_data_in),
+ SKY_PINFUNCTION(PINCTRL_PIN(53, "I2S1_DATA_OUT"), i2s1_data_out),
+ SKY_PINFUNCTION(PINCTRL_PIN(54, "I2S2_MCLK"), i2s2_mck),
+ SKY_PINFUNCTION(PINCTRL_PIN(55, "I2S2_RSCK"), i2s2_rsck),
+ SKY_PINFUNCTION(PINCTRL_PIN(56, "I2S2_RWS"), i2s2_rws),
+ SKY_PINFUNCTION(PINCTRL_PIN(57, "I2S2_TSCK"), i2s2_tsck),
+ SKY_PINFUNCTION(PINCTRL_PIN(58, "I2S2_TWS"), i2s2_tws),
+ SKY_PINFUNCTION(PINCTRL_PIN(59, "I2S2_DATA_IN0"), i2s2_data_in0),
+ SKY_PINFUNCTION(PINCTRL_PIN(60, "I2S2_DATA_IN1"), i2s2_data_in1),
+ SKY_PINFUNCTION(PINCTRL_PIN(61, "I2S2_DATA_OUT0"), i2s2_data_out0),
+ SKY_PINFUNCTION(PINCTRL_PIN(62, "I2S2_DATA_OUT1"), i2s2_data_out1),
+ SKY_PINFUNCTION(PINCTRL_PIN(63, "I2S2_DATA_OUT2"), i2s2_data_out2),
+ SKY_PINFUNCTION(PINCTRL_PIN(64, "I2S2_DATA_OUT3"), i2s2_data_out3),
+ SKY_PINFUNCTION(PINCTRL_PIN(65, "I2S3_MCLK"), i2s3_mclk),
+ SKY_PINFUNCTION(PINCTRL_PIN(66, "I2S3_RSCK"), i2s3_rsck),
+ SKY_PINFUNCTION(PINCTRL_PIN(67, "I2S3_RWS"), i2s3_rws),
+ SKY_PINFUNCTION(PINCTRL_PIN(68, "I2S3_TSCK"), i2s3_tsck),
+ SKY_PINFUNCTION(PINCTRL_PIN(69, "I2S3_TWS"), i2s3_tws),
+ SKY_PINFUNCTION(PINCTRL_PIN(70, "I2S3_DATA_IN0"), i2s3_data_in0),
+ SKY_PINFUNCTION(PINCTRL_PIN(71, "I2S3_DATA_IN1"), i2s3_data_in1),
+ SKY_PINFUNCTION(PINCTRL_PIN(72, "I2S3_DATA_OUT0"), i2s3_data_out0),
+ SKY_PINFUNCTION(PINCTRL_PIN(73, "I2S3_DATA_OUT1"), i2s3_data_out1),
+ SKY_PINFUNCTION(PINCTRL_PIN(74, "GPIO90"), gpio90),
+ SKY_PINFUNCTION(PINCTRL_PIN(75, "GPIO91"), gpio91),
+ SKY_PINFUNCTION(PINCTRL_PIN(76, "GPIO92"), gpio92),
+ SKY_PINFUNCTION(PINCTRL_PIN(77, "GPIO93"), gpio93),
+ SKY_PINFUNCTION(PINCTRL_PIN(78, "GPIO94"), gpio94),
+ SKY_PINFUNCTION(PINCTRL_PIN(79, "UART0_TXD"), uart0_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(80, "UART0_RXD"), uart0_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(81, "UART0_CTS"), uart0_cts),
+ SKY_PINFUNCTION(PINCTRL_PIN(82, "UART0_RTS"), uart0_rts),
+ SKY_PINFUNCTION(PINCTRL_PIN(83, "UART1_TXD"), uart1_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(84, "UART1_RXD"), uart1_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(85, "UART1_CTS"), uart1_cts),
+ SKY_PINFUNCTION(PINCTRL_PIN(86, "UART1_RTS"), uart1_rts),
+ SKY_PINFUNCTION(PINCTRL_PIN(87, "UART2_TXD"), uart2_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(88, "UART2_RXD"), uart2_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(89, "UART3_TXD"), uart3_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(90, "UART3_RXD"), uart3_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(91, "UART3_CTS"), uart3_cts),
+ SKY_PINFUNCTION(PINCTRL_PIN(92, "UART3_RTS"), uart3_rts),
+ SKY_PINFUNCTION(PINCTRL_PIN(93, "UART4_CSU_PM_TXD"), uart4_csu_pm_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(94, "UART4_CSU_PM_RXD"), uart4_csu_pm_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(95, "UART5_CSU_SE_TXD"), uart5_csu_se_txd),
+ SKY_PINFUNCTION(PINCTRL_PIN(96, "UART5_CSU_SE_RXD"), uart5_csu_se_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(97, "UART6_CSU_SE_RXD"), uart6_csu_se_rxd),
+ SKY_PINFUNCTION(PINCTRL_PIN(98, "CLK_REQ0_L"), clk_req0),
+ SKY_PINFUNCTION(PINCTRL_PIN(99, "CLK_REQ2_L"), clk_req2),
+ SKY_PINFUNCTION(PINCTRL_PIN(100, "CLK_REQ4_L"), clk_req4),
+ SKY_PINFUNCTION(PINCTRL_PIN(101, "CSI0_MCLK0"), csi0_mclk0),
+ SKY_PINFUNCTION(PINCTRL_PIN(102, "CSI0_MCLK1"), csi0_mclk1),
+ SKY_PINFUNCTION(PINCTRL_PIN(103, "CSI1_MCLK0"), csi1_mclk0),
+ SKY_PINFUNCTION(PINCTRL_PIN(104, "CSI1_MCLK1"), csi1_mclk1),
+ SKY_PINFUNCTION(PINCTRL_PIN(105, "GPIO121"), gpio121),
+ SKY_PINFUNCTION(PINCTRL_PIN(106, "GPIO122"), gpio122),
+ SKY_PINFUNCTION(PINCTRL_PIN(107, "GPIO123"), gpio123),
+ SKY_PINFUNCTION(PINCTRL_PIN(108, "GPIO124"), gpio124),
+ SKY_PINFUNCTION(PINCTRL_PIN(109, "GPIO125"), gpio125),
+ SKY_PINFUNCTION(PINCTRL_PIN(110, "GPIO126"), gpio126),
+ SKY_PINFUNCTION(PINCTRL_PIN(111, "GPIO127"), gpio127),
+ SKY_PINFUNCTION(PINCTRL_PIN(112, "GPIO128"), gpio128),
+ SKY_PINFUNCTION(PINCTRL_PIN(113, "GPIO129"), gpio129),
+ SKY_PINFUNCTION(PINCTRL_PIN(114, "GPIO130"), gpio130),
+ SKY_PINFUNCTION(PINCTRL_PIN(115, "GPIO131"), gpio131),
+ SKY_PINFUNCTION(PINCTRL_PIN(116, "GPIO132"), gpio132),
+ SKY_PINFUNCTION(PINCTRL_PIN(117, "GPIO133"), gpio133),
+ SKY_PINFUNCTION(PINCTRL_PIN(118, "GPIO134"), gpio134),
+ SKY_PINFUNCTION(PINCTRL_PIN(119, "GPIO135"), gpio135),
+ SKY_PINFUNCTION(PINCTRL_PIN(120, "GPIO136"), gpio136),
+ SKY_PINFUNCTION(PINCTRL_PIN(121, "GPIO137"), gpio137),
+ SKY_PINFUNCTION(PINCTRL_PIN(122, "GPIO138"), gpio138),
+ SKY_PINFUNCTION(PINCTRL_PIN(123, "GPIO139"), gpio139),
+ SKY_PINFUNCTION(PINCTRL_PIN(124, "GPIO140"), gpio140),
+ SKY_PINFUNCTION(PINCTRL_PIN(125, "GPIO141"), gpio141),
+ SKY_PINFUNCTION(PINCTRL_PIN(126, "GPIO142"), gpio142),
+ SKY_PINFUNCTION(PINCTRL_PIN(127, "GPIO143"), gpio143),
+ SKY_PINFUNCTION(PINCTRL_PIN(128, "GPIO144"), gpio144),
+ SKY_PINFUNCTION(PINCTRL_PIN(129, "GPIO145"), gpio145),
+ SKY_PINFUNCTION(PINCTRL_PIN(130, "GPIO146"), gpio146),
+ SKY_PINFUNCTION(PINCTRL_PIN(131, "GPIO147"), gpio147),
+ SKY_PINFUNCTION(PINCTRL_PIN(132, "GPIO148"), gpio148),
+ SKY_PINFUNCTION(PINCTRL_PIN(133, "GPIO149"), gpio149),
+ SKY_PINFUNCTION(PINCTRL_PIN(134, "GPIO150"), gpio150),
+ SKY_PINFUNCTION(PINCTRL_PIN(135, "GPIO151"), gpio151),
+ SKY_PINFUNCTION(PINCTRL_PIN(136, "GPIO152"), gpio152),
+ SKY_PINFUNCTION(PINCTRL_PIN(137, "GPIO153"), gpio153),
+};
+
+static const struct sky1_pinctrl_soc_info sky1_pinctrl_s5_info = {
+ .pins = sky1_pinctrl_s5_pads,
+ .npins = ARRAY_SIZE(sky1_pinctrl_s5_pads),
+};
+
+static const struct sky1_pinctrl_soc_info sky1_pinctrl_info = {
+ .pins = sky1_pinctrl_pads,
+ .npins = ARRAY_SIZE(sky1_pinctrl_pads),
+};
+
+static const struct of_device_id sky1_pinctrl_of_match[] = {
+ { .compatible = "cix,sky1-iomuxc-s5", .data = &sky1_pinctrl_s5_info, },
+ { .compatible = "cix,sky1-iomuxc", .data = &sky1_pinctrl_info, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sky1_pinctrl_of_match);
+
+static int __maybe_unused sky1_pinctrl_suspend(struct device *dev)
+{
+ struct sky1_pinctrl *spctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(spctl->pctl);
+}
+
+static int __maybe_unused sky1_pinctrl_resume(struct device *dev)
+{
+ struct sky1_pinctrl *spctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(spctl->pctl);
+}
+
+const struct dev_pm_ops sky1_pinctrl_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(sky1_pinctrl_suspend,
+ sky1_pinctrl_resume)
+};
+EXPORT_SYMBOL_GPL(sky1_pinctrl_pm_ops);
+
+static int sky1_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct sky1_pinctrl_soc_info *pinctrl_info;
+
+ pinctrl_info = device_get_match_data(&pdev->dev);
+ if (!pinctrl_info)
+ return -ENODEV;
+
+ return sky1_base_pinctrl_probe(pdev, pinctrl_info);
+}
+
+static struct platform_driver sky1_pinctrl_driver = {
+ .driver = {
+ .name = "sky1-pinctrl",
+ .of_match_table = sky1_pinctrl_of_match,
+ .pm = &sky1_pinctrl_pm_ops,
+ },
+ .probe = sky1_pinctrl_probe,
+};
+
+static int __init sky1_pinctrl_init(void)
+{
+ return platform_driver_register(&sky1_pinctrl_driver);
+}
+arch_initcall(sky1_pinctrl_init);
+
+MODULE_AUTHOR("Jerry Zhu <Jerry.Zhu@cixtech.com>");
+MODULE_DESCRIPTION("Cix Sky1 pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/cix/pinctrl-sky1.h b/drivers/pinctrl/cix/pinctrl-sky1.h
new file mode 100644
index 000000000000..a8b099852965
--- /dev/null
+++ b/drivers/pinctrl/cix/pinctrl-sky1.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Author: Jerry Zhu <Jerry.Zhu@cixtech.com>
+ */
+
+#ifndef __DRIVERS_PINCTRL_SKY1_H
+#define __DRIVERS_PINCTRL_SKY1_H
+
+struct sky1_pinctrl_group {
+ const char *name;
+ unsigned long config;
+ unsigned int pin;
+};
+
+struct sky1_pin_desc {
+ const struct pinctrl_pin_desc pin;
+ const char * const *func_group;
+ unsigned int nfunc;
+};
+
+struct sky1_pinctrl_soc_info {
+ const struct sky1_pin_desc *pins;
+ unsigned int npins;
+};
+
+#define SKY_PINFUNCTION(_pin, _func) \
+((struct sky1_pin_desc) { \
+ .pin = _pin, \
+ .func_group = _func##_group, \
+ .nfunc = ARRAY_SIZE(_func##_group), \
+ })
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct sky1_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ const struct sky1_pinctrl_soc_info *info;
+ struct sky1_pinctrl_group *groups;
+ const char **grp_names;
+};
+
+int sky1_base_pinctrl_probe(struct platform_device *pdev,
+ const struct sky1_pinctrl_soc_info *info);
+
+#endif /* __DRIVERS_PINCTRL_SKY1_H */
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] arm64: dts: cix: Add pinctrl nodes for sky1
2025-10-14 1:57 [PATCH v3 0/3] Add pinctrl support for Sky1 Gary Yang
2025-10-14 1:57 ` [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Gary Yang
2025-10-14 1:57 ` [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1 Gary Yang
@ 2025-10-14 1:57 ` Gary Yang
2 siblings, 0 replies; 11+ messages in thread
From: Gary Yang @ 2025-10-14 1:57 UTC (permalink / raw)
To: linus.walleij, robh, krzk+dt, conor+dt
Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
cix-kernel-upstream, Gary Yang
Add the pin-controller nodes for Sky1 platform.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 32 ++
arch/arm64/boot/dts/cix/sky1-pinfunc.h | 417 ++++++++++++++++++++++
arch/arm64/boot/dts/cix/sky1.dtsi | 10 +
3 files changed, 459 insertions(+)
create mode 100644 arch/arm64/boot/dts/cix/sky1-pinfunc.h
diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
index d74964d53c3b..a35a15471a1d 100644
--- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "sky1.dtsi"
+#include "sky1-pinfunc.h"
+
/ {
model = "Radxa Orion O6";
compatible = "radxa,orion-o6", "cix,sky1";
@@ -34,6 +36,36 @@ linux,cma {
};
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hog-pins {
+ pins {
+ pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>,
+ <CIX_PAD_GPIO145_FUNC_GPIO145>,
+ <CIX_PAD_GPIO146_FUNC_GPIO146>,
+ <CIX_PAD_GPIO147_FUNC_GPIO147>;
+ bias-pull-down;
+ drive-strength = <DS_LEVEL4>;
+ };
+ };
+};
+
+&iomuxc_s5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_s5>;
+
+ pinctrl_hog_s5: hog-s5-pins {
+ pins {
+ pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>;
+ bias-pull-up;
+ drive-strength = <DS_LEVEL4>;
+
+ };
+ };
+};
+
&uart2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/cix/sky1-pinfunc.h b/arch/arm64/boot/dts/cix/sky1-pinfunc.h
new file mode 100644
index 000000000000..bb2815903cb8
--- /dev/null
+++ b/arch/arm64/boot/dts/cix/sky1-pinfunc.h
@@ -0,0 +1,417 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2024-2025 Cix Technology Group Co., Ltd.
+ */
+
+#ifndef __CIX_SKY1_H
+#define __CIX_SKY1_H
+
+/* s5 pads */
+#define CIX_PAD_GPIO001_FUNC_GPIO001 (0 << 8 | 0x0)
+#define CIX_PAD_GPIO002_FUNC_GPIO002 (1 << 8 | 0x0)
+#define CIX_PAD_GPIO003_FUNC_GPIO003 (2 << 8 | 0x0)
+#define CIX_PAD_GPIO004_FUNC_GPIO004 (3 << 8 | 0x0)
+#define CIX_PAD_GPIO005_FUNC_GPIO005 (4 << 8 | 0x0)
+#define CIX_PAD_GPIO006_FUNC_GPIO006 (5 << 8 | 0x0)
+#define CIX_PAD_GPIO007_FUNC_GPIO007 (6 << 8 | 0x0)
+#define CIX_PAD_GPIO008_FUNC_GPIO008 (7 << 8 | 0x0)
+#define CIX_PAD_GPIO009_FUNC_GPIO009 (8 << 8 | 0x0)
+#define CIX_PAD_GPIO010_FUNC_GPIO010 (9 << 8 | 0x0)
+#define CIX_PAD_GPIO011_FUNC_GPIO011 (10 << 8 | 0x0)
+#define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
+#define CIX_PAD_GPIO013_FUNC_GPIO013 (12 << 8 | 0x0)
+#define CIX_PAD_GPIO014_FUNC_GPIO014 (13 << 8 | 0x0)
+#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I2C0_SCL (28 << 8 | 0x0)
+#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I3C0_SCL (28 << 8 | 0x1)
+#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I2C0_SDA (29 << 8 | 0x0)
+#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I3C0_SDA (29 << 8 | 0x1)
+#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I2C1_SCL (30 << 8 | 0x0)
+#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I3C1_SCL (30 << 8 | 0x1)
+#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_SPI_CS0 (30 << 8 | 0x2)
+#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I2C1_SDA (31 << 8 | 0x0)
+#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I3C1_SDA (31 << 8 | 0x1)
+#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_SPI_CS1 (31 << 8 | 0x2)
+#define CIX_PAD_SFI_GPIO0_FUNC_GPIO015 (32 << 8 | 0x0)
+#define CIX_PAD_SFI_GPIO0_FUNC_SFI_SPI_SCK (32 << 8 | 0x1)
+#define CIX_PAD_SFI_GPIO0_FUNC_SFI_GPIO0 (32 << 8 | 0x2)
+#define CIX_PAD_SFI_GPIO1_FUNC_GPIO016 (33 << 8 | 0x0)
+#define CIX_PAD_SFI_GPIO1_FUNC_SFI_SPI_MOSI (33 << 8 | 0x1)
+#define CIX_PAD_SFI_GPIO1_FUNC_SFI_GPIO1 (33 << 8 | 0x2)
+#define CIX_PAD_SFI_GPIO2_FUNC_GPIO017 (34 << 8 | 0x0)
+#define CIX_PAD_SFI_GPIO2_FUNC_SFI_SPI_MISO (34 << 8 | 0x1)
+#define CIX_PAD_SFI_GPIO2_FUNC_SFI_GPIO2 (34 << 8 | 0x2)
+#define CIX_PAD_GPIO018_FUNC_SFI_GPIO3 (35 << 8 | 0x0)
+#define CIX_PAD_GPIO018_FUNC_GPIO018 (35 << 8 | 0x1)
+#define CIX_PAD_GPIO019_FUNC_SFI_GPIO4 (36 << 8 | 0x0)
+#define CIX_PAD_GPIO019_FUNC_GPIO019 (36 << 8 | 0x1)
+#define CIX_PAD_GPIO020_FUNC_SFI_GPIO5 (37 << 8 | 0x0)
+#define CIX_PAD_GPIO020_FUNC_GPIO020 (37 << 8 | 0x1)
+#define CIX_PAD_GPIO021_FUNC_SFI_GPIO6 (38 << 8 | 0x0)
+#define CIX_PAD_GPIO021_FUNC_GPIO021 (38 << 8 | 0x1)
+#define CIX_PAD_GPIO022_FUNC_SFI_GPIO7 (39 << 8 | 0x0)
+#define CIX_PAD_GPIO022_FUNC_GPIO022 (39 << 8 | 0x1)
+#define CIX_PAD_GPIO023_FUNC_SFI_GPIO8 (40 << 8 | 0x0)
+#define CIX_PAD_GPIO023_FUNC_GPIO023 (40 << 8 | 0x1)
+#define CIX_PAD_GPIO023_FUNC_SFI_I3C0_PUR_EN_L (40 << 8 | 0x2)
+#define CIX_PAD_GPIO024_FUNC_SFI_GPIO9 (41 << 8 | 0x0)
+#define CIX_PAD_GPIO024_FUNC_GPIO024 (41 << 8 | 0x1)
+#define CIX_PAD_GPIO024_FUNC_SFI_I3C1_PUR_EN_L (41 << 8 | 0x2)
+#define CIX_PAD_SPI1_MISO_FUNC_SPI1_MISO (42 << 8 | 0x0)
+#define CIX_PAD_SPI1_MISO_FUNC_GPIO025 (42 << 8 | 0x1)
+#define CIX_PAD_SPI1_CS0_FUNC_SPI1_CS0 (43 << 8 | 0x0)
+#define CIX_PAD_SPI1_CS0_FUNC_GPIO026 (43 << 8 | 0x1)
+#define CIX_PAD_SPI1_CS1_FUNC_SPI1_CS1 (44 << 8 | 0x0)
+#define CIX_PAD_SPI1_CS1_FUNC_GPIO027 (44 << 8 | 0x1)
+#define CIX_PAD_SPI1_MOSI_FUNC_SPI1_MOSI (45 << 8 | 0x0)
+#define CIX_PAD_SPI1_MOSI_FUNC_GPIO028 (45 << 8 | 0x1)
+#define CIX_PAD_SPI1_CLK_FUNC_SPI1_CLK (46 << 8 | 0x0)
+#define CIX_PAD_SPI1_CLK_FUNC_GPIO029 (46 << 8 | 0x1)
+#define CIX_PAD_GPIO030_FUNC_GPIO030 (47 << 8 | 0x0)
+#define CIX_PAD_GPIO030_FUNC_USB_OC0_L (47 << 8 | 0x1)
+#define CIX_PAD_GPIO031_FUNC_GPIO031 (48 << 8 | 0x0)
+#define CIX_PAD_GPIO031_FUNC_USB_OC1_L (48 << 8 | 0x1)
+#define CIX_PAD_GPIO032_FUNC_GPIO032 (49 << 8 | 0x0)
+#define CIX_PAD_GPIO032_FUNC_USB_OC2_L (49 << 8 | 0x1)
+#define CIX_PAD_GPIO033_FUNC_GPIO033 (50 << 8 | 0x0)
+#define CIX_PAD_GPIO033_FUNC_USB_OC3_L (50 << 8 | 0x1)
+#define CIX_PAD_GPIO034_FUNC_GPIO034 (51 << 8 | 0x0)
+#define CIX_PAD_GPIO034_FUNC_USB_OC4_L (51 << 8 | 0x1)
+#define CIX_PAD_GPIO035_FUNC_GPIO035 (52 << 8 | 0x0)
+#define CIX_PAD_GPIO035_FUNC_USB_OC5_L (52 << 8 | 0x1)
+#define CIX_PAD_GPIO036_FUNC_GPIO036 (53 << 8 | 0x0)
+#define CIX_PAD_GPIO036_FUNC_USB_OC6_L (53 << 8 | 0x1)
+#define CIX_PAD_GPIO037_FUNC_GPIO037 (54 << 8 | 0x0)
+#define CIX_PAD_GPIO037_FUNC_USB_OC7_L (54 << 8 | 0x1)
+#define CIX_PAD_GPIO038_FUNC_GPIO038 (55 << 8 | 0x0)
+#define CIX_PAD_GPIO038_FUNC_USB_OC8_L (55 << 8 | 0x1)
+#define CIX_PAD_GPIO039_FUNC_GPIO039 (56 << 8 | 0x0)
+#define CIX_PAD_GPIO039_FUNC_USB_OC9_L (56 << 8 | 0x1)
+#define CIX_PAD_GPIO040_FUNC_GPIO040 (57 << 8 | 0x0)
+#define CIX_PAD_GPIO040_FUNC_USB_DRIVE_VBUS0 (57 << 8 | 0x1)
+#define CIX_PAD_GPIO041_FUNC_GPIO041 (58 << 8 | 0x0)
+#define CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4 (58 << 8 | 0x1)
+#define CIX_PAD_GPIO042_FUNC_GPIO042 (59 << 8 | 0x0)
+#define CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5 (59 << 8 | 0x1)
+#define CIX_PAD_SE_QSPI_CLK_FUNC_SE_QSPI_CLK (60 << 8 | 0x0)
+#define CIX_PAD_SE_QSPI_CLK_FUNC_QSPI_CLK (60 << 8 | 0x1)
+#define CIX_PAD_SE_QSPI_CS_L_FUNC_SE_QSPI_CS_L (61 << 8 | 0x0)
+#define CIX_PAD_SE_QSPI_CS_L_FUNC_QSPI_CS_L (61 << 8 | 0x1)
+#define CIX_PAD_SE_QSPI_DATA0_FUNC_SE_QSPI_DATA0 (62 << 8 | 0x0)
+#define CIX_PAD_SE_QSPI_DATA0_FUNC_QSPI_DATA0 (62 << 8 | 0x1)
+#define CIX_PAD_SE_QSPI_DATA1_FUNC_SE_QSPI_DATA1 (63 << 8 | 0x0)
+#define CIX_PAD_SE_QSPI_DATA1_FUNC_QSPI_DATA1 (63 << 8 | 0x1)
+#define CIX_PAD_SE_QSPI_DATA2_FUNC_SE_QSPI_DATA2 (64 << 8 | 0x0)
+#define CIX_PAD_SE_QSPI_DATA2_FUNC_QSPI_DATA2 (64 << 8 | 0x1)
+#define CIX_PAD_SE_QSPI_DATA3_FUNC_SE_QSPI_DATA3 (65 << 8 | 0x0)
+#define CIX_PAD_SE_QSPI_DATA3_FUNC_QSPI_DATA3 (65 << 8 | 0x1)
+/* s0 pads */
+#define CIX_PAD_GPIO043_FUNC_GPIO043 (0 << 8 | 0x0)
+#define CIX_PAD_GPIO044_FUNC_GPIO044 (1 << 8 | 0x0)
+#define CIX_PAD_GPIO045_FUNC_GPIO045 (2 << 8 | 0x0)
+#define CIX_PAD_GPIO046_FUNC_GPIO046 (3 << 8 | 0x0)
+#define CIX_PAD_DP2_DIGON_FUNC_DP2_DIGON (18 << 8 | 0x0)
+#define CIX_PAD_DP2_BLON_FUNC_DP2_BLON (19 << 8 | 0x0)
+#define CIX_PAD_DP2_VARY_BL_FUNC_DP2_VARY_BL (20 << 8 | 0x0)
+#define CIX_PAD_I2C7_SCL_FUNC_I2C7_SCL (21 << 8 | 0x0)
+#define CIX_PAD_I2C7_SDA_FUNC_I2C7_SDA (22 << 8 | 0x0)
+#define CIX_PAD_I2C5_SCL_FUNC_I2C5_SCL (26 << 8 | 0x0)
+#define CIX_PAD_I2C5_SCL_FUNC_GPIO047 (26 << 8 | 0x1)
+#define CIX_PAD_I2C5_SDA_FUNC_I2C5_SDA (27 << 8 | 0x0)
+#define CIX_PAD_I2C5_SDA_FUNC_GPIO048 (27 << 8 | 0x1)
+#define CIX_PAD_I2C6_SCL_FUNC_I2C6_SCL (28 << 8 | 0x0)
+#define CIX_PAD_I2C6_SCL_FUNC_GPIO049 (28 << 8 | 0x1)
+#define CIX_PAD_I2C6_SDA_FUNC_I2C6_SDA (29 << 8 | 0x0)
+#define CIX_PAD_I2C6_SDA_FUNC_GPIO050 (29 << 8 | 0x1)
+#define CIX_PAD_I2C0_CLK_FUNC_I2C0_CLK (30 << 8 | 0x0)
+#define CIX_PAD_I2C0_CLK_FUNC_GPIO051 (30 << 8 | 0x1)
+#define CIX_PAD_I2C0_SDA_FUNC_I2C0_SDA (31 << 8 | 0x0)
+#define CIX_PAD_I2C0_SDA_FUNC_GPIO052 (31 << 8 | 0x1)
+#define CIX_PAD_I2C1_CLK_FUNC_I2C1_CLK (32 << 8 | 0x0)
+#define CIX_PAD_I2C1_CLK_FUNC_GPIO053 (32 << 8 | 0x1)
+#define CIX_PAD_I2C1_SDA_FUNC_I2C1_SDA (33 << 8 | 0x0)
+#define CIX_PAD_I2C1_SDA_FUNC_GPIO054 (33 << 8 | 0x1)
+#define CIX_PAD_I2C2_SCL_FUNC_I2C2_SCL (34 << 8 | 0x0)
+#define CIX_PAD_I2C2_SCL_FUNC_I3C0_SCL (34 << 8 | 0x1)
+#define CIX_PAD_I2C2_SCL_FUNC_GPIO055 (34 << 8 | 0x2)
+#define CIX_PAD_I2C2_SDA_FUNC_I2C2_SDA (35 << 8 | 0x0)
+#define CIX_PAD_I2C2_SDA_FUNC_I3C0_SDA (35 << 8 | 0x1)
+#define CIX_PAD_I2C2_SDA_FUNC_GPIO056 (35 << 8 | 0x2)
+#define CIX_PAD_GPIO057_FUNC_GPIO057 (36 << 8 | 0x0)
+#define CIX_PAD_GPIO057_FUNC_I3C0_PUR_EN_L (36 << 8 | 0x1)
+#define CIX_PAD_I2C3_CLK_FUNC_I2C3_CLK (37 << 8 | 0x0)
+#define CIX_PAD_I2C3_CLK_FUNC_I3C1_CLK (37 << 8 | 0x1)
+#define CIX_PAD_I2C3_CLK_FUNC_GPIO058 (37 << 8 | 0x2)
+#define CIX_PAD_I2C3_SDA_FUNC_I2C3_SDA (38 << 8 | 0x0)
+#define CIX_PAD_I2C3_SDA_FUNC_I3C1_SDA (38 << 8 | 0x1)
+#define CIX_PAD_I2C3_SDA_FUNC_GPIO059 (38 << 8 | 0x2)
+#define CIX_PAD_GPIO060_FUNC_GPIO060 (39 << 8 | 0x0)
+#define CIX_PAD_GPIO060_FUNC_I3C1_PUR_EN_L (39 << 8 | 0x1)
+#define CIX_PAD_I2C4_CLK_FUNC_I2C4_CLK (40 << 8 | 0x0)
+#define CIX_PAD_I2C4_CLK_FUNC_GPIO061 (40 << 8 | 0x1)
+#define CIX_PAD_I2C4_SDA_FUNC_I2C4_SDA (41 << 8 | 0x0)
+#define CIX_PAD_I2C4_SDA_FUNC_GPIO062 (41 << 8 | 0x1)
+#define CIX_PAD_HDA_BITCLK_FUNC_HDA_BITCLK (42 << 8 | 0x0)
+#define CIX_PAD_HDA_BITCLK_FUNC_I2S0_SCK (42 << 8 | 0x1)
+#define CIX_PAD_HDA_BITCLK_FUNC_I2S9_RSCK_DBG (42 << 8 | 0x2)
+#define CIX_PAD_HDA_RST_L_FUNC_HDA_RST_L (43 << 8 | 0x0)
+#define CIX_PAD_HDA_RST_L_FUNC_I2S0_DATA_IN (43 << 8 | 0x1)
+#define CIX_PAD_HDA_RST_L_FUNC_I2S9_DATA_IN0_DBG (43 << 8 | 0x2)
+#define CIX_PAD_HDA_SDIN0_FUNC_HDA_SDIN0 (44 << 8 | 0x0)
+#define CIX_PAD_HDA_SDIN0_FUNC_I2S0_MCLK (44 << 8 | 0x1)
+#define CIX_PAD_HDA_SDIN0_FUNC_I2S9_TSCK_DBG (44 << 8 | 0x2)
+#define CIX_PAD_HDA_SDOUT0_FUNC_HDA_SDOUT0 (45 << 8 | 0x0)
+#define CIX_PAD_HDA_SDOUT0_FUNC_I2S0_DATA_OUT (45 << 8 | 0x1)
+#define CIX_PAD_HDA_SDOUT0_FUNC_I2S9_TWS_DBG (45 << 8 | 0x2)
+#define CIX_PAD_HDA_SYNC_FUNC_HDA_SYNC (46 << 8 | 0x0)
+#define CIX_PAD_HDA_SYNC_FUNC_I2S0_WS (46 << 8 | 0x1)
+#define CIX_PAD_HDA_SYNC_FUNC_I2S9_RWS_DBG (46 << 8 | 0x2)
+#define CIX_PAD_HDA_SDIN1_FUNC_HDA_SDIN1 (47 << 8 | 0x0)
+#define CIX_PAD_HDA_SDIN1_FUNC_GPIO063 (47 << 8 | 0x1)
+#define CIX_PAD_HDA_SDIN1_FUNC_I2S9_DATA_IN1_DBG (47 << 8 | 0x2)
+#define CIX_PAD_HDA_SDOUT1_FUNC_HDA_SDOUT1 (48 << 8 | 0x0)
+#define CIX_PAD_HDA_SDOUT1_FUNC_GPIO064 (48 << 8 | 0x1)
+#define CIX_PAD_HDA_SDOUT1_FUNC_I2S9_DATA_OUT0_DBG (48 << 8 | 0x2)
+#define CIX_PAD_I2S1_MCLK_FUNC_I2S1_MCLK (49 << 8 | 0x0)
+#define CIX_PAD_I2S1_MCLK_FUNC_GPIO065 (49 << 8 | 0x1)
+#define CIX_PAD_I2S1_SCK_FUNC_I2S1_SCK (50 << 8 | 0x0)
+#define CIX_PAD_I2S1_SCK_FUNC_GPIO066 (50 << 8 | 0x1)
+#define CIX_PAD_I2S1_WS_FUNC_I2S1_WS (51 << 8 | 0x0)
+#define CIX_PAD_I2S1_WS_FUNC_GPIO067 (51 << 8 | 0x1)
+#define CIX_PAD_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (52 << 8 | 0x0)
+#define CIX_PAD_I2S1_DATA_IN_FUNC_GPIO068 (52 << 8 | 0x1)
+#define CIX_PAD_I2S1_DATA_OUT_FUNC_I2S1_DATA_OUT (53 << 8 | 0x0)
+#define CIX_PAD_I2S1_DATA_OUT_FUNC_GPIO069 (53 << 8 | 0x1)
+#define CIX_PAD_I2S2_MCLK_FUNC_I2S2_MCLK (54 << 8 | 0x0)
+#define CIX_PAD_I2S2_MCLK_FUNC_GPIO070 (54 << 8 | 0x1)
+#define CIX_PAD_I2S2_RSCK_FUNC_I2S2_RSCK (55 << 8 | 0x0)
+#define CIX_PAD_I2S2_RSCK_FUNC_GPIO071 (55 << 8 | 0x1)
+#define CIX_PAD_I2S2_RSCK_FUNC_I2S5_RSCK_DBG (55 << 8 | 0x2)
+#define CIX_PAD_I2S2_RSCK_FUNC_I2S6_RSCK_DBG (55 << 8 | 0x3)
+#define CIX_PAD_I2S2_RWS_FUNC_I2S2_RWS (56 << 8 | 0x0)
+#define CIX_PAD_I2S2_RWS_FUNC_GPIO072 (56 << 8 | 0x1)
+#define CIX_PAD_I2S2_RWS_FUNC_I2S5_RWS_DBG (56 << 8 | 0x2)
+#define CIX_PAD_I2S2_RWS_FUNC_I2S6_RWS_DBG (56 << 8 | 0x3)
+#define CIX_PAD_I2S2_TSCK_FUNC_I2S2_TSCK (57 << 8 | 0x0)
+#define CIX_PAD_I2S2_TSCK_FUNC_GPIO073 (57 << 8 | 0x1)
+#define CIX_PAD_I2S2_TSCK_FUNC_I2S5_TSCK_DBG (57 << 8 | 0x2)
+#define CIX_PAD_I2S2_TSCK_FUNC_I2S6_TSCK_DBG (57 << 8 | 0x3)
+#define CIX_PAD_I2S2_TWS_FUNC_I2S2_TWS (58 << 8 | 0x0)
+#define CIX_PAD_I2S2_TWS_FUNC_GPIO074 (58 << 8 | 0x1)
+#define CIX_PAD_I2S2_TWS_FUNC_I2S5_TWS_DBG (58 << 8 | 0x2)
+#define CIX_PAD_I2S2_TWS_FUNC_I2S6_TWS_DBG (58 << 8 | 0x3)
+#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S2_DATA_IN0 (59 << 8 | 0x0)
+#define CIX_PAD_I2S2_DATA_IN0_FUNC_GPIO075 (59 << 8 | 0x1)
+#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S5_DATA_IN0_DBG (59 << 8 | 0x2)
+#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S6_DATA_IN0_DBG (59 << 8 | 0x3)
+#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S2_DATA_IN1 (60 << 8 | 0x0)
+#define CIX_PAD_I2S2_DATA_IN1_FUNC_GPIO076 (60 << 8 | 0x1)
+#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S5_DATA_IN1_DBG (60 << 8 | 0x2)
+#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S6_DATA_IN1_DBG (60 << 8 | 0x3)
+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S2_DATA_OUT0 (61 << 8 | 0x0)
+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_GPIO077 (61 << 8 | 0x1)
+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S5_DATA_OUT0_DBG (61 << 8 | 0x2)
+#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S6_DATA_OUT0_DBG (61 << 8 | 0x3)
+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S2_DATA_OUT1 (62 << 8 | 0x0)
+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_GPIO078 (62 << 8 | 0x1)
+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S5_DATA_OUT1_DBG (62 << 8 | 0x2)
+#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S6_DATA_OUT1_DBG (62 << 8 | 0x3)
+#define CIX_PAD_I2S2_DATA_OUT2_FUNC_I2S2_DATA_OUT2 (63 << 8 | 0x0)
+#define CIX_PAD_I2S2_DATA_OUT2_FUNC_GPIO079 (63 << 8 | 0x1)
+#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S2_DATA_OUT3 (64 << 8 | 0x0)
+#define CIX_PAD_I2S2_DATA_OUT3_FUNC_GPIO080 (64 << 8 | 0x1)
+#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S9_DATA_OUT1_DBG (64 << 8 | 0x2)
+#define CIX_PAD_I2S3_MCLK_FUNC_I2S3_MCLK (65 << 8 | 0x0)
+#define CIX_PAD_I2S3_MCLK_FUNC_GPIO081 (65 << 8 | 0x1)
+#define CIX_PAD_I2S3_RSCK_FUNC_I2S3_RSCK (66 << 8 | 0x0)
+#define CIX_PAD_I2S3_RSCK_FUNC_GPIO082 (66 << 8 | 0x1)
+#define CIX_PAD_I2S3_RSCK_FUNC_I2S7_RSCK_DBG (66 << 8 | 0x2)
+#define CIX_PAD_I2S3_RSCK_FUNC_I2S8_RSCK_DBG (66 << 8 | 0x3)
+#define CIX_PAD_I2S3_RWS_FUNC_I2S3_RWS (67 << 8 | 0x0)
+#define CIX_PAD_I2S3_RWS_FUNC_GPIO083 (67 << 8 | 0x1)
+#define CIX_PAD_I2S3_RWS_FUNC_I2S7_RWS_DBG (67 << 8 | 0x2)
+#define CIX_PAD_I2S3_RWS_FUNC_I2S8_RWS_DBG (67 << 8 | 0x3)
+#define CIX_PAD_I2S3_TSCK_FUNC_I2S3_TSCK (68 << 8 | 0x0)
+#define CIX_PAD_I2S3_TSCK_FUNC_GPIO084 (68 << 8 | 0x1)
+#define CIX_PAD_I2S3_TSCK_FUNC_I2S7_TSCK_DBG (68 << 8 | 0x2)
+#define CIX_PAD_I2S3_TSCK_FUNC_I2S8_TSCK_DBG (68 << 8 | 0x3)
+#define CIX_PAD_I2S3_TWS_FUNC_I2S3_TWS (69 << 8 | 0x0)
+#define CIX_PAD_I2S3_TWS_FUNC_GPIO085 (69 << 8 | 0x1)
+#define CIX_PAD_I2S3_TWS_FUNC_I2S7_TWS_DBG (69 << 8 | 0x2)
+#define CIX_PAD_I2S3_TWS_FUNC_I2S8_TWS_DBG (69 << 8 | 0x3)
+#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S3_DATA_IN0 (70 << 8 | 0x0)
+#define CIX_PAD_I2S3_DATA_IN0_FUNC_GPIO086 (70 << 8 | 0x1)
+#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S7_DATA_IN0_DBG (70 << 8 | 0x2)
+#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S8_DATA_IN0_DBG (70 << 8 | 0x3)
+#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S3_DATA_IN1 (71 << 8 | 0x0)
+#define CIX_PAD_I2S3_DATA_IN1_FUNC_GPIO087 (71 << 8 | 0x1)
+#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S7_DATA_IN1_DBG (71 << 8 | 0x2)
+#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S8_DATA_IN1_DBG (71 << 8 | 0x3)
+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S3_DATA_OUT0 (72 << 8 | 0x0)
+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_GPIO088 (72 << 8 | 0x1)
+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S7_DATA_OUT0_DBG (72 << 8 | 0x2)
+#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S8_DATA_OUT0_DBG (72 << 8 | 0x3)
+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S3_DATA_OUT1 (73 << 8 | 0x0)
+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_GPIO089 (73 << 8 | 0x1)
+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S7_DATA_OUT1_DBG (73 << 8 | 0x2)
+#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S8_DATA_OUT1_DBG (73 << 8 | 0x3)
+#define CIX_PAD_GPIO090_FUNC_GPIO090 (74 << 8 | 0x0)
+#define CIX_PAD_GPIO090_FUNC_I2S4_MCLK_LB (74 << 8 | 0x1)
+#define CIX_PAD_GPIO091_FUNC_GPIO091 (75 << 8 | 0x0)
+#define CIX_PAD_GPIO091_FUNC_I2S4_SCK_LB (75 << 8 | 0x1)
+#define CIX_PAD_GPIO092_FUNC_GPIO092 (76 << 8 | 0x0)
+#define CIX_PAD_GPIO092_FUNC_I2S4_WS_LB (76 << 8 | 0x1)
+#define CIX_PAD_GPIO093_FUNC_GPIO093 (77 << 8 | 0x0)
+#define CIX_PAD_GPIO093_FUNC_I2S4_DATA_IN_LB (77 << 8 | 0x1)
+#define CIX_PAD_GPIO094_FUNC_GPIO094 (78 << 8 | 0x0)
+#define CIX_PAD_GPIO094_FUNC_I2S4_DATA_OUT_LB (78 << 8 | 0x1)
+#define CIX_PAD_UART0_TXD_FUNC_UART0_TXD (79 << 8 | 0x0)
+#define CIX_PAD_UART0_TXD_FUNC_PWM0 (79 << 8 | 0x1)
+#define CIX_PAD_UART0_TXD_FUNC_GPIO095 (79 << 8 | 0x2)
+#define CIX_PAD_UART0_RXD_FUNC_UART0_RXD (80 << 8 | 0x0)
+#define CIX_PAD_UART0_RXD_FUNC_PWM1 (80 << 8 | 0x1)
+#define CIX_PAD_UART0_RXD_FUNC_GPIO096 (80 << 8 | 0x2)
+#define CIX_PAD_UART0_CTS_FUNC_UART0_CTS (81 << 8 | 0x0)
+#define CIX_PAD_UART0_CTS_FUNC_FAN_OUT2 (81 << 8 | 0x1)
+#define CIX_PAD_UART0_CTS_FUNC_GPIO097 (81 << 8 | 0x2)
+#define CIX_PAD_UART0_RTS_FUNC_UART0_RTS (82 << 8 | 0x0)
+#define CIX_PAD_UART0_RTS_FUNC_FAN_TACH2 (82 << 8 | 0x1)
+#define CIX_PAD_UART0_RTS_FUNC_GPIO098 (82 << 8 | 0x2)
+#define CIX_PAD_UART1_TXD_FUNC_UART1_TXD (83 << 8 | 0x0)
+#define CIX_PAD_UART1_TXD_FUNC_FAN_OUT0 (83 << 8 | 0x1)
+#define CIX_PAD_UART1_TXD_FUNC_GPIO099 (83 << 8 | 0x2)
+#define CIX_PAD_UART1_RXD_FUNC_UART1_RXD (84 << 8 | 0x0)
+#define CIX_PAD_UART1_RXD_FUNC_FAN_TACH0 (84 << 8 | 0x1)
+#define CIX_PAD_UART1_RXD_FUNC_GPIO100 (84 << 8 | 0x2)
+#define CIX_PAD_UART1_CTS_FUNC_UART1_CTS (85 << 8 | 0x0)
+#define CIX_PAD_UART1_CTS_FUNC_FAN_OUT1 (85 << 8 | 0x1)
+#define CIX_PAD_UART1_CTS_FUNC_GPIO101 (85 << 8 | 0x2)
+#define CIX_PAD_UART1_RTS_FUNC_UART1_RTS (86 << 8 | 0x0)
+#define CIX_PAD_UART1_RTS_FUNC_FAN_TACH1 (86 << 8 | 0x1)
+#define CIX_PAD_UART1_RTS_FUNC_GPIO102 (86 << 8 | 0x2)
+#define CIX_PAD_UART2_TXD_FUNC_UART2_TXD (87 << 8 | 0x0)
+#define CIX_PAD_UART2_TXD_FUNC_GPIO103 (87 << 8 | 0x1)
+#define CIX_PAD_UART2_RXD_FUNC_UART2_RXD (88 << 8 | 0x0)
+#define CIX_PAD_UART2_RXD_FUNC_GPIO104 (88 << 8 | 0x1)
+#define CIX_PAD_UART3_TXD_FUNC_UART3_TXD (89 << 8 | 0x0)
+#define CIX_PAD_UART3_TXD_FUNC_GPIO105 (89 << 8 | 0x1)
+#define CIX_PAD_UART3_RXD_FUNC_UART3_RXD (90 << 8 | 0x0)
+#define CIX_PAD_UART3_RXD_FUNC_GPIO106 (90 << 8 | 0x1)
+#define CIX_PAD_UART3_CTS_FUNC_UART3_CTS (91 << 8 | 0x0)
+#define CIX_PAD_UART3_CTS_FUNC_GPIO107 (91 << 8 | 0x1)
+#define CIX_PAD_UART3_CTS_FUNC_TRIGIN0 (91 << 8 | 0x2)
+#define CIX_PAD_UART3_RTS_FUNC_UART3_RTS (92 << 8 | 0x0)
+#define CIX_PAD_UART3_RTS_FUNC_GPIO108 (92 << 8 | 0x1)
+#define CIX_PAD_UART3_RTS_FUNC_TRIGIN1 (92 << 8 | 0x2)
+#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_UART4_CSU_PM_TXD (93 << 8 | 0x0)
+#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_GPIO109 (93 << 8 | 0x1)
+#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_UART4_CSU_PM_RXD (94 << 8 | 0x0)
+#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_GPIO110 (94 << 8 | 0x1)
+#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_UART5_CSU_SE_TXD (95 << 8 | 0x0)
+#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_GPIO111 (95 << 8 | 0x1)
+#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_UART5_CSU_SE_RXD (96 << 8 | 0x0)
+#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_GPIO112 (96 << 8 | 0x1)
+#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_UART6_CSU_SE_RXD (97 << 8 | 0x0)
+#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_GPIO113 (97 << 8 | 0x1)
+#define CIX_PAD_CLK_REQ0_L_FUNC_CLK_REQ0_L (98 << 8 | 0x0)
+#define CIX_PAD_CLK_REQ0_L_FUNC_GPIO114 (98 << 8 | 0x1)
+#define CIX_PAD_CLK_REQ2_L_FUNC_CLK_REQ2_L (99 << 8 | 0x0)
+#define CIX_PAD_CLK_REQ2_L_FUNC_GPIO115 (99 << 8 | 0x1)
+#define CIX_PAD_CLK_REQ4_L_FUNC_CLK_REQ4_L (100 << 8 | 0x0)
+#define CIX_PAD_CLK_REQ4_L_FUNC_GPIO116 (100 << 8 | 0x1)
+#define CIX_PAD_CSI0_MCLK0_FUNC_CSI0_MCLK0 (101 << 8 | 0x0)
+#define CIX_PAD_CSI0_MCLK0_FUNC_GPIO117 (101 << 8 | 0x1)
+#define CIX_PAD_CSI0_MCLK1_FUNC_CSI0_MCLK1 (102 << 8 | 0x0)
+#define CIX_PAD_CSI0_MCLK1_FUNC_GPIO118 (102 << 8 | 0x1)
+#define CIX_PAD_CSI1_MCLK0_FUNC_CSI1_MCLK0 (103 << 8 | 0x0)
+#define CIX_PAD_CSI1_MCLK0_FUNC_GPIO119 (103 << 8 | 0x1)
+#define CIX_PAD_CSI1_MCLK1_FUNC_CSI1_MCLK1 (104 << 8 | 0x0)
+#define CIX_PAD_CSI1_MCLK1_FUNC_GPIO120 (104 << 8 | 0x1)
+#define CIX_PAD_GPIO121_FUNC_GPIO121 (105 << 8 | 0x0)
+#define CIX_PAD_GPIO121_FUNC_GMAC0_REFCLK_25M (105 << 8 | 0x1)
+#define CIX_PAD_GPIO122_FUNC_GPIO122 (106 << 8 | 0x0)
+#define CIX_PAD_GPIO122_FUNC_GMAC0_TX_CTL (106 << 8 | 0x1)
+#define CIX_PAD_GPIO123_FUNC_GPIO123 (107 << 8 | 0x0)
+#define CIX_PAD_GPIO123_FUNC_GMAC0_TXD0 (107 << 8 | 0x1)
+#define CIX_PAD_GPIO124_FUNC_GPIO124 (108 << 8 | 0x0)
+#define CIX_PAD_GPIO124_FUNC_GMAC0_TXD1 (108 << 8 | 0x1)
+#define CIX_PAD_GPIO125_FUNC_GPIO125 (109 << 8 | 0x0)
+#define CIX_PAD_GPIO125_FUNC_GMAC0_TXD2 (109 << 8 | 0x1)
+#define CIX_PAD_GPIO126_FUNC_GPIO126 (110 << 8 | 0x0)
+#define CIX_PAD_GPIO126_FUNC_GMAC0_TXD3 (110 << 8 | 0x1)
+#define CIX_PAD_GPIO127_FUNC_GPIO127 (111 << 8 | 0x0)
+#define CIX_PAD_GPIO127_FUNC_GMAC0_TX_CLK (111 << 8 | 0x1)
+#define CIX_PAD_GPIO128_FUNC_GPIO128 (112 << 8 | 0x0)
+#define CIX_PAD_GPIO128_FUNC_GMAC0_RX_CTL (112 << 8 | 0x1)
+#define CIX_PAD_GPIO129_FUNC_GPIO129 (113 << 8 | 0x0)
+#define CIX_PAD_GPIO129_FUNC_GMAC0_RXD0 (113 << 8 | 0x1)
+#define CIX_PAD_GPIO130_FUNC_GPIO130 (114 << 8 | 0x0)
+#define CIX_PAD_GPIO130_FUNC_GMAC0_RXD1 (114 << 8 | 0x1)
+#define CIX_PAD_GPIO131_FUNC_GPIO131 (115 << 8 | 0x0)
+#define CIX_PAD_GPIO131_FUNC_GMAC0_RXD2 (115 << 8 | 0x1)
+#define CIX_PAD_GPIO132_FUNC_GPIO132 (116 << 8 | 0x0)
+#define CIX_PAD_GPIO132_FUNC_GMAC0_RXD3 (116 << 8 | 0x1)
+#define CIX_PAD_GPIO133_FUNC_GPIO133 (117 << 8 | 0x0)
+#define CIX_PAD_GPIO133_FUNC_GMAC0_RX_CLK (117 << 8 | 0x1)
+#define CIX_PAD_GPIO134_FUNC_GPIO134 (118 << 8 | 0x0)
+#define CIX_PAD_GPIO134_FUNC_GMAC0_MDC (118 << 8 | 0x1)
+#define CIX_PAD_GPIO135_FUNC_GPIO135 (119 << 8 | 0x0)
+#define CIX_PAD_GPIO135_FUNC_GMAC0_MDIO (119 << 8 | 0x1)
+#define CIX_PAD_GPIO136_FUNC_GPIO136 (120 << 8 | 0x0)
+#define CIX_PAD_GPIO136_FUNC_GMAC1_REFCLK_25M (120 << 8 | 0x1)
+#define CIX_PAD_GPIO137_FUNC_GPIO137 (121 << 8 | 0x0)
+#define CIX_PAD_GPIO137_FUNC_GMAC1_TX_CTL (121 << 8 | 0x1)
+#define CIX_PAD_GPIO138_FUNC_GPIO138 (122 << 8 | 0x0)
+#define CIX_PAD_GPIO138_FUNC_GMAC1_TXD0 (122 << 8 | 0x1)
+#define CIX_PAD_GPIO138_FUNC_SPI2_MISO (122 << 8 | 0x2)
+#define CIX_PAD_GPIO139_FUNC_GPIO139 (123 << 8 | 0x0)
+#define CIX_PAD_GPIO139_FUNC_GMAC1_TXD1 (123 << 8 | 0x1)
+#define CIX_PAD_GPIO139_FUNC_SPI2_CS0 (123 << 8 | 0x2)
+#define CIX_PAD_GPIO140_FUNC_GPIO140 (124 << 8 | 0x0)
+#define CIX_PAD_GPIO140_FUNC_GMAC1_TXD2 (124 << 8 | 0x1)
+#define CIX_PAD_GPIO140_FUNC_SPI2_CS1 (124 << 8 | 0x2)
+#define CIX_PAD_GPIO141_FUNC_GPIO141 (125 << 8 | 0x0)
+#define CIX_PAD_GPIO141_FUNC_GMAC1_TXD3 (125 << 8 | 0x1)
+#define CIX_PAD_GPIO141_FUNC_SPI2_MOSI (125 << 8 | 0x2)
+#define CIX_PAD_GPIO142_FUNC_GPIO142 (126 << 8 | 0x0)
+#define CIX_PAD_GPIO142_FUNC_GMAC1_TX_CLK (126 << 8 | 0x1)
+#define CIX_PAD_GPIO142_FUNC_SPI2_CLK (126 << 8 | 0x2)
+#define CIX_PAD_GPIO143_FUNC_GPIO143 (127 << 8 | 0x0)
+#define CIX_PAD_GPIO143_FUNC_GMAC1_RX_CTL (127 << 8 | 0x1)
+#define CIX_PAD_GPIO144_FUNC_GPIO144 (128 << 8 | 0x0)
+#define CIX_PAD_GPIO144_FUNC_GMAC1_RXD0 (128 << 8 | 0x1)
+#define CIX_PAD_GPIO145_FUNC_GPIO145 (129 << 8 | 0x0)
+#define CIX_PAD_GPIO145_FUNC_GMAC1_RXD1 (129 << 8 | 0x1)
+#define CIX_PAD_GPIO146_FUNC_GPIO146 (130 << 8 | 0x0)
+#define CIX_PAD_GPIO146_FUNC_GMAC1_RXD2 (130 << 8 | 0x1)
+#define CIX_PAD_GPIO147_FUNC_GPIO147 (131 << 8 | 0x0)
+#define CIX_PAD_GPIO147_FUNC_GMAC1_RXD3 (131 << 8 | 0x1)
+#define CIX_PAD_GPIO148_FUNC_GPIO148 (132 << 8 | 0x0)
+#define CIX_PAD_GPIO148_FUNC_GMAC1_RX_CLK (132 << 8 | 0x1)
+#define CIX_PAD_GPIO149_FUNC_GPIO149 (133 << 8 | 0x0)
+#define CIX_PAD_GPIO149_FUNC_GMAC1_MDC (133 << 8 | 0x1)
+#define CIX_PAD_GPIO150_FUNC_GPIO150 (134 << 8 | 0x0)
+#define CIX_PAD_GPIO150_FUNC_GMAC1_MDIO (134 << 8 | 0x1)
+#define CIX_PAD_GPIO151_FUNC_GPIO151 (135 << 8 | 0x0)
+#define CIX_PAD_GPIO151_FUNC_PM_GPIO0 (135 << 8 | 0x1)
+#define CIX_PAD_GPIO152_FUNC_GPIO152 (136 << 8 | 0x0)
+#define CIX_PAD_GPIO152_FUNC_PM_GPIO1 (136 << 8 | 0x1)
+#define CIX_PAD_GPIO153_FUNC_GPIO153 (137 << 8 | 0x0)
+#define CIX_PAD_GPIO153_FUNC_PM_GPIO2 (137 << 8 | 0x1)
+
+#define DS_LEVEL1 0x1
+#define DS_LEVEL2 0x2
+#define DS_LEVEL3 0x3
+#define DS_LEVEL4 0x4
+#define DS_LEVEL5 0x5
+#define DS_LEVEL6 0x6
+#define DS_LEVEL7 0x7
+#define DS_LEVEL8 0x8
+#define DS_LEVEL9 0x9
+#define DS_LEVEL10 0xa
+#define DS_LEVEL11 0xb
+#define DS_LEVEL12 0xc
+#define DS_LEVEL13 0xd
+#define DS_LEVEL14 0xe
+#define DS_LEVEL15 0xf
+
+#endif
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 7dfe7677e649..4c6f25fe797c 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -228,6 +228,11 @@ uart3: serial@40e0000 {
status = "disabled";
};
+ iomuxc: pinctrl@4170000 {
+ compatible = "cix,sky1-iomuxc";
+ reg = <0x0 0x04170000 0x0 0x1000>;
+ };
+
mbox_ap2se: mailbox@5060000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x05060000 0x0 0x10000>;
@@ -316,6 +321,11 @@ ppi_partition1: interrupt-partition-1 {
};
};
};
+
+ iomuxc_s5: pinctrl@16007000 {
+ compatible = "cix,sky1-iomuxc-s5";
+ reg = <0x0 0x16007000 0x0 0x1000>;
+ };
};
timer {
--
2.49.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl
2025-10-14 1:57 ` [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Gary Yang
@ 2025-10-14 10:44 ` Linus Walleij
2025-10-14 17:58 ` Conor Dooley
0 siblings, 1 reply; 11+ messages in thread
From: Linus Walleij @ 2025-10-14 10:44 UTC (permalink / raw)
To: Gary Yang
Cc: robh, krzk+dt, conor+dt, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, cix-kernel-upstream
Hi Gary,
thanks for your patch!
On Tue, Oct 14, 2025 at 3:57 AM Gary Yang <gary.yang@cixtech.com> wrote:
> +# Client device subnode's properties
> +patternProperties:
> + 'pins$':
> + type: object
> + additionalProperties: false
> + patternProperties:
> + '(^pins|pins?$)':
> + type: object
> + additionalProperties: false
> + description:
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, and drive strength.
> +
> + properties:
> + pinmux:
> + description:
> + Values are constructed from pin number and mux setting and are
> + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly.
> +
> + bias-disable: true
> +
> + bias-pull-up: true
> +
> + bias-pull-down: true
> +
> + drive-strength:
> + description:
> + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
> + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h.
> +
> + required:
> + - pinmux
Can't you just include both pinmux-node.yaml and pincfg-node.yaml
to get validation from the generic schemas?
'pins$':
type: object
additionalProperties: false
patternProperties:
'(^pins|pins?$)':
type: object
$ref: /schemas/pinctrl/pinmux-node.yaml
$ref: /schemas/pinctrl/pincfg-node.yaml
additionalProperties: false
Something like this, I never get this right before actually testcompiling...
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1
2025-10-14 1:57 ` [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1 Gary Yang
@ 2025-10-14 10:57 ` Linus Walleij
2025-10-16 5:41 ` 回复: " Gary Yang
0 siblings, 1 reply; 11+ messages in thread
From: Linus Walleij @ 2025-10-14 10:57 UTC (permalink / raw)
To: Gary Yang
Cc: robh, krzk+dt, conor+dt, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, cix-kernel-upstream
Hi Gary,
this looks very nice, as long as we finish the bindings we can
soon merge this I hope.
Some small comments!
On Tue, Oct 14, 2025 at 3:57 AM Gary Yang <gary.yang@cixtech.com> wrote:
> There are two pin-controllers on Cix Sky1 platform.
> one is used under S0 state, the other is used under S0 and S5 state.
>
> Signed-off-by: Gary Yang <gary.yang@cixtech.com>
(...)
> +config PINCTRL_SKY1
> + tristate "Cix Sky1 pinctrl driver"
> + depends on ARCH_CIX
Maybe depends on ARCH_CIX || COMPILE_TEST so we
get some compile testing in the test farms and also a test
on the rest of the dependencies.
(Makes the bots complain so we can fix all such things!)
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/pinctrl/machine.h>
Do you really need <linux/pinctrl/machine.h>?
Another thing you might want to consider is whether the
designware GPIO will use this pin controller as
"back-end" for the GPIOs using gpio-ranges in the
GPIO controller nodes, for example (I just made this up):
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
Then you might want to implement the GPIO
accelerator operations in struct pinmux_ops, i.e. these:
* @gpio_request_enable: requests and enables GPIO on a certain pin.
* Implement this only if you can mux every pin individually as GPIO. The
* affected GPIO range is passed along with an offset(pin number) into that
* specific GPIO range - function selectors and pin groups are orthogonal
* to this, the core will however make sure the pins do not collide.
* @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
* @gpio_request_enable
* @gpio_set_direction: Since controllers may need different configurations
* depending on whether the GPIO is configured as input or output,
* a direction selector function may be implemented as a backing
* to the GPIO controllers that need pin muxing.
* @strict: do not allow simultaneous use of the same pin for GPIO and another
* function. Check both gpio_owner and mux_owner strictly before approving
* the pin request.
And nowadays it is also worth considering using:
bool (*function_is_gpio) (struct pinctrl_dev *pctldev,
unsigned int selector);
To make the pinctrl core awara of a certain function selector being the
GPIO function (which makes the accelerated functions work much better
with the strict mode).
This can all be added later in separate patches, but this is a good time
to make sure nothing stands in the way of doing this.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl
2025-10-14 10:44 ` Linus Walleij
@ 2025-10-14 17:58 ` Conor Dooley
2025-10-14 19:17 ` Linus Walleij
0 siblings, 1 reply; 11+ messages in thread
From: Conor Dooley @ 2025-10-14 17:58 UTC (permalink / raw)
To: Linus Walleij
Cc: Gary Yang, robh, krzk+dt, conor+dt, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel, cix-kernel-upstream
[-- Attachment #1: Type: text/plain, Size: 2369 bytes --]
On Tue, Oct 14, 2025 at 12:44:15PM +0200, Linus Walleij wrote:
> Hi Gary,
>
> thanks for your patch!
>
> On Tue, Oct 14, 2025 at 3:57 AM Gary Yang <gary.yang@cixtech.com> wrote:
>
>
> > +# Client device subnode's properties
> > +patternProperties:
> > + 'pins$':
> > + type: object
> > + additionalProperties: false
> > + patternProperties:
> > + '(^pins|pins?$)':
> > + type: object
> > + additionalProperties: false
> > + description:
> > + A pinctrl node should contain at least one subnodes representing the
> > + pinctrl groups available on the machine. Each subnode will list the
> > + pins it needs, and how they should be configured, with regard to muxer
> > + configuration, pullups, and drive strength.
> > +
> > + properties:
> > + pinmux:
> > + description:
> > + Values are constructed from pin number and mux setting and are
> > + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly.
> > +
> > + bias-disable: true
> > +
> > + bias-pull-up: true
> > +
> > + bias-pull-down: true
> > +
> > + drive-strength:
> > + description:
> > + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
> > + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h.
Isn't this wrong?
drive-strength is in mA but you're just shoving register values in here.
pw-bot: changes-requested
> > +
> > + required:
> > + - pinmux
>
> Can't you just include both pinmux-node.yaml and pincfg-node.yaml
> to get validation from the generic schemas?
>
> 'pins$':
> type: object
> additionalProperties: false
> patternProperties:
> '(^pins|pins?$)':
Why does this pattern allow foopin but not pinfoo?
Also seems overkill to have both suffix and prefix options, instead of
just sticking to one!
> type: object
> $ref: /schemas/pinctrl/pinmux-node.yaml
> $ref: /schemas/pinctrl/pincfg-node.yaml
> additionalProperties: false
>
> Something like this, I never get this right before actually testcompiling...
spacemit,k1-pinctrl has a node of this type, that can be copied from
Gary. Essentially, you need an allOf: for the two references.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl
2025-10-14 17:58 ` Conor Dooley
@ 2025-10-14 19:17 ` Linus Walleij
0 siblings, 0 replies; 11+ messages in thread
From: Linus Walleij @ 2025-10-14 19:17 UTC (permalink / raw)
To: Conor Dooley
Cc: Gary Yang, robh, krzk+dt, conor+dt, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel, cix-kernel-upstream
On Tue, Oct 14, 2025 at 7:58 PM Conor Dooley <conor@kernel.org> wrote:
> > > + drive-strength:
> > > + description:
> > > + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
> > > + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h.
(side note to Gary: drop the reference to the arch/arm64 etc
sky1-pinfunc.h file,
this is Linux-specific and U-Boot and BSD will be confused)
> Isn't this wrong?
> drive-strength is in mA but you're just shoving register values in here.
> pw-bot: changes-requested
That's right, Gary do you think you can add a mA->strength value
translation table into the driver and let this be configured in mA?
> > type: object
> > $ref: /schemas/pinctrl/pinmux-node.yaml
> > $ref: /schemas/pinctrl/pincfg-node.yaml
> > additionalProperties: false
> >
> > Something like this, I never get this right before actually testcompiling...
>
> spacemit,k1-pinctrl has a node of this type, that can be copied from
> Gary. Essentially, you need an allOf: for the two references.
Neat, thanks Conor!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* 回复: [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1
2025-10-14 10:57 ` Linus Walleij
@ 2025-10-16 5:41 ` Gary Yang
2025-10-16 22:51 ` Linus Walleij
0 siblings, 1 reply; 11+ messages in thread
From: Gary Yang @ 2025-10-16 5:41 UTC (permalink / raw)
To: Linus Walleij
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
Hi Linus:
Thanks for your comments
>
> EXTERNAL EMAIL
>
> Hi Gary,
>
> this looks very nice, as long as we finish the bindings we can soon merge this I
> hope.
>
> Some small comments!
>
> On Tue, Oct 14, 2025 at 3:57 AM Gary Yang <gary.yang@cixtech.com> wrote:
>
>
> > There are two pin-controllers on Cix Sky1 platform.
> > one is used under S0 state, the other is used under S0 and S5 state.
> >
> > Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> (...)
>
> > +config PINCTRL_SKY1
> > + tristate "Cix Sky1 pinctrl driver"
> > + depends on ARCH_CIX
>
> Maybe depends on ARCH_CIX || COMPILE_TEST so we get some compile
> testing in the test farms and also a test on the rest of the dependencies.
>
> (Makes the bots complain so we can fix all such things!)
>
OK, we will add COMPILE_TEST in next version.
> > +#include <linux/device.h>
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pinctrl/machine.h>
>
> Do you really need <linux/pinctrl/machine.h>?
>
Yes, You‘re right, it is a legacy issue. We will remove it next version
> Another thing you might want to consider is whether the designware GPIO will
> use this pin controller as "back-end" for the GPIOs using gpio-ranges in the
> GPIO controller nodes, for example (I just made this up):
>
> gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
>
> Then you might want to implement the GPIO accelerator operations in struct
> pinmux_ops, i.e. these:
>
> * @gpio_request_enable: requests and enables GPIO on a certain pin.
> * Implement this only if you can mux every pin individually as GPIO.
> The
> * affected GPIO range is passed along with an offset(pin number) into
> that
> * specific GPIO range - function selectors and pin groups are
> orthogonal
> * to this, the core will however make sure the pins do not collide.
> * @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
> * @gpio_request_enable
> * @gpio_set_direction: Since controllers may need different configurations
> * depending on whether the GPIO is configured as input or output,
> * a direction selector function may be implemented as a backing
> * to the GPIO controllers that need pin muxing.
> * @strict: do not allow simultaneous use of the same pin for GPIO and
> another
> * function. Check both gpio_owner and mux_owner strictly before
> approving
> * the pin request.
>
> And nowadays it is also worth considering using:
>
> bool (*function_is_gpio) (struct pinctrl_dev *pctldev,
> unsigned int selector);
>
> To make the pinctrl core awara of a certain function selector being the GPIO
> function (which makes the accelerated functions work much better with the
> strict mode).
>
> This can all be added later in separate patches, but this is a good time to make
> sure nothing stands in the way of doing this.
>
GPIO IP on Sky1 is Cadence, not Synopsys designware. We wants to do it when upstream GPIO driver in the future.
Are you agree?
> Yours,
> Linus Walleij
Best wishes
Gary
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1
2025-10-16 5:41 ` 回复: " Gary Yang
@ 2025-10-16 22:51 ` Linus Walleij
2025-10-17 1:43 ` 回复: " Gary Yang
0 siblings, 1 reply; 11+ messages in thread
From: Linus Walleij @ 2025-10-16 22:51 UTC (permalink / raw)
To: Gary Yang
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
On Thu, Oct 16, 2025 at 7:41 AM Gary Yang <gary.yang@cixtech.com> wrote:
> GPIO IP on Sky1 is Cadence, not Synopsys designware. We wants to do
> it when upstream GPIO driver in the future.
> Are you agree?
Yes no problem. (I misremembered that it was Cadence, not Synopsys...)
When I look at the Cadence driver I see it needs some modifications
if it should work properly with GPIO ranges and interoperate with
pin controllers. It needs to call gpiochip_generic_request() and
gpiochip_generic_free() from its request/free functions, and
preferably also gpiochip_generic_config() which will extend
the gpiolib to call down to the pin controller and take control
over line properties.
But let's do that in a separate patch!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* 回复: [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1
2025-10-16 22:51 ` Linus Walleij
@ 2025-10-17 1:43 ` Gary Yang
0 siblings, 0 replies; 11+ messages in thread
From: Gary Yang @ 2025-10-17 1:43 UTC (permalink / raw)
To: Linus Walleij
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
Hi Linus,
I'm glad to see your kind comments
>
> EXTERNAL EMAIL
>
> On Thu, Oct 16, 2025 at 7:4 AM Gary Yang <gary.yang@cixtech.com> wrote:
>
> > GPIO IP on Sky1 is Cadence, not Synopsys designware. We wants to do it
> > when upstream GPIO driver in the future.
> > Are you agree?
>
> Yes no problem. (I misremembered that it was Cadence, not Synopsys...)
>
> When I look at the Cadence driver I see it needs some modifications if it should
> work properly with GPIO ranges and interoperate with pin controllers. It needs
> to call gpiochip_generic_request() and
> gpiochip_generic_free() from its request/free functions, and preferably also
> gpiochip_generic_config() which will extend the gpiolib to call down to the pin
> controller and take control over line properties.
>
> But let's do that in a separate patch!
>
Thanks for your remind and understandings. We need focus on modifying dt-bindings file, and
hope merge pinctrl driver as soon as possible. We will take it consider when upstream GPIO driver later.
> Yours,
> Linus Walleij
Best wishes
Gary
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-10-17 1:43 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-14 1:57 [PATCH v3 0/3] Add pinctrl support for Sky1 Gary Yang
2025-10-14 1:57 ` [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Gary Yang
2025-10-14 10:44 ` Linus Walleij
2025-10-14 17:58 ` Conor Dooley
2025-10-14 19:17 ` Linus Walleij
2025-10-14 1:57 ` [PATCH v3 2/3] pinctrl: cix: Add pin-controller support for sky1 Gary Yang
2025-10-14 10:57 ` Linus Walleij
2025-10-16 5:41 ` 回复: " Gary Yang
2025-10-16 22:51 ` Linus Walleij
2025-10-17 1:43 ` 回复: " Gary Yang
2025-10-14 1:57 ` [PATCH v3 3/3] arm64: dts: cix: Add pinctrl nodes " Gary Yang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).