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From: Linus Walleij <linus.walleij@linaro.org>
To: Robin van der Gracht <robin@protonic.nl>,
	Shawn Guo <shawn.guo@linaro.org>,
	Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>,
	Maxime Ripard <maxime.ripard@free-electrons.com>,
	Sascha Hauer <kernel@pengutronix.de>
Cc: Alexandre Courbot <gnurou@gmail.com>,
	"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
	David Jander <david@protonic.nl>, Marek Vasut <marex@denx.de>
Subject: Re: [PATCH] gpio: mxs: Use PIN2IRQ register to mask interrupts
Date: Tue, 13 Jan 2015 07:34:31 +0100	[thread overview]
Message-ID: <CACRpkdaqPVED6U6mYWEzfrbtoYdfmdGZ34jjmokMp_KfOCZnaQ@mail.gmail.com> (raw)
In-Reply-To: <1418639312-12520-1-git-send-email-robin@protonic.nl>

On Mon, Dec 15, 2014 at 11:28 AM, Robin van der Gracht
<robin@protonic.nl> wrote:

> The PIN2IRQ register should be used to mask an interrupt. Clearing a
> bit in the IRQEN register only prevents the interrupt from propagating but
> still allows hardware to set the status bit when triggered. So when
> unmasking the interrupt, it will immediately re-trigger if an interrupt
> condition occurred during masking.
>
> This is unwanted behavior especially when using level triggered
> interrupts. In this case every interrupt triggers twice. If the
> interrupt is handled in the handler, the second interrupt will be
> the first one to be able to ack the interrupt.
>
> Signed-off-by: Robin van der Gracht <robin@protonic.nl>

Apparently MXS is a popular GPIO controller without a real maintainer.

Adding some random users to the To: line hoping we get some
review of this patch.

Yours,
Linus Walleij

  reply	other threads:[~2015-01-13  6:34 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-15 10:28 [PATCH] gpio: mxs: Use PIN2IRQ register to mask interrupts Robin van der Gracht
2015-01-13  6:34 ` Linus Walleij [this message]
2015-01-13 14:21   ` Shawn Guo

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