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AJvYcCV9+A72WYbT5oVSsSCgclU7NZOfl7qlllCqq3oVEJOiDGXw46DnrvxeUwloGbC3b4r5pGUDv5sdSoWN@vger.kernel.org X-Gm-Message-State: AOJu0YzDlyifUzi7hXfV8poi6zOJBB7KM16fRQJx1lWtECmpunwwmfwx CSOuNPzwGDXjrXJ1TO4c4/DFjKxpFqB21u2zEyMWOGd3iJLdkngp0Zmb5rqBP0bMc7MAP6E/dRn 6rwuvOWuB+G6vwTTkUwlrZ9fRSXGQD4F2abPwrEd6VQ== X-Gm-Gg: ASbGnct/BjoU+t7NF1h+6J3tVC8LZ9YB79KIj+Z/UnCsTuJ/36PEv+gPFFBsBW1Obfp UQowg/7pk28OyjcGUTAY5FzVlBIO2lWi49KlS5zXZ9Ufn8vH91SV02jIkT6YeQLR4SxF0yEb/t2 CweoxlIGXJlnphFitQFe6yQngho4vbgsmbX8d9ep5moztY2Wr9FOjEZEQrDCKEngwZrGgkvTirt VmJYjs= X-Google-Smtp-Source: AGHT+IEg/39vWPjh633ZUj8UqZLuNkeQ4zJb+DeEXqhdOGqkb2UzJv4loDelR2kMaTSHX23IkdKGCBQxVkP3ySeashA= X-Received: by 2002:a05:651c:4ca:b0:32b:755e:6cd7 with SMTP id 38308e7fff4ca-3305509f9c8mr19310751fa.32.1752348428638; Sat, 12 Jul 2025 12:27:08 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250710002047.1573841-1-ksk4725@coasia.com> In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> From: Linus Walleij Date: Sat, 12 Jul 2025 21:26:57 +0200 X-Gm-Features: Ac12FXwfRBs5js5oSquCaRb4DKz10a2pVgF5CqiS_5Na7OWkjOlWh-jR8X6bLJY Message-ID: Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC To: ksk4725@coasia.com Cc: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , SungMin Park , Pankaj Dubey , Shradha Todi , Ravi Patel , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Hakyeong, thanks for your patch! On Thu, Jul 10, 2025 at 2:20=E2=80=AFAM wrote: > Add basic support for the Axis ARTPEC-8 SoC. > This SoC contains four Cortex-A53 CPUs and other several IPs. > > Patches 1 to 10 provide the support for the clock controller, > which is similar to other Samsung SoCs. > > The remaining patches provide pinctrl support and > initial device tree support. > > Hakyeong Kim (9): > dt-bindings: clock: Add ARTPEC-8 CMU bindings > clk: samsung: Add clock PLL support for ARTPEC-8 SoC > clk: samsung: artpec-8: Add initial clock support > clk: samsung: artpec-8: Add clock support for CMU_CMU block > clk: samsung: artpec-8: Add clock support for CMU_BUS block > clk: samsung: artpec-8: Add clock support for CMU_CORE block > clk: samsung: artpec-8: Add clock support for CMU_CPUCL block > clk: samsung: artpec-8: Add clock support for CMU_FSYS block > clk: samsung: artpec-8: Add clock support for CMU_PERI block Out of the 9 patches there are 7 patches related to "CMU" without any explanation or even expansion of this acronym. Camera Management Unit? I think I'm not supposed to guess. Is is an Axis-custom piece of hardware? (Would make sense.) Please expand this acronym and state clearly that (if this is a correct assumption) that you are not supplying any bindings and even less a driver for the "CMU" thing, just the clocks. (That's fine the actual CMU can come later, but it should be clear *what* it is.) Yours, Linus Walleij