From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [PATCHv5 2/2] Add a GPIO driver for Altera FPGA Manager Fabric I/O Date: Tue, 31 Oct 2017 11:04:15 +0100 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Received: from mail-io0-f195.google.com ([209.85.223.195]:44773 "EHLO mail-io0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754307AbdJaKEQ (ORCPT ); Tue, 31 Oct 2017 06:04:16 -0400 Received: by mail-io0-f195.google.com with SMTP id m16so33766753iod.1 for ; Tue, 31 Oct 2017 03:04:16 -0700 (PDT) In-Reply-To: Sender: linux-gpio-owner@vger.kernel.org List-Id: linux-gpio@vger.kernel.org To: Bernd Edlinger Cc: Rob Herring , Christian Lamparter , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" On Thu, Oct 26, 2017 at 5:28 PM, Bernd Edlinger wrote: > This is an internal 32-bit input and 32-bit output port to the FPGA logic. > > Instantiate this in the device tree as: > > gpio3: gpio@ff706010 { > #address-cells = <1>; > #size-cells = <0>; > compatible = "altr,fpgamgr-gpio"; > reg = <0xff706010 0x8>; > status = "okay"; > > portd: gpio-controller@0 { > compatible = "altr,fpgamgr-gpio-output"; > gpio-controller; > #gpio-cells = <2>; > reg = <0>; > }; > > porte: gpio-controller@1 { > compatible = "altr,fpgamgr-gpio-input"; > gpio-controller; > #gpio-cells = <2>; > reg = <1>; > }; > }; > > Signed-off-by: Bernd Edlinger (...) > + err = bgpio_init(&port->bgc, gpio->dev, 4, dat, NULL, NULL, > + NULL, NULL, pp->idx ? BGPIOF_NO_OUTPUT : 0); Don't magically use the index to determine which block us input-only. Use the port-specific compatible string and match to handle this using .data in the match. Yours, Linus Walleij