From: Linus Walleij <linus.walleij@linaro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register
Date: Tue, 14 Nov 2023 08:45:56 +0100 [thread overview]
Message-ID: <CACRpkdb14A5z2nhe18VupwPdDvuOXxM68nTrU-drO9nRNhWmzA@mail.gmail.com> (raw)
In-Reply-To: <20231013145935.220945-3-krzysztof.kozlowski@linaro.org>
On Fri, Oct 13, 2023 at 4:59 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> Existing Qualcomm SoCs have the LPASS pin controller slew rate control
> in separate register, however this will change with upcoming Qualcomm
> SoCs. The slew rate will be part of the main register for pin
> configuration, thus second device IO address space is not needed.
>
> Prepare for supporting new SoCs by adding flag customizing the driver
> behavior for slew rate.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patches applied.
Yours,
Linus Walleij
next prev parent reply other threads:[~2023-11-14 7:46 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 14:59 [PATCH v2 0/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Krzysztof Kozlowski
2023-10-13 14:59 ` [PATCH v2 1/2] pinctrl: qcom: lpass-lpi: split slew rate set to separate function Krzysztof Kozlowski
2023-10-18 8:51 ` Konrad Dybcio
2023-10-13 14:59 ` [PATCH v2 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Krzysztof Kozlowski
2023-10-18 9:00 ` Konrad Dybcio
2023-11-14 7:45 ` Linus Walleij [this message]
2023-10-23 8:19 ` [PATCH v2 0/2] " Linus Walleij
2023-10-23 8:22 ` Krzysztof Kozlowski
2023-10-23 8:27 ` Linus Walleij
2023-10-23 8:48 ` Krzysztof Kozlowski
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