* [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
@ 2023-03-02 15:52 Krzysztof Kozlowski
2023-03-07 13:32 ` Linus Walleij
2023-03-08 20:33 ` Rob Herring
0 siblings, 2 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-02 15:52 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Srinivas Kandagatla,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
The description of second IO address is a bit confusing. It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base. The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +-
.../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +-
.../bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
index 200b3b6ccd87..a9167dac9ab5 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
@@ -20,7 +20,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- - description: LPASS LPI pins SLEW registers
+ - description: LPASS LPI MCC registers
clocks:
items:
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
index 8bf51df0b231..1eefa9aa6a86 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
@@ -20,7 +20,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- - description: LPASS LPI pins SLEW registers
+ - description: LPASS LPI MCC registers
clocks:
items:
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
index 5e90051ed314..691bf60abb8c 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
@@ -21,7 +21,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- - description: LPASS LPI pins SLEW registers
+ - description: LPASS LPI MCC registers
clocks:
items:
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
2023-03-02 15:52 [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg Krzysztof Kozlowski
@ 2023-03-07 13:32 ` Linus Walleij
2023-03-07 13:39 ` Krzysztof Kozlowski
2023-03-08 20:33 ` Rob Herring
1 sibling, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2023-03-07 13:32 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Srinivas Kandagatla, linux-arm-msm,
linux-gpio, devicetree, linux-kernel
On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> The description of second IO address is a bit confusing. It is supposed
> to be the MCC range which contains the slew rate registers, not the slew
> rate register base. The Linux driver then accesses slew rate register
> with hard-coded offset (0xa000).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
LGTM, is this something I should just apply or will you collect a larger
series of Qcom DT patches this time around as well?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
2023-03-07 13:32 ` Linus Walleij
@ 2023-03-07 13:39 ` Krzysztof Kozlowski
2023-03-09 13:46 ` Linus Walleij
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-07 13:39 UTC (permalink / raw)
To: Linus Walleij
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Srinivas Kandagatla, linux-arm-msm,
linux-gpio, devicetree, linux-kernel
On 07/03/2023 14:32, Linus Walleij wrote:
> On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>
>> The description of second IO address is a bit confusing. It is supposed
>> to be the MCC range which contains the slew rate registers, not the slew
>> rate register base. The Linux driver then accesses slew rate register
>> with hard-coded offset (0xa000).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> LGTM, is this something I should just apply or will you collect a larger
> series of Qcom DT patches this time around as well?
Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
technical debt, thus no more work for me!
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
2023-03-07 13:39 ` Krzysztof Kozlowski
@ 2023-03-09 13:46 ` Linus Walleij
2023-03-09 16:11 ` Krzysztof Kozlowski
0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2023-03-09 13:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Srinivas Kandagatla, linux-arm-msm,
linux-gpio, devicetree, linux-kernel
On Tue, Mar 7, 2023 at 2:40 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 07/03/2023 14:32, Linus Walleij wrote:
> > On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >
> >> The description of second IO address is a bit confusing. It is supposed
> >> to be the MCC range which contains the slew rate registers, not the slew
> >> rate register base. The Linux driver then accesses slew rate register
> >> with hard-coded offset (0xa000).
> >>
> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >
> > LGTM, is this something I should just apply or will you collect a larger
> > series of Qcom DT patches this time around as well?
>
> Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
> technical debt, thus no more work for me!
OK patch applied!
Also: good job! The Qualcomm bindings look very nice now.
But what about these oldskool bindings?
$ ls Documentation/devicetree/bindings/pinctrl/qcom,*.txt
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
2023-03-09 13:46 ` Linus Walleij
@ 2023-03-09 16:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-09 16:11 UTC (permalink / raw)
To: Linus Walleij
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Srinivas Kandagatla, linux-arm-msm,
linux-gpio, devicetree, linux-kernel
On 09/03/2023 14:46, Linus Walleij wrote:
>> Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
>> technical debt, thus no more work for me!
>
> OK patch applied!
>
> Also: good job! The Qualcomm bindings look very nice now.
>
> But what about these oldskool bindings?
> $ ls Documentation/devicetree/bindings/pinctrl/qcom,*.txt
> Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
> Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
> Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
> Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
Low priority for me, but I will get to them at some point :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
2023-03-02 15:52 [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg Krzysztof Kozlowski
2023-03-07 13:32 ` Linus Walleij
@ 2023-03-08 20:33 ` Rob Herring
1 sibling, 0 replies; 6+ messages in thread
From: Rob Herring @ 2023-03-08 20:33 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, linux-kernel, devicetree, Andy Gross, linux-gpio,
Konrad Dybcio, Srinivas Kandagatla, Linus Walleij,
Krzysztof Kozlowski, linux-arm-msm, Rob Herring
On Thu, 02 Mar 2023 16:52:55 +0100, Krzysztof Kozlowski wrote:
> The description of second IO address is a bit confusing. It is supposed
> to be the MCC range which contains the slew rate registers, not the slew
> rate register base. The Linux driver then accesses slew rate register
> with hard-coded offset (0xa000).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +-
> .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +-
> .../bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
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2023-03-02 15:52 [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg Krzysztof Kozlowski
2023-03-07 13:32 ` Linus Walleij
2023-03-07 13:39 ` Krzysztof Kozlowski
2023-03-09 13:46 ` Linus Walleij
2023-03-09 16:11 ` Krzysztof Kozlowski
2023-03-08 20:33 ` Rob Herring
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