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From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Steven Lee <steven_lee@aspeedtech.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@aj.id.au>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	"moderated list:ARM/ASPEED MACHINE SUPPORT" 
	<linux-arm-kernel@lists.infradead.org>,
	"moderated list:ARM/ASPEED MACHINE SUPPORT" 
	<linux-aspeed@lists.ozlabs.org>,
	open list <linux-kernel@vger.kernel.org>,
	Hongweiz@ami.com, ryan_chen@aspeedtech.com,
	Billy Tsai <billy_tsai@aspeedtech.com>
Subject: Re: [PATCH v3 3/5] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
Date: Thu, 3 Jun 2021 14:05:53 +0300	[thread overview]
Message-ID: <CAHp75Vef0HDXAHzSNL-LtA0Sra6Zpivt513_+aFR_um0JeFkog@mail.gmail.com> (raw)
In-Reply-To: <20210603101822.9645-4-steven_lee@aspeedtech.com>

On Thu, Jun 3, 2021 at 1:19 PM Steven Lee <steven_lee@aspeedtech.com> wrote:
>
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> In the current driver, the maximum number of gpio pins of SoC is hardcoded
> as 80 and the gpio pin count mask for GPIO Configuration register is
> hardcode as GENMASK(9,6). In addition, some functions uses the hardcoded

use

> value to calculate the gpio offset.
> The patch adds ast2600 compatibles and platform data that includes the
> max number of gpio pins supported by ast2600 and gpio pin count mask for
> GPIO Configuration register.
> The patch also modifies some functions to pass aspeed_sgpio struct for
> calculating gpio offset wihtout using the hardcoded value.

without

...

> +#include <linux/of_device.h>

Why?

...

> +#define GPIO_OFFSET(x)        ((x) & 0x1f)

GENMASK()

...

> +       pdata = of_device_get_match_data(&pdev->dev);

device_get_match_data()

I guess you may replace all those of_*() to the corresponding
device_*() or fwnode_*() calls.

-- 
With Best Regards,
Andy Shevchenko

  reply	other threads:[~2021-06-03 11:06 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03 10:18 [PATCH v3 0/5] ASPEED sgpio driver enhancement Steven Lee
2021-06-03 10:18 ` [PATCH v3 1/5] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
2021-06-03 23:25   ` Andrew Jeffery
2021-06-04  3:30     ` Steven Lee
2021-06-04  3:40       ` Andrew Jeffery
2021-06-09  9:17       ` Linus Walleij
2021-06-03 10:18 ` [PATCH v3 2/5] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee
2021-06-03 23:29   ` Andrew Jeffery
2021-06-03 10:18 ` [PATCH v3 3/5] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee
2021-06-03 11:05   ` Andy Shevchenko [this message]
2021-06-04  2:08     ` Steven Lee
2021-06-04  2:14     ` Steven Lee
2021-06-04 10:21       ` Andy Shevchenko
2021-06-03 10:18 ` [PATCH v3 4/5] gpio: gpio-aspeed-sgpio: Add set_config function Steven Lee
2021-06-03 11:07   ` Andy Shevchenko
2021-06-04  2:18     ` Steven Lee
2021-06-03 10:18 ` [PATCH v3 5/5] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct Steven Lee
2021-06-03 23:28   ` Andrew Jeffery

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