From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 317E9C433F5 for ; Thu, 14 Oct 2021 20:07:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 071BA61027 for ; Thu, 14 Oct 2021 20:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231570AbhJNUJK (ORCPT ); Thu, 14 Oct 2021 16:09:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234078AbhJNUJJ (ORCPT ); Thu, 14 Oct 2021 16:09:09 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F25EC061755 for ; Thu, 14 Oct 2021 13:07:04 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id ec8so28929669edb.6 for ; Thu, 14 Oct 2021 13:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=tOC9prHZYIEZh+iOSkgASgqcP4dzHU1Vi2nx843IsCk=; b=NL0BrbBgqbeg+0k1NdyHAoUworVxwn/bPXtWcOyPrJjiIpNlT1faHXA45eyP9NndQ8 GY6YgAmOHLAZ/tAmiSlkjl6N8hPbdMSxqgVNlAkQWq4zFMK0JLWO7AArMg2YnWWk2jSp k3WkVkHvKn3O99QXT7K3GiVbGxYD/qzA3Bw94Yswc2z3skllu6r8XA+f/34SzUTYrVno +RIWyNtx2rCeOe/yliw4fna8bHmSd0oZjw9hN+mJnzJL47/a/yr3XjQDu7aRj4zYWWVv 4EypWFYkT+zi4P4XBv6M0hYyyXU8d9p2vYXwozwbXGocu6QkkGopMHu6J9GPflpKU/6N gtyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tOC9prHZYIEZh+iOSkgASgqcP4dzHU1Vi2nx843IsCk=; b=ExCxK9dDAsDTjuFCjqR0MO1NAZwLle7ZAXakD5UzqG3MDpL0o9ijRkMJTtcmCkAAOK tROrcMSoWNAxdRnP4LaRKOfUtfOwmINF/zXNzx9peabREz0FsnU2TdlcBJL7+GACQz76 ZGxCmo0fjFSY0jkOR7UazZT2vIh3cuuoH3rWRLdjmEy5rYbbn8JzhU3KJtBuAq5k6uj8 JamyxhxBZ1t3bJ8StLe0fbDk+UrS8Awk8LM/ELeHII51eWDXLHcAe64IR/XfHccpamhP rVyjy2Zfn0vr1fDjZBrufONtdnKciN1mW0VbfA+32T0VVOin0uCpGQBYKp6ByN0TFzi5 E8ug== X-Gm-Message-State: AOAM533+Swft5J3wrhQmFTvgtzXF0dtpsE3ZDJBfvvSJLtctzGXLHsIe rsnofbFyXuQo8a9VfJx3FbU10AbPPXbdasf5GMxQBQ== X-Google-Smtp-Source: ABdhPJxD9UzCWfjeFxRsC1YkcQ1vTaG6mft6f+Mucv9VjzzB99L17qlsFkC2Y1a/7iwSh5iOwxPa20nY0PCyjOOngtw= X-Received: by 2002:a17:906:b19:: with SMTP id u25mr1397747ejg.36.1634242022767; Thu, 14 Oct 2021 13:07:02 -0700 (PDT) MIME-Version: 1.0 References: <20210304034141.7062-1-brad@pensando.io> <20210304034141.7062-2-brad@pensando.io> <20210304091025.ny52qjm7wbfvmjgl@mobilestation> In-Reply-To: From: Brad Larson Date: Thu, 14 Oct 2021 13:06:52 -0700 Message-ID: Subject: Re: [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control To: Linus Walleij Cc: Mark Brown , Serge Semin , Linux ARM , Arnd Bergmann , Bartosz Golaszewski , Adrian Hunter , Ulf Hansson , Olof Johansson , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Tue, Oct 12, 2021 at 4:52 PM Linus Walleij wrote: > > On Mon, Oct 4, 2021 at 6:46 PM Brad Larson wrote: > > > Yes that works, please see the diff below where the file > > gpio-elba-spics.c goes away. The original implementation was > > motivated by gpio-spear-spics.c. > > This looks good to me :) > > Yours, > Linus Walleij Hi Linus, :-) It's better to not have to look at a related gpio driver file to the spi-dw-mmio.c driver and think it could possibly be used as general purpose gpio. Here is a response summary per patch. Should I start respinning the patchset against the latest linux-next tag? The changes are merged to our production 5.10.28 kernel and the next step is to re-spin the set against the latest linux-next which has a newer dtc, run checkpatch, etc. For reference as this has been cooking for awhile here is the overview from V2 patchset cover letter. This series enables support for Pensando Elba SoC based platforms. The Elba SoC has the following features: - Sixteen ARM64 A72 cores - Dual DDR 4/5 memory controllers - 32 lanes of PCIe Gen3/4 to the Host - Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and also a single 1GE management port. - Storage/crypto offloads and 144 programmable P4 cores. - QSPI and EMMC for SoC storage - Two SPI interfaces for peripheral management - I2C bus for platform management Summary of response to V1/V2 patchset 0001-gpio-Add-Elba-SoC-gpio-driver-for-spi-cs-control.patch - This patch is deleted. Elba SOC specific gpio spics control is integrated into spi-dw-mmio.c. 0002-spi-cadence-quadspi-Add-QSPI-support-for-Pensando-El.patch - Changed compatible to "pensando,elba-qspi" to be more descriptive in spi-cadence-quadspi.c. - Arnd wondered if moving to DT properties for quirks may be the way to go. Feedback I've received on other patches was don't mix two efforts in one patch so I'm currently just adding the Elba support to the current design. 0003-spi-dw-Add-support-for-Pensando-Elba-SoC-SPI.patch - Changed the implementation to use existing dw_spi_set_cs() and integrated Elba specific CS control into spi-dw-mmio.c. The native designware support is for two chip-selects while Elba provides 4 chip-selects. Instead of adding a new file for this support in gpio-elba-spics.c the support is in one file (spi-dw-mmio.c). 0004-spidev-Add-Pensando-CPLD-compatible.patch - This patch is deleted. The addition of compatible "pensando,cpld" to spidev.c is removed. 0005-mmc-sdhci-cadence-Add-Pensando-Elba-SoC-support.patch - Ulf and Yamada-san agreed the amount of code for this support is not enough to need a new file. The support is added into sdhci-cadence.c and new files sdhci-cadence-elba.c and sdhci-cadence.h are deleted. - Redundant defines are removed (e.g. use SDHCI_CDNS_HRS04 and remove SDIO_REG_HRS4). - Removed phy init function sd4_set_dlyvr() and used existing sdhci_cdns_phy_init(). Init values are from DT properties. - Replace devm_ioremap_resource(&pdev->dev, iomem) with devm_platform_ioremap_resource(pdev, 1) - Refactored the elba priv_writ_l() and elba_write_l() to remove a little redundant code. - The config option CONFIG_MMC_SDHCI_CADENCE_ELBA goes away. - Only C syntax and Elba functions are prefixed with elba_ 0006-arm64-Add-config-for-Pensando-SoC-platforms.patch - Added a little more info to the platform help text to assist users to decide on including platform support or not. 0007-arm64-dts-Add-Pensando-Elba-SoC-support.patch - Node names changed to DT generic names - Changed from using 'spi@' which is reserved - The elba-flash-parts.dtsi is kept separate as it is included in multiple dts files. - SPDX license tags at the top of each file - The compatible = "pensando,elba" and 'model' are now together in the board file. - UIO nodes removed - Ordered nodes by increasing unit address - Removed an unreferenced container node. - Dropped deprecated 'device_type' for uart0 node. - Added syscon usage 0010-dt-bindings-spi-cadence-qspi-Add-support-for-Pensand.patch - Updated since the latest documentation has been converted to yaml 0011-dt-bindings-gpio-Add-Pensando-Elba-SoC-support.patch - This patch is deleted since the Elba gpio spics is added to the spi dw driver and documented there. Best, Brad