[PATCH 0/2] CAN & CAN FD pinctrl support for r8a7795 SoC

[PATCH 0/2] CAN & CAN FD pinctrl support for r8a7795 SoC

[Ramesh Shanmugasundaram]

This patch set adds CAN & CAN FD pinctrl support for r8a7795 SoC.

This set is based on linux-next repo(tag: next-20160225).

Ramesh Shanmugasundaram (2):
  pinctrl: sh-pfc: r8a7795: Add CAN support
  pinctrl: sh-pfc: r8a7795: Add CAN FD support

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 102 +++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

-- 
1.9.1

[PATCH 1/2] pinctrl: sh-pfc: r8a7795: Add CAN support

[Ramesh Shanmugasundaram]

This patch adds CAN[0-1] pinmux support to r8a7795 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 58 ++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index ce4f5cd..fbe8e95 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -2913,6 +2913,43 @@ static const unsigned int scif_clk_b_mux[] = {
 	SCIF_CLK_B_MARK,
 };
 
+/* - RCAN ------------------------------------------------------------------ */
+static const unsigned int can0_data_a_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
+};
+
+static const unsigned int can0_data_a_mux[] = {
+	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
+};
+
+static const unsigned int can0_data_b_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
+};
+
+static const unsigned int can0_data_b_mux[] = {
+	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
+};
+
+static const unsigned int can1_data_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
+};
+
+static const unsigned int can1_data_mux[] = {
+	CAN1_TX_MARK,		CAN1_RX_MARK,
+};
+/* - RCAN-CLK --------------------------------------------------------------- */
+static const unsigned int can_clk_pins[] = {
+	/* CLK */
+	RCAR_GP_PIN(1, 25),
+};
+
+static const unsigned int can_clk_mux[] = {
+	CAN_CLK_MARK,
+};
+
 /* - SSI -------------------------------------------------------------------- */
 static const unsigned int ssi0_data_pins[] = {
 	/* SDATA */
@@ -3322,6 +3359,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(ssi9_data_b),
 	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+	SH_PFC_PIN_GROUP(can0_data_a),
+	SH_PFC_PIN_GROUP(can0_data_b),
+	SH_PFC_PIN_GROUP(can1_data),
+	SH_PFC_PIN_GROUP(can_clk),
 };
 
 static const char * const audio_clk_groups[] = {
@@ -3636,6 +3677,20 @@ static const char * const ssi_groups[] = {
 	"ssi9_ctrl_b",
 };
 
+static const char * const can0_groups[] = {
+	"can0_data_a",
+	"can0_data_b",
+};
+
+static const char * const can1_groups[] = {
+	"can1_data",
+};
+
+static const char * const can_clk_groups[] = {
+	"can_clk",
+};
+
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(audio_clk),
 	SH_PFC_FUNCTION(avb),
@@ -3664,6 +3719,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi2),
 	SH_PFC_FUNCTION(sdhi3),
 	SH_PFC_FUNCTION(ssi),
+	SH_PFC_FUNCTION(can0),
+	SH_PFC_FUNCTION(can1),
+	SH_PFC_FUNCTION(can_clk),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.9.1

[PATCH 2/2] pinctrl: sh-pfc: r8a7795: Add CAN FD support

[Ramesh Shanmugasundaram]

This patch adds CANFD[0-1] pinmux support to r8a7795 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 44 ++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index fbe8e95..0e6fb18 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -2940,6 +2940,36 @@ static const unsigned int can1_data_pins[] = {
 static const unsigned int can1_data_mux[] = {
 	CAN1_TX_MARK,		CAN1_RX_MARK,
 };
+
+/* - RCAN FD --------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
+};
+
+static const unsigned int canfd0_data_a_mux[] = {
+	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
+};
+
+static const unsigned int canfd0_data_b_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
+};
+
+static const unsigned int canfd0_data_b_mux[] = {
+	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
+};
+
+static const unsigned int canfd1_data_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
+};
+
+static const unsigned int canfd1_data_mux[] = {
+	CANFD1_TX_MARK,         CANFD1_RX_MARK,
+};
+
+
 /* - RCAN-CLK --------------------------------------------------------------- */
 static const unsigned int can_clk_pins[] = {
 	/* CLK */
@@ -3362,6 +3392,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(can0_data_a),
 	SH_PFC_PIN_GROUP(can0_data_b),
 	SH_PFC_PIN_GROUP(can1_data),
+	SH_PFC_PIN_GROUP(canfd0_data_a),
+	SH_PFC_PIN_GROUP(canfd0_data_b),
+	SH_PFC_PIN_GROUP(canfd1_data),
 	SH_PFC_PIN_GROUP(can_clk),
 };
 
@@ -3686,6 +3719,15 @@ static const char * const can1_groups[] = {
 	"can1_data",
 };
 
+static const char * const canfd0_groups[] = {
+	"canfd0_data_a",
+	"canfd0_data_b",
+};
+
+static const char * const canfd1_groups[] = {
+	"canfd1_data",
+};
+
 static const char * const can_clk_groups[] = {
 	"can_clk",
 };
@@ -3721,6 +3763,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(ssi),
 	SH_PFC_FUNCTION(can0),
 	SH_PFC_FUNCTION(can1),
+	SH_PFC_FUNCTION(canfd0),
+	SH_PFC_FUNCTION(canfd1),
 	SH_PFC_FUNCTION(can_clk),
 };
 
-- 
1.9.1

Re: [PATCH 1/2] pinctrl: sh-pfc: r8a7795: Add CAN support

[Geert Uytterhoeven]

On Thu, Feb 25, 2016 at 5:48 PM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
> This patch adds CAN[0-1] pinmux support to r8a7795 SoC.
>
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Add CAN FD support

[Geert Uytterhoeven]

On Thu, Feb 25, 2016 at 5:48 PM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
> This patch adds CANFD[0-1] pinmux support to r8a7795 SoC.
>
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/2] pinctrl: sh-pfc: r8a7795: Add CAN support

[Geert Uytterhoeven]

Hi Ramesh,

On Thu, Feb 25, 2016 at 5:48 PM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
> This patch adds CAN[0-1] pinmux support to r8a7795 SoC.
>
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>

Sorry, I spoke too soon. While the pin data is correct, I noticed the following
while applying:

> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 58 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> index ce4f5cd..fbe8e95 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> @@ -2913,6 +2913,43 @@ static const unsigned int scif_clk_b_mux[] = {
>         SCIF_CLK_B_MARK,
>  };
>
> +/* - RCAN ------------------------------------------------------------------ */

Please use "CAN" instead of "RCAN", and insert in alphabetical order.

> +static const unsigned int can0_data_a_pins[] = {
> +       /* TX, RX */
> +       RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
> +};

> @@ -3322,6 +3359,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
>         SH_PFC_PIN_GROUP(ssi9_data_b),
>         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
>         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
> +       SH_PFC_PIN_GROUP(can0_data_a),
> +       SH_PFC_PIN_GROUP(can0_data_b),
> +       SH_PFC_PIN_GROUP(can1_data),
> +       SH_PFC_PIN_GROUP(can_clk),

Please insert in alphabetical order.

> @@ -3636,6 +3677,20 @@ static const char * const ssi_groups[] = {
>         "ssi9_ctrl_b",
>  };
>
> +static const char * const can0_groups[] = {

Please insert in alphabetical order.

> @@ -3664,6 +3719,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
>         SH_PFC_FUNCTION(sdhi2),
>         SH_PFC_FUNCTION(sdhi3),
>         SH_PFC_FUNCTION(ssi),
> +       SH_PFC_FUNCTION(can0),
> +       SH_PFC_FUNCTION(can1),
> +       SH_PFC_FUNCTION(can_clk),

Please insert in alphabetical order.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Add CAN FD support

[Geert Uytterhoeven]

Hi Ramesh,

On Thu, Feb 25, 2016 at 5:48 PM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
> This patch adds CANFD[0-1] pinmux support to r8a7795 SoC.
>
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>

Sorry, I spoke too soon. While the pin data is correct, I noticed the following
while applying:

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> @@ -2940,6 +2940,36 @@ static const unsigned int can1_data_pins[] = {
>  static const unsigned int can1_data_mux[] = {
>         CAN1_TX_MARK,           CAN1_RX_MARK,
>  };
> +
> +/* - RCAN FD --------------------------------------------------------------- */

Please use "CAN" instead of "RCAN", and insert in alphabetical order.

> +static const unsigned int canfd0_data_a_pins[] = {

> @@ -3362,6 +3392,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
>         SH_PFC_PIN_GROUP(can0_data_a),
>         SH_PFC_PIN_GROUP(can0_data_b),
>         SH_PFC_PIN_GROUP(can1_data),
> +       SH_PFC_PIN_GROUP(canfd0_data_a),
> +       SH_PFC_PIN_GROUP(canfd0_data_b),
> +       SH_PFC_PIN_GROUP(canfd1_data),
>         SH_PFC_PIN_GROUP(can_clk),

Please insert in alphabetical order.

> @@ -3686,6 +3719,15 @@ static const char * const can1_groups[] = {
>         "can1_data",
>  };
>
> +static const char * const canfd0_groups[] = {
> +       "canfd0_data_a",
> +       "canfd0_data_b",
> +};
> +
> +static const char * const canfd1_groups[] = {
> +       "canfd1_data",
> +};

Please insert in alphabetical order.

> +
>  static const char * const can_clk_groups[] = {
>         "can_clk",
>  };
> @@ -3721,6 +3763,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
>         SH_PFC_FUNCTION(ssi),
>         SH_PFC_FUNCTION(can0),
>         SH_PFC_FUNCTION(can1),
> +       SH_PFC_FUNCTION(canfd0),
> +       SH_PFC_FUNCTION(canfd1),
>         SH_PFC_FUNCTION(can_clk),

Please insert in alphabetical order.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 2/2] pinctrl: sh-pfc: r8a7795: Add CAN FD support

[Ramesh Shanmugasundaram]

This patch adds CAN FD[0-1] pinmux support for R-Car H3 ES2.0. The pin
config is identical to H3 ES1.*.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 59249a990cef..34a2dc471e5a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1813,6 +1813,29 @@ static const unsigned int can_clk_mux[] = {
 	CAN_CLK_MARK,
 };
 
+/* - CAN FD --------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
+};
+static const unsigned int canfd1_data_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
+};
+static const unsigned int canfd1_data_mux[] = {
+	CANFD1_TX_MARK,         CANFD1_RX_MARK,
+};
+
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
 	/* CLK, SYNC */
@@ -3879,6 +3902,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(can0_data_b),
 	SH_PFC_PIN_GROUP(can1_data),
 	SH_PFC_PIN_GROUP(can_clk),
+	SH_PFC_PIN_GROUP(canfd0_data_a),
+	SH_PFC_PIN_GROUP(canfd0_data_b),
+	SH_PFC_PIN_GROUP(canfd1_data),
 	SH_PFC_PIN_GROUP(drif0_ctrl_a),
 	SH_PFC_PIN_GROUP(drif0_data0_a),
 	SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4203,6 +4229,15 @@ static const char * const can_clk_groups[] = {
 	"can_clk",
 };
 
+static const char * const canfd0_groups[] = {
+	"canfd0_data_a",
+	"canfd0_data_b",
+};
+
+static const char * const canfd1_groups[] = {
+	"canfd1_data",
+};
+
 static const char * const drif0_groups[] = {
 	"drif0_ctrl_a",
 	"drif0_data0_a",
@@ -4611,6 +4646,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(can0),
 	SH_PFC_FUNCTION(can1),
 	SH_PFC_FUNCTION(can_clk),
+	SH_PFC_FUNCTION(canfd0),
+	SH_PFC_FUNCTION(canfd1),
 	SH_PFC_FUNCTION(drif0),
 	SH_PFC_FUNCTION(drif1),
 	SH_PFC_FUNCTION(drif2),
-- 
2.12.2

Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Add CAN FD support

[Geert Uytterhoeven]

On Fri, Nov 10, 2017 at 2:58 PM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
> This patch adds CAN FD[0-1] pinmux support for R-Car H3 ES2.0. The pin
> config is identical to H3 ES1.*.
>
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
I.e. will queue in sh-pfc-for-v4.16.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds