* [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down
@ 2025-02-05 10:01 Claudiu
2025-02-05 11:27 ` Lad, Prabhakar
2025-02-11 8:37 ` Geert Uytterhoeven
0 siblings, 2 replies; 3+ messages in thread
From: Claudiu @ 2025-02-05 10:01 UTC (permalink / raw)
To: geert+renesas, linus.walleij
Cc: claudiu.beznea, linux-renesas-soc, linux-gpio, linux-kernel,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The Renesas RZ/G3S supports a power-saving mode where power to most of the
SoC components is lost, including the PIN controller. Save and restore the
pull-up/pull-down register contents to ensure the functionality is
preserved after a suspend/resume cycle.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 4fae24453c11..7eb91ac5ba42 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -318,6 +318,7 @@ struct rzg2l_pinctrl_pin_settings {
* @pmc: PMC registers cache
* @pfc: PFC registers cache
* @iolh: IOLH registers cache
+ * @pupd: PUPD registers cache
* @ien: IEN registers cache
* @sd_ch: SD_CH registers cache
* @eth_poc: ET_POC registers cache
@@ -331,6 +332,7 @@ struct rzg2l_pinctrl_reg_cache {
u32 *pfc;
u32 *iolh[2];
u32 *ien[2];
+ u32 *pupd[2];
u8 sd_ch[2];
u8 eth_poc[2];
u8 eth_mode;
@@ -2712,6 +2714,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
if (!cache->ien[i])
return -ENOMEM;
+ cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]),
+ GFP_KERNEL);
+ if (!cache->pupd[i])
+ return -ENOMEM;
+
/* Allocate dedicated cache. */
dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
sizeof(*dedicated_cache->iolh[i]),
@@ -2953,7 +2960,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
for (u32 port = 0; port < nports; port++) {
- bool has_iolh, has_ien;
+ bool has_iolh, has_ien, has_pupd;
u32 off, caps;
u8 pincnt;
u64 cfg;
@@ -2965,6 +2972,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
caps = FIELD_GET(PIN_CFG_MASK, cfg);
has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
has_ien = !!(caps & PIN_CFG_IEN);
+ has_pupd = !!(caps & PIN_CFG_PUPD);
if (suspend)
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
@@ -2983,6 +2991,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
}
}
+ if (has_pupd) {
+ RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
+ cache->pupd[0][port]);
+ if (pincnt >= 4) {
+ RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
+ cache->pupd[1][port]);
+ }
+ }
+
RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down
2025-02-05 10:01 [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down Claudiu
@ 2025-02-05 11:27 ` Lad, Prabhakar
2025-02-11 8:37 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Lad, Prabhakar @ 2025-02-05 11:27 UTC (permalink / raw)
To: Claudiu
Cc: geert+renesas, linus.walleij, linux-renesas-soc, linux-gpio,
linux-kernel, Claudiu Beznea
On Wed, Feb 5, 2025 at 10:13 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S supports a power-saving mode where power to most of the
> SoC components is lost, including the PIN controller. Save and restore the
> pull-up/pull-down register contents to ensure the functionality is
> preserved after a suspend/resume cycle.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 4fae24453c11..7eb91ac5ba42 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -318,6 +318,7 @@ struct rzg2l_pinctrl_pin_settings {
> * @pmc: PMC registers cache
> * @pfc: PFC registers cache
> * @iolh: IOLH registers cache
> + * @pupd: PUPD registers cache
> * @ien: IEN registers cache
> * @sd_ch: SD_CH registers cache
> * @eth_poc: ET_POC registers cache
> @@ -331,6 +332,7 @@ struct rzg2l_pinctrl_reg_cache {
> u32 *pfc;
> u32 *iolh[2];
> u32 *ien[2];
> + u32 *pupd[2];
> u8 sd_ch[2];
> u8 eth_poc[2];
> u8 eth_mode;
> @@ -2712,6 +2714,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
> if (!cache->ien[i])
> return -ENOMEM;
>
> + cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]),
> + GFP_KERNEL);
> + if (!cache->pupd[i])
> + return -ENOMEM;
> +
> /* Allocate dedicated cache. */
> dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
> sizeof(*dedicated_cache->iolh[i]),
> @@ -2953,7 +2960,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
> struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
>
> for (u32 port = 0; port < nports; port++) {
> - bool has_iolh, has_ien;
> + bool has_iolh, has_ien, has_pupd;
> u32 off, caps;
> u8 pincnt;
> u64 cfg;
> @@ -2965,6 +2972,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
> caps = FIELD_GET(PIN_CFG_MASK, cfg);
> has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
> has_ien = !!(caps & PIN_CFG_IEN);
> + has_pupd = !!(caps & PIN_CFG_PUPD);
>
> if (suspend)
> RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
> @@ -2983,6 +2991,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
> }
> }
>
> + if (has_pupd) {
> + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
> + cache->pupd[0][port]);
> + if (pincnt >= 4) {
> + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
> + cache->pupd[1][port]);
> + }
> + }
> +
> RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
> RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
>
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down
2025-02-05 10:01 [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down Claudiu
2025-02-05 11:27 ` Lad, Prabhakar
@ 2025-02-11 8:37 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2025-02-11 8:37 UTC (permalink / raw)
To: Claudiu
Cc: linus.walleij, linux-renesas-soc, linux-gpio, linux-kernel,
Claudiu Beznea
On Wed, 5 Feb 2025 at 11:01, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S supports a power-saving mode where power to most of the
> SoC components is lost, including the PIN controller. Save and restore the
> pull-up/pull-down register contents to ensure the functionality is
> preserved after a suspend/resume cycle.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2025-02-05 10:01 [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down Claudiu
2025-02-05 11:27 ` Lad, Prabhakar
2025-02-11 8:37 ` Geert Uytterhoeven
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