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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id i130-20020a0ddf88000000b0056d51c39c1fsm291307ywe.23.2023.09.14.05.18.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 05:18:59 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id 3f1490d57ef6-d801c83325fso936861276.0; Thu, 14 Sep 2023 05:18:58 -0700 (PDT) X-Received: by 2002:a25:7497:0:b0:d78:3a4e:c19e with SMTP id p145-20020a257497000000b00d783a4ec19emr5260394ybc.24.1694693938512; Thu, 14 Sep 2023 05:18:58 -0700 (PDT) MIME-Version: 1.0 References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> <20230912045157.177966-9-claudiu.beznea.uj@bp.renesas.com> <8490f909-c0ad-5a6d-7a97-03c80a8b47ba@omp.ru> In-Reply-To: <8490f909-c0ad-5a6d-7a97-03c80a8b47ba@omp.ru> From: Geert Uytterhoeven Date: Thu, 14 Sep 2023 14:18:44 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 08/37] clk: renesas: rzg2l: trust value returned by hardware To: Sergey Shtylyov Cc: Claudiu , mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Tue, Sep 12, 2023 at 6:43 PM Sergey Shtylyov wrote: > On 9/12/23 7:51 AM, Claudiu wrote: > > > From: Claudiu Beznea > > > > Initial value of CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. Hardware user's > > manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is > > prohibited. The rzg2l_cpg_sd_clk_mux_get_parent() should just read > > CPG_PL2SDHI_DSEL, trust the value and return the proper clock parent index > > based on the read value. Do this. > > > > Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") > > Signed-off-by: Claudiu Beznea > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -239,14 +239,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) > > > > val >>= GET_SHIFT(hwdata->conf); > > val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); > > - if (val) { > > - val--; > > - } else { > > - /* Prohibited clk source, change it to 533 MHz(reset value) */ > > - rzg2l_cpg_sd_clk_mux_set_parent(hw, 0); > > - } > > > > - return val; > > + return val ? --val : val; > > return val ? val - 1 : 0; Definitely, mixing multiple users of the same variable and pre-decrement is ill-defined. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds