From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01113E7AD6E for ; Tue, 3 Oct 2023 15:15:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229713AbjJCPPL convert rfc822-to-8bit (ORCPT ); Tue, 3 Oct 2023 11:15:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231248AbjJCPPK (ORCPT ); Tue, 3 Oct 2023 11:15:10 -0400 Received: from mail-yb1-f177.google.com (mail-yb1-f177.google.com [209.85.219.177]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5409AC9; Tue, 3 Oct 2023 08:15:07 -0700 (PDT) Received: by mail-yb1-f177.google.com with SMTP id 3f1490d57ef6-d89ba259964so1083560276.2; Tue, 03 Oct 2023 08:15:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696346106; x=1696950906; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cNhSWAJYWgEDGwtiwjiH8QlfR14j4fmvgyQzNmxJTSU=; b=hTTSn+f/bb+WTxFkvDp05w1vE/lXlwsWqeqPT4+qH/40lO/BCZJctOJGZYFqmWQ9tM /s+xSAGesrsVct28+zPj5ZVDwZl6Z7QotY+zEusjU4/H0Wi02H8eampKA//fh82nBTwl PRUbFloArUCcI2w9oE0VjOz3/R1qh8lk7hxmd7xLo8XL6Lv0Tq2lxkst1covBvYTSbs8 k5EXDJabrOFHiVASeWKGbZE0241i4l7DC9d/4h4OgpcfO9TCkBvo7KYhE3sOVj5CliXR g9v9QoEV7neziIzvzx8xtH2OeC3lLDmrWo/FzhGkHNAebd+MtCzMis+Tuvi4RnKwKQqV qpfg== X-Gm-Message-State: AOJu0YwM3wBS5ogjM6gVmTRIwzvk2yYQZGck5crEgDviBwdVqCJwngS8 ErDWM80uVMgWIWnUPxGeRif1okY9SFBn2w== X-Google-Smtp-Source: AGHT+IExJlaND/bKWaUuUpX2KdLNm1zvoB5Wk69ljUOGH9ijRnq7wIvdjSmpFe3169JwdwbYzwC47A== X-Received: by 2002:a25:941:0:b0:d89:4343:a0a5 with SMTP id u1-20020a250941000000b00d894343a0a5mr13217297ybm.42.1696346106075; Tue, 03 Oct 2023 08:15:06 -0700 (PDT) Received: from mail-yb1-f174.google.com (mail-yb1-f174.google.com. [209.85.219.174]) by smtp.gmail.com with ESMTPSA id a9-20020a259389000000b00d8128f9a46bsm449515ybm.37.2023.10.03.08.15.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Oct 2023 08:15:04 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id 3f1490d57ef6-d8181087dc9so1082657276.3; Tue, 03 Oct 2023 08:15:04 -0700 (PDT) X-Received: by 2002:a25:c791:0:b0:d81:6e88:7cb3 with SMTP id w139-20020a25c791000000b00d816e887cb3mr14108080ybe.47.1696346103886; Tue, 03 Oct 2023 08:15:03 -0700 (PDT) MIME-Version: 1.0 References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> <20230929053915.1530607-3-claudiu.beznea@bp.renesas.com> In-Reply-To: <20230929053915.1530607-3-claudiu.beznea@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 3 Oct 2023 17:14:51 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 02/28] clk: renesas: rzg2l: wait for status bit of SD mux before continuing To: Claudiu Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Fri, Sep 29, 2023 at 7:39 AM Claudiu wrote: > From: Claudiu Beznea > > Hardware user manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, > chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching > Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for > SD clock switching status. > > Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") > Signed-off-by: Claudiu Beznea > --- > > Changes in v2: > - initialized msk Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-clk-for-v6.7. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds