From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 904D5C6FA86 for ; Mon, 19 Sep 2022 14:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230144AbiISOck (ORCPT ); Mon, 19 Sep 2022 10:32:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbiISOc2 (ORCPT ); Mon, 19 Sep 2022 10:32:28 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82CBF32EDB; Mon, 19 Sep 2022 07:32:10 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id z25so47296258lfr.2; Mon, 19 Sep 2022 07:32:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=fbOtVx32xD0An1BP4gF5wsbpUuDHf0RuAIKgzeGlyw8=; b=oCY3SQQ06GI1T0nc3vcegfw92SJwkc8GhNmDuFea6YzJroQA1iJ/C0VGdrJSgUz9jx mApqMR+9XBUm/uurHE2l+5JQHn2ITXWeQV9bcFU0CNL9s/AsShY84T7chTNmXJLWe4wu WCP+4EKr9Nr34D7du1LtLHoiWh7Br/ERUuvDz1gBnykah2JOscL2r/aUjHsOHwb9ltbJ la5S4xmdhcWePibJaIj099rNjvZPOikrYSFMzzIMFFgI8RfwnlpHlXHB52MRUmJUBjs+ SdqxwySj5lN9Am7atnFcJv1SQm1DdpFDiYichNtnI6qxbj8CBO8UxKyxH1InjVj1eEj4 8Rzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=fbOtVx32xD0An1BP4gF5wsbpUuDHf0RuAIKgzeGlyw8=; b=Lt1D4qLYnzvhgfZDUFcwtSDGcX4eTXghxl/bK7NF3aAsvIBA0fd/Flr76bm+Us3/dh F2uoFk6aw6BjNPdStZL5UXzzstS8/eKWAYPC+XxTLLukIPCImAlMwr/v4XNVoAJBT8mF Y4OZhg8WscoiWaCHx1kt0lZHv9WFnb+ZQFqXGPIN03meJTy/SdaM34YNyXD2AHckHKxX r3j79qIJL7yphWMhzOQqLekwDuutH0uLsZXaY706e3xn8tTB6OYbsv0jlP1yiDgzdN6G 3ADC1Q+agPsjLjWi2v1bP4jzoPBuyZCVAhDpoB6tjQOe1zq3J8vajArI2Z8BP6cGd8Qg VxfQ== X-Gm-Message-State: ACrzQf1CI2oYgSVCzHkXDk6+n7xSleC06/HaGhfmJ1Y769SRwLq6tdTB 0IBaQcDMV91qkmV1LG9gF50x5vo2tzAhdtFrQNg= X-Google-Smtp-Source: AMsMyM4TvhQ+C6HD/ZV0YS/n8Apo8lVG6faXAtccFQUMj9KOsAXpl4UCFWGvBlxtGV9MQYWcekd+O4B2UpHaNWuzNlw= X-Received: by 2002:a05:6512:eaa:b0:497:a1ed:6fa5 with SMTP id bi42-20020a0565120eaa00b00497a1ed6fa5mr6073634lfb.108.1663597928023; Mon, 19 Sep 2022 07:32:08 -0700 (PDT) MIME-Version: 1.0 References: <20220714122322.63663-1-tmaimon77@gmail.com> <20220714122322.63663-2-tmaimon77@gmail.com> <20220718211046.GA3547663-robh@kernel.org> <3981e6e8-d4bb-b13d-7aaa-7aea83ffaad9@linaro.org> In-Reply-To: <3981e6e8-d4bb-b13d-7aaa-7aea83ffaad9@linaro.org> From: Tomer Maimon Date: Mon, 19 Sep 2022 17:31:56 +0300 Message-ID: Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation To: Krzysztof Kozlowski Cc: Rob Herring , Avi Fishman , Tali Perry , Joel Stanley , Patrick Venture , Nancy Yuen , Benjamin Fair , Linus Walleij , Krzysztof Kozlowski , =?UTF-8?Q?Jonathan_Neusch=C3=A4fer?= , zhengbin13@huawei.com, OpenBMC Maillist , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , devicetree Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Krzysztof, Sorry but I didn't understand, On Mon, 19 Sept 2022 at 09:56, Krzysztof Kozlowski wrote: > > On 18/09/2022 20:28, Tomer Maimon wrote: > > Hi Rob, > > > > Thanks for your comment and sorry for the late reply. > > Two months... we are out of the context and this will not help your > patchset. > > > > > On Tue, 19 Jul 2022 at 00:10, Rob Herring wrote: > >> > > (...) > > >>> +examples: > >>> + - | > >>> + #include > >>> + #include > >>> + > >>> + soc { > >>> + #address-cells = <2>; > >>> + #size-cells = <2>; > >>> + > >>> + pinctrl: pinctrl@f0800000 { > >>> + compatible = "nuvoton,npcm845-pinctrl"; > >>> + ranges = <0x0 0x0 0xf0010000 0x8000>; > >>> + #address-cells = <1>; > >>> + #size-cells = <1>; > >>> + nuvoton,sysgcr = <&gcr>; > >>> + > >>> + gpio0: gpio@f0010000 { > >> > >> gpio@0 > >> > >> Is this really a child block of the pinctrl? Doesn't really look like it > >> based on addressess. Where are the pinctrl registers? In the sysgcr? If > >> so, then pinctrl should be a child of it. But that doesn't really work > >> too well with gpio child nodes... > > the pin controller mux is handled by sysgcr this is why the sysgcr in > > the mother node, > > and the pin configuration are handled by the GPIO registers. each > > GPIO bank (child) contains 32 GPIO. > > this is why the GPIO is the child node. > > Then maybe pinctrl should be the sysgcr and expose regmap for other devices? The pin controller using the sysgcr to handle the pinmux, this is why the sysgcr is in the mother node, is it problematic? > > > Best regards, > Krzysztof Best regards, Tomer