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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id x2sm890433oog.10.2021.06.10.19.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 19:51:43 -0700 (PDT) Date: Thu, 10 Jun 2021 21:51:42 -0500 From: Bjorn Andersson To: Bhupesh Sharma Cc: linux-arm-msm@vger.kernel.org, Linus Walleij , Liam Girdwood , Mark Brown , Vinod Koul , Rob Herring , Andy Gross , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, bhupesh.linux@gmail.com Subject: Re: [PATCH 2/8] dt-bindings: pinctrl: qcom,pmic-gpio: Add compatible for SA8155p-adp Message-ID: References: <20210607113840.15435-1-bhupesh.sharma@linaro.org> <20210607113840.15435-3-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210607113840.15435-3-bhupesh.sharma@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Mon 07 Jun 06:38 CDT 2021, Bhupesh Sharma wrote: > Add pmic-gpio compatible strings for pmm8155au_1 and pmm8155au_2 pmics > found on SA8155p-adp board. > > Cc: Linus Walleij > Cc: Liam Girdwood > Cc: Mark Brown > Cc: Bjorn Andersson > Cc: Vinod Koul > Cc: Rob Herring > Cc: Andy Gross > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-gpio@vger.kernel.org > Cc: bhupesh.linux@gmail.com > Signed-off-by: Bhupesh Sharma > --- > Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > index f6a9760558a6..ee4721f1c477 100644 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt > @@ -27,6 +27,8 @@ PMIC's from Qualcomm. > "qcom,pm660l-gpio" > "qcom,pm8150-gpio" > "qcom,pm8150b-gpio" > + "qcom,pmm8155au-1-gpio" > + "qcom,pmm8155au-2-gpio" As with the regulator this seems to be a single component. > "qcom,pm8350-gpio" > "qcom,pm8350b-gpio" > "qcom,pm8350c-gpio" > @@ -116,6 +118,9 @@ to specify in a pin configuration subnode: > and gpio8) > gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7) > gpio1-gpio12 for pm8150l (hole on gpio7) > + gpio1-gpio10 for pmm8155au-1 (holes on gpio2, gpio5, gpio7 > + and gpio8) > + gpio1-gpio10 for pmm8155au-2 (holes on gpio2, gpio5, gpio7) In the schematics all 10 pins are wired on both of these PMICs, so I don't think there are holes. Please omit the comment. Thanks, Bjorn > gpio1-gpio10 for pm8350 > gpio1-gpio8 for pm8350b > gpio1-gpio9 for pm8350c > -- > 2.31.1 >